abov MC96FR116C Series Manuals

Manuals and User Guides for abov MC96FR116C Series. We have 1 abov MC96FR116C Series manual available for free PDF download: User Manual

abov MC96FR116C Series User Manual

abov MC96FR116C Series User Manual (196 pages)

8-BIT MICROCONTROLLERS

Brand: abov | Category: Microcontrollers | Size: 3 MB

Table of Contents

Revision History
2
Table of Contents
5
List of Figures
8
1 Overview

11
- Description
  11
- Features
  11
- Ordering Information
  12
- Figure 1-1 Device Nomenclature
  13
- Development Tools
  14
- Figure 1-2 OCD Software and Connector
  14
- Figure 1-3 OCD Mode Sequence
  15
- Figure 1-4 OCD Interface Circuit
  16
- Figure 1-5 E-PGM
  17
- Figure 1-6 Pgmpluslc-II
  18
- Figure 1-7 Gang Programmer
  18
2 Block Diagram

19
- Figure 2-1 Block Diagram of MC96FR116C
  19
3 Pin Configurations

20
4 Package Dimension

23
5 Pin Description

26
6 Port Structures

27
- General Purpose I/O Port
  27
- Figure 6-1 General I/O
  27
- External Interrupt I/O Port
  28
- Figure 6-2 I/O with External Interrupt Function
  28
- REM_PP_OUT Port
  29
- REM_OD_OUT Port
  29
7 Electrical Characteristics

30
8 Memory

39
- Program Memory
  39
- Figure 8-1 Program Memory
  39
- Iram
  40
- Figure 8-2 DATA MEMORY (IRAM)
  40
- Figure 8-3 Lower 128 Byte of IRAM
  41
- Figure 8-4 PSW Register
  43
- Xram
  44
- Figure 8-5 DATA MEMORY (XRAM)
  44
- Registers
  45
9 I/O Ports

49
- Introduction
  49
- Register Description
  49
10 Interrupt Controller

55
11 Peripheral Units

70
12 Power Management

158
- Overview
  158
- Peripheral Operation in Sleep/Stop/Bod Mode
  158
- SLEEP Mode
  158
- STOP Mode
  159
- Figure 12-1 Wake-Up from SLEEP Mode by an Interrupt
  159
- Figure 12-2 SLEEP Mode Release by an External Reset
  159
- Figure 12-3 Wake-Up from STOP Mode by an Interrupt
  160
- Figure 12-4 STOP Mode Release by an External Reset
  160
- BOD Mode
  161
- Figure 12-5 BOD Mode During Normal Mode
  162
- Figure 12-6 BOD Mode During Stop Mode
  163
- Register Map
  164
- Register Description
  164
- Power Sequence
  164
- Figure 12-7 Power Sequence
  164
13 Reset

165
14 On-Chip Debug System

174
15 FLASH Memory Controller

179
- Overview
  179
- Boot Area
  179
- Register Map
  180
- Figure 15-1 Program Memory Address Space
  180
- Register Description
  181
- Memory Map
  187
- Figure 15-2 FLASH Memory Map
  187
- Figure 15-3 FLASH Memory Address Generation
  187
- Serial In-System Program Mode
  188
- Security
  192
16 Fuse

193
- FUSE Control Register
  193
17 Appendix

194

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