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Abov MC97F6108A User Manual

16 mhz 8-bit microcontroller 8kb flash, 12-bit adc, analog comparator and op-amp
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8KB Flash, 12-bit ADC, Analog Comparator and OP-AMP

Introduction

This user's manual targets application developers who use MC97F6108A for their specific needs. This
document provides complete information of how to use MC97F6108A device. Standard functions and
blocks including corresponding register information of MC97F6108A are introduced in each chapter,
while instruction set is in Appendix.
MC97F6108A is based on M8051 core, and provides standard features of 8051 such as 8-bit ALU, PC,
8-bit registers, timers and counters, serial data communication, PSW, DPTR, SP, 8-bit data bus and
2x16-bit address bus, and 8/11/16-bit operations.
In addition, this device offers highly flexible and cost effective solutions with the following peripherals
inside: 8Kbytes of FLASH, 256bytes of IRAM, 256bytes of XRAM, General Purpose I/Os, Basic Interval
Timer, Watchdog Timer, 16-bit timer/counter, 16-bit PWM output, 16-bit PPG output, UART, I2C, 12-bit
A/D Converter, analog comparator, on-chip OP-AMP, buzzer driving port, on-chip POR, LVR, BOD, on-
chip oscillator and clock circuitry.
As a field proven best seller, MC97F6108A has been sold more than 3 billion units up to now, and
introduces rich features such as excellent noise immunity, code optimization, cost effectiveness, and
so on.

Reference document

MC97F6108A programming tools and manuals released by ABOV: They are available at
ABOV website, www.abovsemi.com.
SDK-51 User's guide (System Design Kit) released by Intel in 1982: It contains all of
components of a single-board computer based on Intel's 8051 single-chip microcomputer.
Information on Mentor Graphics 8051 microcontroller: The technical document is provided at
Mentor website:
https://www.mentor.com/products/ip/peripheral/microcontroller/
Global Top Smart MCU Innovator
www.abovsemi.com
MC97F6108A
User's Manual
16 MHz 8-bit Microcontroller
User's Manual Version 1.12

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Summary of Contents for Abov MC97F6108A

  • Page 1: Introduction

    A/D Converter, analog comparator, on-chip OP-AMP, buzzer driving port, on-chip POR, LVR, BOD, on- chip oscillator and clock circuitry. As a field proven best seller, MC97F6108A has been sold more than 3 billion units up to now, and introduces rich features such as excellent noise immunity, code optimization, cost effectiveness, and so on.

  • Page 2: Table Of Contents

    Contents Introduction.............................. 1 Reference document ..........................1 Description ........................... 12 Device overview ........................ 12 MC97F6108A block diagram ..................... 14 Pinouts and pin description ......................15 Pinouts ..........................15 Pin description ........................17 Port structures ..........................19 Memory organization ........................22 Program memory.......................
  • Page 3 MC97F6108A User’s manual Contents 6.12.1 Interrupt Enable Register (IE, IE1, IE2, and IE3) ..........57 6.12.2 Interrupt Priority Register (IP, IPH, IP1, IP1H, IP2, IP2H, IP3 and IP3H) .... 57 6.12.3 External Interrupt Flag Enable Register (EIENAB) ..........57 6.12.4 External Interrupt Flag Register (EIFLAG) ............57 6.12.5 External Interrupt Flag Edge Register (EIEDGE) ..........
  • Page 4 Contents MC97F6108A User’s manual 11.8.2 PPG period when ATPSEL = 2'b00 ..............105 11.8.3 PPG period when ATPSEL = 2'b01 ..............106 11.8.4 PPG period when ATPSEL = 2'b1x ..............107 11.8.5 PPG period when writing ..................109 11.8.6 PPG period min/max limitation ................111 11.8.7 PPG off-time max/min limitation .................
  • Page 5 MC97F6108A User’s manual Contents 16.5 Acknowledge ........................171 16.6 Synchronization/ arbitration ..................... 172 16.7 Block Operation ....................... 173 16.7.1 I2C block initialization process ................174 16.7.2 I2C interrupt service ................... 175 16.7.3 Master transmitter ....................176 16.7.4 Slave receiver ..................... 178 16.8...
  • Page 6 Contents MC97F6108A User’s manual 20.10 DC characteristics ......................224 20.11 AC characteristics ......................225 20.12 Analog comparator characteristics .................. 226 20.13 Operational amplifier characteristics ................226 20.14 USART characteristics ....................227 20.15 SPI characteristics......................228 20.16 I2C characteristics ......................229 20.17 Data retention voltage in STOP mode ................
  • Page 7 List of figures List of figures Figure 1. MC97F6108A Block Diagram ....................14 Figure 2. MC97F6108A 20 SOP Pin Assignment ................. 15 Figure 3. MC97F6108A 16 SOPN Pin Assignment ................16 Figure 4. General Purpose I/O Port ...................... 19 Figure 5. Secondary Function I/O Port ....................20 Figure 6.
  • Page 8 List of figures MC97F6108A User’s manual Figure 49. Auto Period Mode Block Diagram (ATPSEL = 2'b1x) ............107 Figure 50. Auto Period Mode (ATPSEL = 2'b1x) ................108 Figure 51. PPG Period Block Diagram When Writing ................. 109 Figure 52. PPG Period When Writing (ATPSEL = 2'b1x) ..............110 Figure 53.
  • Page 9 Figure 119. 20 SOP Package Outline ....................235 Figure 120. 16 SOPN Package Outline ....................236 Figure 121. MC97F6108A Device Numbering Nomenclature ............. 237 Figure 122. Debugger (OCD1/OCD2) and Pinouts ................239 Figure 123. E-PGM+ (Single Writer) and Pinouts ................239 Figure 124.
  • Page 10 List of tables MC97F6108A User’s manual List of tables Table 1. MC97F6108A Device Features and Peripheral Counts ............12 Table 2. Normal Pin Description ......................17 Table 3. SFR Map Summary ......................... 27 Table 4. XSFR Map Summary ......................28 Table 5.
  • Page 11 Table 54. Data Retention Voltage in STOP Mode ................230 Table 55. Internal Flash ROM Characteristics ..................231 Table 56. Input/Output Capacitance ....................231 Table 57. MC97F6108A Device Ordering Information ................ 237 Table 58. Pins for Flash Programming ....................241 Table 59. OCD II Features ........................243 Table 60.

  • Page 12: Description

    1. Description MC97F6108A User’s manual Description MC97F6108A is an advanced CMOS 8-bit microcontroller with 8Kbytes of FLASH. This is a powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. Device overview In this section, features of MC97F6108A and peripheral counts are introduced.
  • Page 13 MC97F6108A User’s manual 1. Description Table 1. MC97F6108A Device Features and Peripheral Counts (continued) Peripherals Description General Purpose I/O (GPIO) 20 SOP Normal I/O : 18 ports  — P0[7:0], P1[7:0], P2[1:0] 16 SOPN Normal I/O : 14 ports ...

  • Page 14: Mc97F6108A Block Diagram

    1. Description MC97F6108A User’s manual MC97F6108A block diagram In this section, MC97F6108A device with peripherals are described in a block diagram. Flash 8 KB CORE M8051 XRAM 256 B IRAM 256 B General purpose I/O 18 ports normal I/O (with analog input)

  • Page 15: Pinouts And Pin Description

    MC97F6108A User’s manual 2. Pinouts and pin description Pinouts and pin description In this chapter, MC97F6108A device pinouts and pin descriptions are introduced. Pinouts RESETB/P00 P21/AMP1I DSDA/AN0/EC1/CMPXO/SCK/XCK/P01 P20/AN5/AMP2O DSCL/AN1/EINT0/SS/P02 P17/AN7/AVREF/(AMP1O) AN2/EINT1/SDA/MISO/RXD/P03 P16/CMP0_IN_N AN3/EINT2/SCL/MOSI/TXD/P04 P15/CMP0_IN_P PPGO/PWM3O/T3O/P05 P14/CMP2_IN_P AN4/PWM1O/T1O/P06 P13/CMP1_IN_P TPPGO/BUZO/PWM0O/T0O/P07 P12/DSDA1...

  • Page 16: Figure 3. Mc97F6108A 16 Sopn Pin Assignment

    When using 16-pin products, it is recommended that configure internal pull-up to the floating pin in order to prevent current consumption. Programmer (E-PGM+, E-Gang4/6) uses P0[1:2] pin as DSCL, DSDA. The second functions of DSDA and DSCL port are not supported in OCD mode. (EC1, XCK, EINT0). Figure 3. MC97F6108A 16 SOPN Pin Assignment...

  • Page 17: Pin Description

    MC97F6108A User’s manual 2. Pinouts and pin description Pin description Table 2. Normal Pin Description Pin no. PIN Name Description Remark 20 SOP 16 SOPN P00* IOUS Port 0 bit 0 Input/output RSTB Reset pin Pull-up P01* IOUS Port 0 bit 1 Input/output...
  • Page 18 2. Pinouts and pin description MC97F6108A User’s manual Table 2. Normal Pin Description (continued) Pin no. PIN Name Description Remark 20 SOP 16 SOPN Timer 2 interval output ADC input ch-6 P11* IOUS Port 1 bit 1 Input/output DSCL1 OCD debugger clock...

  • Page 19: Port Structures

    MC97F6108A User’s manual 3. Port structures Port structures In this chapter, two port structures are introduced in figures 1, 2 and 3 regarding general purpose I/O port and external interrupt I/O port respectively. Level Shift (ExtVDD to 1.8V) Level Shift (1.8V to ExtVDD)

  • Page 20: Figure 5. Secondary Function I/O Port

    3. Port structures MC97F6108A User’s manual Level Shift (ExtVDD to 1.8V) Level Shift (1.8V to ExtVDD) SUB-FUNC ENABLE OPEN-DRAIN REGISTER DATA REGISTER SUB-FUNC DATA OUTPUT SUB-FUNC DIRECTION DIRECTION REGISTER PORTx INPUT Schmitt Level Input SUB-FUNC DATA INPUT PULL-UP REGISTER * If one sub-function is selected, the direction of the sub-function is applied to the port automatically.

  • Page 21: Figure 6. Analog Input I/O Port

    MC97F6108A User’s manual 3. Port structures Level Shift (ExtVDD to 1.8V) Level Shift (1.8V to ExtVDD) OPEN-DRAIN REGISTER DATA REGISTER DIRECTION REGISTER Schmitt Level Input PORTx INPUT Digital Input blocking enable Analog Channel enable ANALOG INPUT PULL-UP REGISTER Figure 6. Analog Input I/O Port...

  • Page 22: Memory Organization

    16-bit Data Memory address is generated through the DPTR register. MC97F6108A provides on-chip 8Kbytes of the ISP type flash program memory, which readable and writable. Internal data memory (IRAM) is 256bytes and it includes the stack area. External data memory...

  • Page 23: Program Memory

    MC97F6108A User’s manual 4. Memory organization Program memory A 16-bit program counter is capable of addressing up to 64Kbytes, and MC97F6108A has just 8Kbytes program memory space. Figure 7 shows a map of the lower part of the program memory.

  • Page 24: Data Memory

    4. Memory organization MC97F6108A User’s manual Data memory Internal data memory space is divided into three blocks, which are generally referred to as lower 128bytes, upper 128bytes, and SFR space. Internal data memory addresses are always one byte wide, which implies an address space of 256bytes. In fact, the addressing modes for the internal data memory can accommodate up to 384bytes by using a simple trick.

  • Page 25: Figure 9. Lower 128Bytes Of Ram

    MC97F6108A User’s manual 4. Memory organization 7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70 6F 6E 6D 6C 6B 6A 69 68 67 66 65 64 63 62 61 60 5F 5E 5D 5C 5B 5A 59 58...

  • Page 26: External Data Memory

    4. Memory organization MC97F6108A User’s manual External data memory MC97F6108A has 256bytes of XRAM and 256bytes of XSFR. This area has no relation with RAM/FLASH. It can be read and written to through SFR with 8-bit unit. 2FFFH Extended Special Function Registers...

  • Page 27: Sfr Mapd

    MC97F6108A User’s manual 4. Memory organization SFR mapd 4.4.1 SFR map summary Table 3. SFR Map Summary ― Reserved M8051 compatible 00H/8H 01H/9H 02H/0AH 03H/0BH 04H/0CH 05H/0DH 06H/0EH 07H/0FH 0F8H ― ATPCR UCTRL1 UCTRL2 UCTRL3 USTAT UBAUD UDATA 0F0H ATPHR...

  • Page 28: Table 4. Xsfr Map Summary

    4. Memory organization MC97F6108A User’s manual Table 4. XSFR Map Summary 00H/8H 01H/9H 02H/0AH 03H/0BH 04H/0CH 05H/0DH 06H/0EH 07H/0FH 2F78H ― ― ― ― ― ― ― ― 2F70H ― ― ― ― ― ― ― ― 2F68H ― ―...

  • Page 29: Sfr Map

    MC97F6108A User’s manual 4. Memory organization 4.4.2 SFR map Table 5. SFR Map Address Function Symbol @Reset P0 Data Register Stack Pointer Data Pointer Register Low Data Pointer Register High Data Pointer Register Low 1 DPL1 Data Pointer Register High 1...
  • Page 30 4. Memory organization MC97F6108A User’s manual Table 5. SFR Map (continued) Address Function Symbol @Reset External Interrupt Flag Polarity Register EIPOLA – – – – – External Interrupt Flag Both Edge Enable EIBOTH – – – – – Register Interrupt Enable Register –...
  • Page 31 MC97F6108A User’s manual 4. Memory organization Table 5. SFR Map (continued) Address Function Symbol @Reset Timer 2 Register Low Capture 2 Data Register Low CDR2L PWM 2 Duty Register Low PWM2DRL Timer 2 Register High Capture 2 Data Register High...
  • Page 32 4. Memory organization MC97F6108A User’s manual Table 5. SFR Map (continued) Address Function Symbol @Reset PPG Control Register PPGCR – PPG Control Register 1 PPGCR1 – – – – PPG Duty Register Low PPGDL PPG Duty Register High PPGDH PPG Period Register Low...

  • Page 33: Table 6. Xsfr Map

    MC97F6108A User’s manual 4. Memory organization Table 6. XSFR Map Address Function Symbol @Reset 2F00H P0 Pull-up Resistor Selection Register P0PU 2F01H P0 Open-drain Selection Register P0OD 2F02H P0 De-bounce Enable Register P0DB 2F04H Auto Period Mode Max Period Low...

  • Page 34: Compiler Compatible Sfr

    4. Memory organization MC97F6108A User’s manual 4.4.3 Compiler compatible SFR ACC (Accumulator Register): E0H Initial value: 00H Accumulator B (B Register): F0H Initial value: 00H B Register SP (Stack Pointer): 81H Initial value: 07H Stack Pointer DPL (Data Pointer Register Low): 82H...
  • Page 35 MC97F6108A User’s manual 4. Memory organization DPH1 (Data Pointer Register High 1): 85H DPH1 Initial value: 00H DPH1 Data Pointer High 1 PSW (Program Status Word Register): D0H Initial value: 00H Carry Flag Auxiliary Carry Flag General Purpose User-Definable Flag...

  • Page 36: O Ports

    MC97F6108A User’s manual I/O ports MC97F6108A has three groups of I/O ports (P0 ~ P2). Each port can be easily configured by software as I/O pin, internal pull up and open-drain pin to meet various system configurations and design requirements. P1 includes a function that can generate interrupt signals according to state of a pin.

  • Page 37: Register Map

    MC97F6108A User’s manual 5. I/O ports 5.1.7 Register map Table 7. Port Register Map Name Address Direction Default Description P0 Data Register P0IO P0 Direction Register P0PU 2F00H P0 Pull-up Resistor Selection Register P0OD 2F01H P0 Open-drain Selection Register P0DB...

  • Page 38: P0 Port

    5. I/O ports MC97F6108A User’s manual P0 port 5.2.1 P0 port description P0 is an 8-bit I/O port. P0 control registers consist of P0 data register (P0), P0 direction register (P0IO), debounce enable register (P0DB), P0 pull-up resistor selection register (P0PU), and P0 open-drain selection register (P0OD).
  • Page 39 MC97F6108A User’s manual 5. I/O ports P0DB (P0 De-bounce Enable Register): 2F02H P07DB P06DB P05DB P04DB P03DB P02DB P01DB P00DB Initial value: 00H P0DB[7:0] Configure De-bounce of P0 Port Disable Enable NOTE: Debounce time of each ports are 1/2/4/8us NOTES: If the same level is not detected on enabled pin three or four times in a row at the sampling clock, the signal is eliminated as noise.
  • Page 40 5. I/O ports MC97F6108A User’s manual PSR2 (Analog I/O port Selection Register): 2F4AH PSR27 PSR26 PSR25 PSR24 PSR23 PSR22 PSR21 PSR20 Initial value: 00H PSR27 P1[7] Analog Input selection register P1[7] digital input (default) P1[7] AIN[7] input PSR26 P1[0] Analog Input selection register...
  • Page 41 MC97F6108A User’s manual 5. I/O ports PSR3 (Analog I/O port Selection Register): 2F4BH PSR35 PSR34 PSR33 PSR32 PSR31 Initial value: 00H PSR35 P2[1] Analog Input selection register P2[1] digital input (default) P2[1] AMP1I input PSR34 P1[6] Analog Input selection register...

  • Page 42: P1 Port

    5. I/O ports MC97F6108A User’s manual P1 port 5.3.1 P1 port description P1 is an 8-bit I/O port. P1 control registers consist of P1 data register (P1), P1 direction register (P1IO), debounce enable register (P15DB), P1 pull-up resistor selection register (P1PU), and P1 open-drain selection register (P1OD).
  • Page 43 MC97F6108A User’s manual 5. I/O ports P1DB (P1 De-bounce Enable Register): 2F0AH P17DB P16DB P15DB P14DB P13DB P12DB P11DB P10DB Initial value: 00H P1DB[7:0] Configure De-bounce of P1 Port Disable Enable NOTES: If the same level is not detected on enabled pin three or four times in a row at the sampling clock, the signal is eliminated as noise.

  • Page 44: P2 Port

    5. I/O ports MC97F6108A User’s manual P2 port 5.4.1 P2 port description P2 is a 2-bit I/O port. P2 control registers consist of P2 data register (P2), P2 direction register (P2IO), P2 pull-up resistor selection register (P2PU) andP2 open-drain selection register (P2OD).Refer to the port function selection registers for the P2 function selection.
  • Page 45 MC97F6108A User’s manual 5. I/O ports P2DB (P2 De-bounce Enable Register): 2F02H P21DB P20DB Initial value: 00H P2DB[1:0] Configure de-bounce of P2 port Disable Enable...

  • Page 46: Interrupt Controller

    The EA bit is always cleared to ‘0’ jumping to an interrupt service vector and set to ‘1’ executing the [RETI] instruction. The MC97F6108A supports a four-level priority scheme. Each maskable interrupt is individually assigned to one of four...

  • Page 47: Figure 11. Interrupt Group Priority Level

    MC97F6108A User’s manual 6. Interrupt controller Default interrupt mode is level-trigger mode basically, but if needed, it is possible to change to edge- trigger mode. Figure 11 shows the Interrupt Group Priority Level that is available for sharing interrupt priority. Priority of a group is set by two bits of interrupt priority registers (one bit from IPx, another one from IPxH).

  • Page 48: External Interrupt

    6. Interrupt controller MC97F6108A User’s manual External interrupt External interrupts on EINT0, EINT1 and EINT2 pins receive various interrupt requests depending on the external interrupt edge register (EIEDGE) and external interrupt polarity (EIPOLA). Each external interrupt source has enable/disable bits.

  • Page 49: Comparator Interrupt And Comparator Flag

    MC97F6108A User’s manual 6. Interrupt controller Comparator Interrupt and Comparator Flag Comparator output interrupt also receive various interrupt request depending on the CIEDGE (Comparator Interrupt Edge register) and CIPOLA (Comparator Interrupt Polarity register). Each comparator interrupt source has control setting bits. The CIFLAG (Comparator interrupt flag register) provides the status of each interrupts.

  • Page 50: Block Diagram

    6. Interrupt controller MC97F6108A User’s manual Block diagram IP3[9E IP3H[9F IP2[9C IP2H[9D IP1[9A IP1H[9B EIEDGE[A5 IE[A8 IP[92 IPH[93 EIPOLA[A6 EIBOTH[A7 EIFLAG.0 [A4 EINT0 FLAG0 EIFLAG.1 [A4 Priority High EINT1 FLAG1 EIFLAG.2 [A4 EINT2 FLAG2 EIFLAG.3 [A4 FLAG3 ATPCR.6 [F9 ATP_MIN ATP_MIN ATPCR.7 [F9...

  • Page 51: Interrupt Vector Table

    6. Interrupt controller Interrupt vector table Interrupt controller of MC97F6108A supports 23 interrupt sources as shown in Table 8. When interrupt is served, long call instruction (LCALL) is executed and program counter jumps to the vector address. All interrupt requests have their own priority order.

  • Page 52: Interrupt Sequence

    6. Interrupt controller MC97F6108A User’s manual Interrupt sequence An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to ‘0’ by a reset or an instruction. Interrupt acceptance always generates at last cycle of the instruction. So instead of fetching the current instruction, CPU executes internally LCALL instruction and saves the PC at stack.

  • Page 53: Effective Timing After Controlling Interrupt Bit

    MC97F6108A User’s manual 6. Interrupt controller Effective timing after controlling interrupt bit Case A in Figure 16 shows the effective time after controlling Interrupt Enable Registers (IE, IE1, IE2, and IE3). Interrupt Enable Register command After executing IE set/clear, enable register is effective.

  • Page 54: Multi-Interrupt

    6. Interrupt controller MC97F6108A User’s manual Multi-interrupt If two requests of different priority levels are received simultaneously, the request of higher priority level is served first. If more than one interrupt request are received, the interrupt polling sequence determines which request is served first by hardware. However, for special features, multi-interrupt processing can be executed by software.

  • Page 55: Interrupt Enable Accept Timing

    MC97F6108A User’s manual 6. Interrupt controller Interrupt enable accept timing System Max. 4 Machine Cycle 4 Machine Cycle Clock Interrupt goes Interrupt Interrupt Processing active latched Interrupt Routine : LCALL & LJMP Figure 19. Interrupt Response Timing Diagram Interrupt service routine address...

  • Page 56: Interrupt Timing

    6. Interrupt controller MC97F6108A User’s manual 6.11 Interrupt timing Interrupt sampled here CLP2 CLP1 CLP2 C1P1 C1P2 C2P1 C2P2 SCLK INT_SRC INTR_ACK LAST_CYC INTR_LCALL 8-bit interrupt Vector INT_VEC PROGA NOTE: Variable x and n of a command cycle CnPn imply the followings: ...

  • Page 57: Interrupt Register Overview

    MC97F6108A User’s manual 6. Interrupt controller 6.12 Interrupt register overview 6.12.1 Interrupt Enable Register (IE, IE1, IE2, and IE3) Interrupt enable register consists of global interrupt control bit (EA) and peripheral interrupt control bits. Total 23 peripherals are able to control interrupt.

  • Page 58: Comparator Interrupt Flag Enable Register (Cienab)

    6. Interrupt controller MC97F6108A User’s manual 6.12.8 Comparator Interrupt Flag Enable Register (CIENAB) Comparator Interrupt Flag Enable Register (CIENAB) determined to enable each comparator (comparator0 to comparator4) interrupt to occur by writing ‘1’. Also, these flags can be cleared to disable external interrupt by writing ‘0’...

  • Page 59: Comparator Flag Edge Register (Cfedge)

    MC97F6108A User’s manual 6. Interrupt controller 6.12.15 Comparator Flag Edge Register (CFEDGE) Comparator Interrupt Flag Edge Register (CIEDGE) determined a level or an edge type of comparator (comparator0 to comparator 4) flag. 6.12.16 Comparator Flag Polarity Register (CFPOLA) Comparator Flag Polarity Register (CFPOLA) determines a level type from high and low level or determined an edge type from rising and falling edge of comparator (comparator0 to comparator 4) flag.

  • Page 60: 6.12.19 Register Map

    6. Interrupt controller MC97F6108A User’s manual 6.12.19 Register map Table 9. Interrupt Register Map Name Address Direction Default Description Interrupt Enable Register Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Enable Register 3 Interrupt PriorityRegister Interrupt PriorityRegister High Interrupt PriorityRegister 1...

  • Page 61: 6.12.20 Interrupt Register Description

    MC97F6108A User’s manual 6. Interrupt controller 6.12.20 Interrupt register description IE (Interrupt Enable Register): A8H – INT5E INT4E INT3E INT2E INT1E INT0E – Initial value: 00H Enable or Disable All Interrupt bits All Interrupt disable All Interrupt enable INT5E Enable or Disable ATP_MAX Interrupt...
  • Page 62 6. Interrupt controller MC97F6108A User’s manual IE1 (Interrupt Enable Register 1): A9H – – INT11E INT10E INT9E INT8E INT7E INT6E – – Initial value: 00H INT11E Enable or Disable I2C Interrupt Disable Enable INT10E Enable or Disable Comparator4 Interrupt Disable...
  • Page 63 MC97F6108A User’s manual 6. Interrupt controller IE2 (Interrupt Enable Register 2): AAH –- – INT17E INT16E INT15E INT14E INT13E INT12E – – Initial value: 00H INT17E Enable or Disable Timer 3 Interrupt Disable Enable INT16E Enable or Disable Timer 2 Interrupt...
  • Page 64 6. Interrupt controller MC97F6108A User’s manual IE3 (Interrupt Enable Register 3): ABH – – INT23E INT22E INT21E INT20E INT19E INT18E – – Initial value: 00H INT23E Reserved Disable Enable INT22E Enable or Disable BOD Interrupt Disable Enable INT21E Enable or Disable BIT Interrupt...
  • Page 65 MC97F6108A User’s manual 6. Interrupt controller IP1 (Interrupt Priority Register 1): 9AH – – IP15 IP14 IP13 IP12 IP11 IP10 – – Initial value: 00H IP1H (Interrupt Priority Register 1 High): 9BH – – IP1H5 IP1H4 IP1H3 IP1H2 IP1H1 IP1H0 –...
  • Page 66 6. Interrupt controller MC97F6108A User’s manual IP3H (Interrupt Priority Register 3 High): 9FH – – IP3H5 IP3H4 IP3H3 IP3H2 IP3H1 IP3H0 – – Initial value: 00H IP3[5:0], Select Interrupt Group Priority IP3H[5:0] Each IP3H and IP3 corresponds to INT23~INT18. IP3H...
  • Page 67 MC97F6108A User’s manual 6. Interrupt controller EIFLAG (External Interrupt Flag0 Register): A4H FLAG3 FLAG2 FLAG1 FLAG0 Initial value: 00H EIFLAG0[3:0] When a PCI interrupt or an External Interrupt 0-2 are occurred while EIENAB is set to ‘1’, the flag becomes ‘1’.The flag is cleared only by writing ‘0’...
  • Page 68 6. Interrupt controller MC97F6108A User’s manual EIPOLA (External Interrupt Flag Polarity Register) : A6H POLA2 POLA1 POLA0 Initial value : 0H According to EIEDGE, this register acts differently. If EIEDGE is level type, external interrupt polarity have level value. If EIEDGE is edge type, external interrupt polarity have edge value.
  • Page 69 MC97F6108A User’s manual 6. Interrupt controller CIENAB (Comparator Interrupt Flag Enable Register) : B1H CIENAB4 CIENAB3 CIENAB2 CIENAB1 CIENAB0 Initial value : 00H CIENAB4 Enable or Disable Comparator4 Interrupt Disable Comparator4 interrupt(default) Enable Comparator4 interrupt CIENAB3 Enable or Disable Comparator3 Interrupt...
  • Page 70 6. Interrupt controller MC97F6108A User’s manual CIEDGE (Comparator Interrupt Flag Edge Register) : ADH CIEDGE4 CIEDGE3 CIEDGE2 CIEDGE1 CIEDGE0 Initial value : 00H CIEDGE4 Determines the type of Comparator4 interrupt, edge or level sensitive. Level (default) Edge CIEDGE3 Determines the type of Comparator3 interrupt, edge or level sensitive.
  • Page 71 MC97F6108A User’s manual 6. Interrupt controller CIBOTH (Comparator Interrupt Flag Both Edge Enable Register) : AFH CIBOTH4 CIBOTH3 CIBOTH 2 CIBOTH 1 CIBOTH 0 Initial value : 00H If CIBOTHx is written to ‘1’, the corresponding comparator interrupt is enabled by both edges(no level).
  • Page 72 6. Interrupt controller MC97F6108A User’s manual CFFLAG (Comparator Flag Register) : C8H C4_FLAG C3_FLAG C2_FLAG C1_FLAG C0_FLAG Initial value : 00H When an comparator source is generated and CFENAB is set to '1', the flag is generated. The flag can be cleared by writing a ‘0’ to bit.
  • Page 73 MC97F6108A User’s manual 6. Interrupt controller CFPOLA (Comparator Flag Polarity Register) : B0H CFPOLA4 CFPOLA3 CFPOLA2 CFPOLA1 CFPOLA0 Initial value : 00H According to CFEDGE, this register acts differently. If CFEDGE is level type, comparator flag polarity has level value. If CFEDGE is edge type, comparator flag polarity has edge value.
  • Page 74 6. Interrupt controller MC97F6108A User’s manual PCI (Pin Change Interrupt Enable Register) : 94H PCI7 PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 Initial value : 00H PCI[7] Select PCI interrupt enable or disable of P1[7] Disable (default) Enable PCI[6] Select PCI interrupt enable or disable of P1[6]...

  • Page 75: Clock Generator

    — INTRC OSC/1 (16MHz, default system clock) — INTRC OSC/2 (8MHz) — INTRC OSC/4 (4MHz) — INTRC OSC/8 (2MHz) Clock generator block diagram In this section, a clock generator of MC97F6108A is described in a block diagram. SYSCK[1:0] Clock System Clock SCLK = fX...

  • Page 76: Register Map

    7. Clock generator MC97F6108A User’s manual Register map Table 10. Clock Generator Register Map Name Address Direction Default Description SCCR System and Clock Control Register Register description SCCR (System and Clock Control Register): 8AH WDTRCON – CHBS – – –...

  • Page 77: Basic Interval Timer (Bit)

    8. Basic Interval Timer (BIT) Basic Interval Timer (BIT) MC97F6108A has a free running 8-bit Basic Interval Timer (BIT). BIT generates the time base for watchdog timer counting, and provides a basic interval timer interrupt (BITF). BIT of MC97F6108A features the followings: During Power On, BIT gives a stable clock generation time ...

  • Page 78: Bit Register Description

    8. Basic Interval Timer (BIT) MC97F6108A User’s manual BIT register description BITCR (Basic Interval Timer Control Register): 8BH BITF BCK2 BCK1 BWDTRC BCLR BPD2 BPD1 BPD0 Initial value: 45H When BIT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to...

  • Page 79: Watchdog Timer (Wdt)

    MC97F6108A User’s manual 9. Watchdog Timer (WDT) Watchdog Timer (WDT) Watchdog Timer (WDT) rapidly detects the CPU malfunction such as endless looping caused by noise or something like that, and resumes the CPU to the normal state. Watchdog timer signal for malfunction detection can be used as either a CPU reset or an interrupt request.

  • Page 80: Wdt Block Diagram

    9. Watchdog Timer (WDT) MC97F6108A User’s manual WDT block diagram BIT Overflow Watchdog Timer Counter Register Clear To Reset BIT Clock Source WDTCNT Circuit WDTEN WDTCK Clear WDTIFR INT_ACK BIT Overflow comparator BIT Overflow/8 WDTIF WDTDR Watchdog Timer Data Register...

  • Page 81: Register Description

    MC97F6108A User’s manual 9. Watchdog Timer (WDT) Register description WDTR (Watchdog Timer Register: Write Case): 8EH WDTR7 WDTR 6 WDTR 5 WDTR 4 WDTR 3 WDTR 2 WDTR 1 WDTR 0 Initial value: FFH WDTR[7:0] Set a period WDT Interrupt Interval=(BIT Interrupt Interval) x(WDTDR Value+1) NOTE: Do not write “0”...

  • Page 82: Timer0/1/2/3

    10. Timer0/1/2/3 MC97F6108A User’s manual Timer0/1/2/3 A 16-bit timer0/1/2/3 consists of multiplexer, timer0/1/2/3 data register high/low, timer0/1/2/3 register high/low and timer0/1/2/3 mode register, PWM0/1/2/3 duty register high/low and PWM0/1/2/3 period register high/low (TxDRH, TxDRL, TxH, TxL, TxCR, TxCR1, PWMxDRH, PWMxDRL, PWMxPRL, PWMxPRH, x=0/1/2/3).

  • Page 83: 16-Bit Timer/Counter Mode

    MC97F6108A User’s manual 10. Timer0/1/2/3 10.2 16-bit timer/counter mode In the 16-bit timer/counter mode of timer0/1/2/3, If the value of TxH/TxL and the value of TxDRH/TxDRL are matched, the square wave form is output through TxO/PWMx port. The output is 50:50 of duty...

  • Page 84: 16-Bit Capture Mode

    10. Timer0/1/2/3 MC97F6108A User’s manual 10.3 16-bit capture mode The 16-bit capture mode of timer0/1/2/3 is set by CAPx as ‘1’ in TxCR register. The clock is the same source as 16-bit timer/counter mode. Interrupt occurs at TxH/TxL and TxDRH/TxDRL matching time.

  • Page 85: 16-Bit Pwm Mode

    MC97F6108A User’s manual 10. Timer0/1/2/3 10.4 16-bit PWM mode Timer0/1/2/3 has a PWM (pulse Width Modulation) function. In PWM mode, 16-bit resolution PWM wave form is output through TxO/PWMx pin. This pin should be configured as a PWM output by set TX_PE to ‘1’.

  • Page 86: Figure 29. 16-Bit Pwm Mode Of Timer0/1/2/3

    10. Timer0/1/2/3 MC97F6108A User’s manual ADDRESS : B2 , BA , C2 , CA TxCR TxEN PWMxE CAPx TxCK2 TxCK1 TxCK0 TxCN TxST INITIAL VALUE : 0000_0000 ADDRESS : B3 , BB , C3 , CB TxCR1 TxIN[2] TxIN[1] TxIN[0]...

  • Page 87: Figure 31. 16-Bit Pwm Example At 16Mhz (Period=Duty)

    MC97F6108A User’s manual 10. Timer0/1/2/3 Source Clock (f 0000 0001 0002 FFFF 0000 0001 0002 0000 0001 0002 FFFF 0000 0001 0002 /PWM POL0 = 1 Period = Duty /PWM POL0 = 0 Period = Duty Duty Cycle (1+0002 )X250ns = 0.75us Period Cycle (FFFFH+1+0002H)X250ns = 16.38ms →...

  • Page 88: Register Map

    10. Timer0/1/2/3 MC97F6108A User’s manual 10.5 Register map Table 15. Register Map Name Address Default Description T0CR Timer 0 Mode Control Register T0CR1 Timer 0 Mode Control Register 1 Timer 0 Low Register PWM0DRL PWM 0 Duty Register Low CDR0L...
  • Page 89 MC97F6108A User’s manual 10. Timer0/1/2/3 Table 15. Register Map (continued) Name Address Default Description PWM2PRL PWM 2 Period Register Low T2DRH Timer 2 Data Register High PWM2PRH PWM 2 Period Register High T3CR Timer 3 Mode Control Register T3CR1 Timer 3 Mode Control Register 1...

  • Page 90: Register Description

    10. Timer0/1/2/3 MC97F6108A User’s manual 10.6 Register description TxCR (Timer0/1/23 Mode Control Register): T0CR(B2H), T1CR(BAH), T2CR(C2H), T3CR(CAH) TxEN PWMxE CAPx TxCK2 TxCK1 TxCK0 TxCN TxST Initial value: 00 TxEN Control Timer X Timer X enable PWMxE Control PWM enable PWM disable...
  • Page 91 MC97F6108A User’s manual 10. Timer0/1/2/3 TxCR1 (Timer0/1/23 Mode Control Register 1) : B3H, BBH, C3H, CBH TxIN[2] TxIN[1] TxIN[0] ECEN Tx_PE Initial value: 00 TxIN[2:0] Select Event Counter and External Interrupt for Capture mode TxIN2 TxIN1 TxIN0 description TxEC0 TxEC1...
  • Page 92 10. Timer0/1/2/3 MC97F6108A User’s manual PWMxDRL (PWM0/1/2/3 Duty Register Low, Write Case) : B4H, BCH, C4H, CCH PWMxDRL7 PWMxDRL6 PWMxDRL5 PWMxDRL4 PWMxDRL3 PWMxDRL2 PWMxDRL1 PWMxDRL0 Initial value: 00 PWMxDRL[7:0] Tx PWM Duty Low data NOTE: Reading and writing is possible only when PWMxE = 1 and TxST = 0...
  • Page 93 MC97F6108A User’s manual 10. Timer0/1/2/3 PWMxPRL (PWM0/1/2/3 Period Register Low, Write Case) : B6H, BEH, C6H, CEH PWMxPRL7 PWMxPRL6 PWMxPRL5 PWMxPRL4 PWMxPRL3 PWMxPRL2 PWMxPRL1 PWMxPRL0 Initial value: FF PWMxPRL[7:0] Tx PWM Period Low data NOTE: Reading and writing is effective only when PWMxE = 1 and TxST = 0...

  • Page 94: Ppg (Programmable Pulse Generator)

    When PPGEN set to '1', PPG output goes to high. And initial value of P05PU(pullup register of PPGO port) is '1'. MC97F6108A has five analog comparators, and their output controls PPG operation respectively. Output from internal comparator 0 whose input is from an external analog pin can be used to synchronize the pulse output and the pulse controls IGBT.

  • Page 95: Ppg Block Diagram

    MC97F6108A User’s manual 11. PPG (Programmable Pulse Generator) 11.1 PPG block diagram ADDRESS : E2 PPGCR PPGEN CAPE PPGCK2 PPGCK1 PPGCK0 PPGCN PPGST INITIAL VALUE : 0000_0000 ADDRESS : E3 PPGCR1 PPGIN[2] PPGIN[1] PPGIN[0] PPG_PE INITIAL VALUE : 0000_0000 ADDRESS : E1...

  • Page 96: Ppg Start And One Shot Pulse

    11. PPG (Programmable Pulse Generator) MC97F6108A User’s manual 11.2 PPG start and one shot pulse PPG start sources are PPGST bit of PPGCR register and C0_FLAG (comparator 1 flag). If PPGMD is '0', only PPGST starts the counter, if PPGMD is '1', PPGST or C0_FLAG starts the counter. After one period, C0_FLAG is cleared automatically.

  • Page 97: Figure 33. Ppg Start And One Shot Pulse

    MC97F6108A User’s manual 11. PPG (Programmable Pulse Generator) Default value of PPGO is high, it is toggled when duty matching and period matching (duty matching: reset, period matching: set). To export the pulse output as PPG port, set the PPG_PE bit in the PPGCR1 register.

  • Page 98: Ppg Period/Duty Write

    11. PPG (Programmable Pulse Generator) MC97F6108A User’s manual 11.3 PPG period/duty write When writing a value to the PPG period registers, write to the PPGPH first, then write to the PPGPL. As shown in the figure below, when writing to the PPGPH, the value is saved to a buffer. When writing to the PPGPL, the saved value and PPGPL is loaded to the compare registers.

  • Page 99: Capture Mode

    MC97F6108A User’s manual 11. PPG (Programmable Pulse Generator) 11.4 Capture mode PPG capture mode is set by CAPE as ‘1’ in PPGCR register. The capture result is loaded into PPGCH/PPGCL. The counter (PPGH/PPGL) does not stop when counter is captured. Capture sources are CMP3IF, CMP1IF and CMP4IF.

  • Page 100: Disable Ppg Output By Comparator 1

    11. PPG (Programmable Pulse Generator) MC97F6108A User’s manual 11.5 Disable PPG output by comparator 1 PERIOD Compare REGISTER PPG_CLK clear PPGH/L (16-bit Counter) DUTY Compare REGISTER CFEDGE[1] PPG_PE CFPOLA[1] CFBOTH[1] CFENAB[1] C1DBSEL[1:0] by pass PPGO 0.3 us CMP1 C1_FLAG 0.6 us 1.2 us...

  • Page 101: Disable Ppg Output By Comparator 3

    MC97F6108A User’s manual 11. PPG (Programmable Pulse Generator) 11.6 Disable PPG output by comparator 3 PERIOD Compare CMP4IF REGISTER PPGIN[2:0] CMP1IF PPG_CLK clear PPGH/L (16-bit Counter) PPGMD CIENAB[3] C3DBSEL[1:0] CAPE by pass 0.3 us CMP3 CMP3IF DUTY Compare 0.6 us REGISTER 1.2 us...

  • Page 102: Ppg Period Limitation

    11. PPG (Programmable Pulse Generator) MC97F6108A User’s manual 11.7 PPG period limitation PPG max period is determined by the PPGPXH/PPGPXL. After duty matching, period comparation is enabled until period matching. If PPG counter value and PPGPXH/PPGPXL matches before PPG counter value and PPGPH/PPGPL matches, the counter is cleared and waits for the start signal.

  • Page 103: Auto Period Mode By Comparator 2

    MC97F6108A User’s manual 11. PPG (Programmable Pulse Generator) 11.8 Auto period mode by comparator 2 When ATPEN is '1', PPG operates in auto period mode and PPG period is changed automatically. When comparator 2 outputs high, ATPHR/ATPLR (the period register in auto period mode) is decreased by DSTEP and it is applied to the next cycle.

  • Page 104: Ppg Period Decrease

    11. PPG (Programmable Pulse Generator) MC97F6108A User’s manual 11.8.1 PPG period decrease When comparator 2 outputs high, ATPHR/ATPLR (the period register in auto period mode) is decreased by DSTEP and it is applied to the next cycle. NOTE: In duty state, comparator2 is not detected.

  • Page 105: Ppg Period When Atpsel = 2'B00

    MC97F6108A User’s manual 11. PPG (Programmable Pulse Generator) 11.8.2 PPG period when ATPSEL = 2'b00 When comparator 2 outputs low and ATPSEL is 2'b00, ATPHR/ATPLR (the period register in auto period mode) is maintained as the current period. current period...

  • Page 106: Ppg Period When Atpsel = 2'B01

    11. PPG (Programmable Pulse Generator) MC97F6108A User’s manual 11.8.3 PPG period when ATPSEL = 2'b01 When comparator 2 outputs low and ATPSEL is 2'b01, ATPHR/ATPLR (the period register in auto period mode) is PPGPH/PPGPL. current period PERIOD write PPGPH PPGPL...

  • Page 107: Ppg Period When Atpsel = 2'B1X

    MC97F6108A User’s manual 11. PPG (Programmable Pulse Generator) 11.8.4 PPG period when ATPSEL = 2'b1x When comparator 2 outputs low and ATPSEL is 2'b1x, ATPHR/ATPLR (the period register in auto period mode) is increased by USTEP and it is applied to the next cycle.

  • Page 108: Figure 50. Auto Period Mode (Atpsel = 2'B1X)

    11. PPG (Programmable Pulse Generator) MC97F6108A User’s manual < ATPSEL = 2'b1x > ATPEN PPGPH/PPGPL USTEP DSTEP CPOUT2 ATPHR, ATPLR start pulse PPGO PERIOD=A PERIOD=8 PERIO D=9 PERIOD=A PERIOD=8 PERIO D=9 PERIOD=A Figure 50. Auto Period Mode (ATPSEL = 2'b1x)

  • Page 109: Ppg Period When Writing

    MC97F6108A User’s manual 11. PPG (Programmable Pulse Generator) 11.8.5 PPG period when writing When writing to PPGPH/PPGPL, written period value is loaded into the ATPHR/ATPLR in the next cycle and other function is ignored. current period PERIOD write PPGPH PPGPL...

  • Page 110: Figure 52. Ppg Period When Writing (Atpsel = 2'B1X)

    11. PPG (Programmable Pulse Generator) MC97F6108A User’s manual < ATPSEL = 2'b1x > ATPEN PPGPH/PPGPL write write USTEP increase increase increase DSTEP decrease CPOUT2 ATPHR, ATPLR start pulse PPGO PERIO D=A PERIO D=8 PERIO D=7 PERIO D=8 PERIO D=A PERIO D=B PERIO D=C Figure 52.

  • Page 111: Ppg Period Min/Max Limitation

    MC97F6108A User’s manual 11. PPG (Programmable Pulse Generator) 11.8.6 PPG period min/max limitation When ATPHR/ATPLR is increasing, if ATPHR/ATPLR value and ATPMAXHR/ATPMAXLR matches, ATP_MAX (max period matching flag) set to '1'. When ATPHR/ATPLR is decreasing, if ATPHR/ATPLR value and ATPMINHR/ATPMINLR matches, ATP_MIN (min matching flag) set to '1'.

  • Page 112: Figure 54. Ppg Period Block Diagram When Period Min/Max Matching

    11. PPG (Programmable Pulse Generator) MC97F6108A User’s manual current period PERIOD write PPGPH PPGPL increase (8-bit) (8-bit) + USTEP[7:0] current period ATPSEL[1:0] decrease - DSTEP[7:0] C2DBSEL[1:0 current period CPOUT2 by pass (in the previous period) 0.3 us CMP2 0.6 us 1.2 us...

  • Page 113: Figure 56. When Min Period Matching

    MC97F6108A User’s manual 11. PPG (Programmable Pulse Generator) ATPEN ATPSEL 1x (increase) PPGPH/PPGPL USTEP DSTEP CPOUT2 ATPMINHR/ATPMINLR ATPHR, ATPLR start pulse PPGO PERIOD=F PERIO D=B PERIO D=7 PERIOD=7 PERIOD=7 PERIOD=8 PERIOD=9 ATP_MIN write 0 Figure 56. When Min Period Matching...

  • Page 114: Ppg Off-Time Max/Min Limitation

    11. PPG (Programmable Pulse Generator) MC97F6108A User’s manual 11.8.7 PPG off-time max/min limitation PPG off-time can be limited by OFFCR register setting to prevent that PPG off-time is too long or too short. If PPG off-time is too long and the start source is not received, PPG starts automatically after a certain period of time.

  • Page 115: Figure 58. Ppg Off-Time Max/Min Limitation

    MC97F6108A User’s manual 11. PPG (Programmable Pulse Generator) OFFMAXHR/OFFMAXLR MIN detect OFFMINHR/OFFMINLR CPOUT0 C0_FLAG PPGO PERIO D PERIO D PERIO D PPG off-time counter MAX detect PPG off-time max match PPG off-time min detect Figure 58. PPG Off-time Max/Min Limitation...

  • Page 116: Register Map

    11. PPG (Programmable Pulse Generator) MC97F6108A User’s manual 11.9 Register map Table 16. Register Map Name Address Default Description PPGCR PPG Control Register PPGCR1 PPG Control Register 1 PPGCR2 PPG Control Register 2 PPGL PPG Low Register PPGCL PPG Capture Data Register Low...

  • Page 117: 11.10 Register Description

    MC97F6108A User’s manual 11. PPG (Programmable Pulse Generator) 11.10 Register description PPGCR (PPG Control Register): E2H PPGEN CAPE PPGCK2 PPGCK1 PPGCK0 PPGCN PPGST Initial value: 00H PPGEN Enable PPG PPG disable PPG enable CAPE capture mode enable Disable capture mode...
  • Page 118 11. PPG (Programmable Pulse Generator) MC97F6108A User’s manual PPGCR1 (PPG Control Register 1) : E3H PPGIN[2] PPGIN[1] PPGIN[0] PPG_PE Initial value: 00H PPGIN[2:0] Select Event Counter and Comparator Interrupt for Capture mode PPGIN2 PPGIN1 PPGIN0 description CMP3IF CMP1IF CMP4IF PPG_PE...
  • Page 119 MC97F6108A User’s manual 11. PPG (Programmable Pulse Generator) PGL (PPG Register Low, Read Case) : D3H PPGL7 PPGL6 PPGL5 PPGL4 PPGL3 PPGL2 PPGL1 PPGL0 Initial value: 00H PPGL[7:0] PPGL Counter Low data. PPGCL (PPG Capture Data Register Low, Read Case) : D3H...
  • Page 120 11. PPG (Programmable Pulse Generator) MC97F6108A User’s manual PPGPL (PPG Period Register Low) : E6H PPGPL7 PPGPL6 PPGPL5 PPGPL4 PPGPL3 PPGPL2 PPGPL1 PPGPL0 Initial value: FFH PPGPL[7:0] PPG Period Low data PPGPH (PPG Period Register High) : E7H PPGPH7 PPGPH6...
  • Page 121 MC97F6108A User’s manual 11. PPG (Programmable Pulse Generator) ATPCR (Auto Period Mode Control Register) : F9H MAX_REQ MIN_REQ ATPMAX ATPMIN ATPSEL1 ATPSEL0 ATPEN Initial value: 00H If PPG period max matching occurs, the flag becomes ‘1’. The flag is cleared MAX_REQ before interrupt service routine is served.
  • Page 122 11. PPG (Programmable Pulse Generator) MC97F6108A User’s manual USTEP (Auto Period Mode Up Step Register) : C1H USTEP7 USTEP6 USTEP5 USTEP4 USTEP3 USTEP2 USTEP1 USTEP0 R / W R / W R / W R / W R / W...
  • Page 123 MC97F6108A User’s manual 11. PPG (Programmable Pulse Generator) ATPMINLR (Auto Period Mode Min Period Low Register) : 2F06H ATPMINLR7 ATPMINLR6 ATPMINLR5 ATPMINLR4 ATPMINLR3 ATPMINLR2 ATPMINLR1 ATPMINLR0 R / W R / W R / W R / W R / W...
  • Page 124 11. PPG (Programmable Pulse Generator) MC97F6108A User’s manual OFFMINHR (PPG Off Time Min Period High Register) : 2F0FH OFFMINHR7 OFFMINHR6 OFFMINHR5 OFFMINHR4 OFFMINHR3 OFFMINHR2 OFFMINHR1 OFFMINHR0 R / W R / W R / W R / W R / W...

  • Page 125: Analog Comparator And Op-Amp

    12. Analog comparator and OP-AMP Analog comparator and OP-AMP MC97F6108A has five analog comparators and two operational amplifiers whose inputs are external analog inputs and whose outputs are sources of internal peripheral circuits. Each comparator has output noise canceler, de-bounce and interrupt circuits. De-bounce length for each comparator is selectable by setting CxDBSEL[1:0].

  • Page 126: Comparator And Op-Amp Description

    12. Analog comparator and OP-AMP MC97F6108A User’s manual 12.1 Comparator and OP-AMP description Comparator 0 "+" and "–" input are external analog port (CMP0_IN_P, CMP0_IN_N).  Output(CPOUT0) generates interrupt flag(CMP0IF) and comparator flag(C0_FLAG).  CPOUT0 is connected to the timer 0 event counter source.
  • Page 127 MC97F6108A User’s manual 12. Analog comparator and OP-AMP Comparator 3 "+" input is the output of the AMP1  "-" input is internal Vref selected by setting C3NVSL[3:0] register.  Output(CPOUT3) generates interrupt flag(CMP3IF) and comparator flag(C3_FLAG).  CPOUT3 is connected to the timer 3 event counter source.

  • Page 128: Block Diagram

    12. Analog comparator and OP-AMP MC97F6108A User’s manual 12.2 Block diagram <option> 1/50VDD 2/50VDD 3/50VDD CFEDGE[4] CFENAB[4] 4/50VDD CFPOLA[4] CFBOTH[] 5/50VDD C4DBSEL[1:0] C4_FLAG 6/50VDD 4 us 8/50VDD 8 us 10/50VDD INT10 CMP4IF CMP4 CIEDGE[4] 16 us CIPOLA[4] IE1.4 CIENAB[4] 32 us...

  • Page 129: Register Description

    MC97F6108A User’s manual 12. Analog comparator and OP-AMP 12.3 Register description CA_REG1 (Comparator Amp Register 1) : 2F31H OPAEN AORA_EN AMP2EI_EN OINPen Initial value: 00H OPAEN Control OP-AMP OP-AMP disable OP-AMP enable AORA_EN Control AMP2 output voltage divider Disable enable...
  • Page 130 12. Analog comparator and OP-AMP MC97F6108A User’s manual CA_REG3 (Comparator Amp Register 3) : 2F33H DGCAL2[2] DGCAL2[1] DGCAL2[0] DGCAL1[2] DGCAL1[1] DGCAL1[0] Initial value: 00H DGCAL2[2:0] AMP2 DC gain selection x 1.5 x 2.5 DGCAL1[2:0] AMP1 DC gain selection x 2.5 x 3.53...
  • Page 131 MC97F6108A User’s manual 12. Analog comparator and OP-AMP CA_REG4 (Comparator Amp Register 4) : 2F34H CMPEN HYSL_EN3 HYSL_EN2 HYSL_EN1 C2INPen C1INPen C0INPen C0INNen Initial value: 00H CMPEN Control comparator All Comparator Disable All Comparator Enable HYSL_EN3 Control Comparator 3 hysteresis...
  • Page 132 12. Analog comparator and OP-AMP MC97F6108A User’s manual CA_REG5 (Comparator Amp Register 5) : 2F35H C4NVSL[2] C4NVSL[1] C4NVSL[0] C1NVSL[3] C1NVSL[2] C1NVSL[1] C1NVSL[0] Initial value: 00 C4NVSL[2:0] Comparator 1 input reference voltage selection VDD x 1/50 VDD x 2/50 VDD x 3/50...
  • Page 133 MC97F6108A User’s manual 12. Analog comparator and OP-AMP CA_REG6 (Comparator Amp Register 6) : 2F36H C3NVSL[3] C3NVSL[2] C3NVSL[1] C3NVSL[0] C2NVSL[3] C2NVSL[2] C2NVSL[1] C2NVSL[0] Initial value: 00 C3NVSL[3:0] Comparator 3 input reference voltage selection 0000 VDD x 20/50 0001 VDD x 21/50...
  • Page 134 12. Analog comparator and OP-AMP MC97F6108A User’s manual CA_REG7 (Comparator Amp Register 7) : 2F37H CMPXOen CMPOSL[2] CMPOSL[1] CMPOSL[0] Initial value: 00 CMPXOen Control CMPXO port Comparator 0~4 output to CMPXO port disable Comparator 0~4 output to CMPXO port enable...
  • Page 135 MC97F6108A User’s manual 12. Analog comparator and OP-AMP CA_REGB (Comparator Amp Register B) : 2F3BH C4DBSEL[1] C4DBSEL[0] C4OUTINV C3OUTINV C2OUTINV C1OUTINV C0OUTINV Initial value: 00 C4DBSEL[1:0] Comparator 4 de-bounce selection 16us 32us C4OUTINV Control Comparator 4 output Non invert Invert...

  • Page 136: Buzzer Driver

    MC97F6108A User’s manual Buzzer driver A buzzer of MC97F6108A consists of 8-bit counter, a buzzer data register (BUZDR), and a buzzer control register (BUZCR). It outputs square wave (0.122kHz to 62.5kHz @ 1MHz) through P30/BUZO pin, and its buzzer data register (BUZDR) controls the buzzer frequency (refer to the following expression).

  • Page 137: Table 17. Buzzer Frequency At 1Mhz

    MC97F6108A User’s manual 13. Buzzer driver Table 17. Buzzer Frequency at 1MHz BUZDATA BUZDATA Buzzer Frequency (kHz) Buzzer Frequency (kHz) [5:0] [5:0] BUZDIV[1:0] BUZDIV[1:0] (fbuz/8) (fbuz/16) (fbuz/32) (fbuz/64) (fbuz/8) (fbuz/16) (fbuz/32) (fbuz/64) 62.500 31.250 15.625 7.813 1.894 0.947 0.473 0.237 31.250...

  • Page 138: Buzzer Driver Block Diagram

    13. Buzzer driver MC97F6108A User’s manual 13.1 Buzzer driver block diagram BUZEN fx/1 6-bit Up-Counter fx/2 Clear fx/4 Counter fx/8 fx/16 scaler Match fx/32 BUZO fx/64 Comparator fx/128 BUZOEN BUZDR BUCK[2:0] Figure 60. Buzzer Driver Block Diagram 13.2 Register map Table 18.

  • Page 139: Register Description

    MC97F6108A User’s manual 13. Buzzer driver 13.3 Register description BUZDR (Buzzer Data Register): EFH BUZDIV1 BUZDIV0 BUZDATA5 BUZDATA4 BUZDATA3 BUZDATA2 BUZDATA1 BUZDATA0 Initial value: FFH BUZDIV[1:0] Buzzer Clock Divider BUZDIV1 BUZDIV0 Description BUZDATA[5:0] This bits control the Buzzer frequency. Its resolution is 00H to 3FH.

  • Page 140: 12-Bit Ad Converter (Adc)

    MC97F6108A User’s manual 12-bit AD Converter (ADC) Analog-to-digital converter (ADC) of MC97F6108A allows conversion of an analog input signal to corresponding 12-bit digital value. This A/D module has eight analog inputs. Output of the multiplexer becomes input into the converter which generates the result through successive approximation.

  • Page 141: Figure 61. 12-Bit Adc Block Diagram

    MC97F6108A User’s manual 14. 12-bit AD Converter (ADC) ÷2 ÷4 SCLK ÷8 scale ÷32 12bit A/D Converter Data Register ADCRH[7:0] ADCRL[7:4] CKSEL[1:0] ADCLK ADST or EXTRG (8bit) (4bit) VDD18 Clear Successive Approximation ADIF Interrupt Circuit Comparator ADSEL[3:0] ADST or Trigger...

  • Page 142: Adc Operation

    14. 12-bit AD Converter (ADC) MC97F6108A User’s manual 14.3 ADC operation In this section, control registers and align bits are introduced in Figure 64, and ADC operation flow sequence is introduced in Figure 65. Align bit set 0 ADCO11 ADCO10...

  • Page 143: Register Map

    MC97F6108A User’s manual 14. 12-bit AD Converter (ADC) SET ADCM1 Select ADC Clock & Data Align Bit. SET ADCM ADC enable & Select AN Input Channel. Converting START Start ADC Conversion. If Conversion is completed, AFLG is set “1” and ADC AFLAG = 1? interrupt is occurred.

  • Page 144: Register Description

    14. 12-bit AD Converter (ADC) MC97F6108A User’s manual 14.5 Register description ADCM (A/D Converter Mode Register): 95H STBY ADST REFSEL AFLAG ADSEL3 ADSEL2 ADSEL1 ADSEL0 Initial value: 8FH STBY Control Operation of A/D standby (power down) ADC module enable ADC module disable (power down) ADST Control A/D Conversion stop/start.
  • Page 145 MC97F6108A User’s manual 14. 12-bit AD Converter (ADC) ADCRH (A/D Converter Result High Register):97H ADDM11 ADDM10 ADDM9 ADDM8 ADDM7 ADDM6 ADDM5 ADDM4 ADDL11 ADDL10 ADDL9 ADDL8 Initial value: xxH ADDM[11:4] MSB align, A/D Converter High Data (8-bit), default ADDL[11:8] LSB align, A/D Converter High Data (4-bit)
  • Page 146 14. 12-bit AD Converter (ADC) MC97F6108A User’s manual ADCM1 (A/D Converter Mode Register): 96H EXTRG TSEL2 TSEL1 TSEL0 ALIGN CKSEL1 CKSEL0 STBY = 1 R/W( STBY = 0 Initial value: 01H EXTRG A/D external Trigger A/D conversion Start by external Trigger, and Stop by clearing this bit...

  • Page 147: Usart

    MC97F6108A User’s manual 15. USART USART Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. USART of MC97F6108A features the followings: Full Duplex Operation (Independent Serial Receive and Transmit Registers)  Asynchronous or Synchronous Operation ...

  • Page 148: Block Diagram

    15. USART MC97F6108A User’s manual 15.1 Block diagram UBAUD SCLK Baud Rate Generator Master Clock Sync Logic Control UMSEL[1:0] Rx Interrupt RXD/ MISO Clock Control Recovery Data Recovery UMSEL1&UMSEL0 DOR/PE/FE UDATA[0] Master Checker (Rx) UDATA[1] Stop bit UMSEL0 (Rx) Generator...

  • Page 149: Clock Generation

    MC97F6108A User’s manual 15. USART 15.2 Clock generation Clock generation logic generates a base clock signal for Transmitter and Receiver. USART supports four modes of clock operation such as Normal Asynchronous mode, Double Speed Asynchronous mode, Master Synchronous mode, and Slave Synchronous mode.

  • Page 150: External Clock (Xck)

    15. USART MC97F6108A User’s manual 15.3 External clock (XCK) External clocking is used by the synchronous or SPI slave modes of operation. External clock input from the XCK pin is sampled by a synchronization logic to remove meta-stability. The output from the synchronization logic must then pass through an edge detector before it can be used by Transmitter and Receiver.

  • Page 151: Data Format

    MC97F6108A User’s manual 15. USART 15.5 Data format A serial frame is defined to consist of one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. USART2 supports all 30 combinations of the followings as a valid frame format.

  • Page 152: Parity Bit

    15. USART MC97F6108A User’s manual 15.6 Parity bit Parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result of the exclusive-or is inverted. Parity bit is located between St + bits and first stop bit of a serial frame.

  • Page 153: Parity Generator

    MC97F6108A User’s manual 15. USART UDRE flag indicates whether the transmit buffer is ready to be loaded with new data. This bit is set when the transmit buffer is empty and cleared when the transmit buffer contains transmission data which has not yet been moved into the shift register. And also this flag can be cleared by writing ‘0’ to this bit field.

  • Page 154: Receiver Flag And Interrupt

    15. USART MC97F6108A User’s manual Even if there’s 2nd stop bit in the frame, the 2nd stop bit is ignored by Receiver. That is, receiving the first stop bit means that a complete serial frame is present in the receiver shift register and contents of the shift register are to be moved into the receive buffer.

  • Page 155: Disabling Receiver

    MC97F6108A User’s manual 15. USART 15.8.4 Disabling receiver In contrast to Transmitter, disabling the Receiver by clearing RXE bit makes the Receiver inactive immediately. When the Receiver is disabled the Receiver flushes the receive buffer and the remaining data in the buffer is all reset. Function of USART is not overridden on the RXD pin, so the RXD pin becomes normal GPIO or primary function pin.

  • Page 156: Figure 71. Sampling Of Data And Parity Bit

    15. USART MC97F6108A User’s manual As described already, when Receiver clock is synchronized to the start bit, the data recovery can begin. Data recovery process is almost similar to the clock recovery process. The data recovery logic samples 16 times for each incoming bits for Normal mode and 8 times for Double Speed mode. It uses the samples 8, 9, and 10 to decide data value for Normal mode, and the samples 4, 5, and 6 for Double Speed mode.

  • Page 157: Spi Mode

    MC97F6108A User’s manual 15. USART 15.9 SPI mode USART can be set to operate in industrial standard SPI compliant mode. The SPI mode has the following features. Full duplex, three-wire synchronous data transfer  Master or Slave operation  Supports all four SPI modes of operation (mode0, 1, 2, and 3) ...

  • Page 158: Figure 73. Spi Clock Formats When Ucpha = 0

    15. USART MC97F6108A User’s manual (UCPOL=0) (UCPOL=1) SAMPLE MOSI MSB First BIT7 BIT6 … BIT2 BIT1 BIT0 LSB First BIT0 BIT1 … BIT5 BIT6 BIT7 MISO /SS OUT (MASTER) /SS IN (SLAVE) Figure 73. SPI Clock Formats when UCPHA = 0 When UCPHA=0, the slave begins to drive its MISO output with the first data bit value when SS goes to active low.

  • Page 159: Figure 74. Spi Clock Formats When Ucpha = 1

    MC97F6108A User’s manual 15. USART (UCPOL=0) (UCPOL=1) SAMPLE MOSI2 MSB First BIT7 BIT6 … BIT2 BIT1 BIT0 LSB First BIT0 BIT1 … BIT5 BIT6 BIT7 MISO2 /SS2 OUT (MASTER) /SS2 IN (SLAVE) Figure 74. SPI Clock Formats when UCPHA = 1 When UCPHA=1, the slave begins to drive its MISO output when SS goes active low, but the data is not defined until the first XCK edge.

  • Page 160: 15.10 Register Map

    15. USART MC97F6108A User’s manual 15.10 Register map Table 22. USART Register Map Name Address Direction Default Description UCTRL1 USART Control 1 Register UCTRL2 USART Control 2 Register UCTRL3 USART Control 3 Register USTAT USART Status Register UBAUD USART Baud Rate Generation Register...

  • Page 161: 15.11 Register Description

    MC97F6108A User’s manual 15. USART 15.11 Register description UCTRL1 (USART Control 1 Register) FAH USIZE1 USIZE0 UMSEL1 UMSEL0 UPM1 UPM0 USIZE2 UCPOL UDORD UCPHA Initial value: 00H UMSEL[1:0] Selects operation mode of USART UMSEL1 UMSEL0 Operating Mode Asynchronous Mode (Normal Uart)
  • Page 162 15. USART MC97F6108A User’s manual UCTRL2 (USART Control 2 Register) FBH UDRIE TXCIE RXCIE WAKEIE USARTEN Initial value: 00H UDRIE Interrupt enable bit for USART Data Register Empty. Interrupt from UDRE is inhibited (use polling) When UDRE is set, request an interrupt TXCIE Interrupt enable bit for Transmit Complete.
  • Page 163 MC97F6108A User’s manual 15. USART UCTRL3 (USART Control 3 Register) FCH MASTER LOOPS DISXCK SPISS USBS Initial value: 00H MASTER Selects master or slave in SPI or Synchronous mode operation and controls the direction of XCK pin. Slave mode operation and XCK is input pin.
  • Page 164 15. USART MC97F6108A User’s manual USTAT (USART2 Status Register) FDH UDRE WAKE SOFTRST Initial value: 80H UDRE The UDRE flag indicates if the transmit buffer (UDATA) is ready to be loaded with new data. If UDRE is ‘1’, it means the transmit buffer is empty and can hold one or two new data.
  • Page 165 MC97F6108A User’s manual 15. USART UBAUD (USART Baud-Rate Generation Register) FEH UBAUD7 UBAUD6 UBAUD5 UBAUD4 UBAUD3 UBAUD2 UBAUD1 UBAUD0 Initial value: FFH UBAUD [7:0] The value in this register is used to generate internal baud rate in asynchronous mode or to generate XCK clock in synchronous or SPI mode.

  • Page 166: Baud Rate Settings (Example)

    15. USART MC97F6108A User’s manual 15.12 Baud rate settings (example) Table 23. Examples of UBAUD Settings for Commonly Used Oscillator Frequencies Baud fOSC=1.00MHz fOSC=1.8432MHz fOSC=2.00MHz Rate U2X=0 U2X=1 U2X=0 U2X=1 U2X=0 U2X=1 UBAUD ERROR UBAUD ERROR UBAUD ERROR UBAUD ERROR...
  • Page 167 MC97F6108A User’s manual 15. USART Table 23. Examples of UBAUD Settings for Commonly Used Oscillator Frequencies (continued) Baud fOSC=8.00MHz fOSC=11.0592MHz fOSC=14.7456MHz Rate U2X=0 U2X=1 U2X=0 U2X=1 U2X=0 U2X=1 UBAUD ERROR UBAUD ERROR UBAUD ERROR UBAUD ERROR UBAUD ERROR UBAUD ERROR 2400 0.2%...

  • Page 168: Inter Integrated Circuit (I2C)

    16. Inter Integrated Circuit (I2C) MC97F6108A User’s manual Inter Integrated Circuit (I2C) Inter Integrated Circuit (I2C) is one of the industrial standard serial communication protocols, and which uses 2 bus lines Serial Data Line (SDA) and Serial Clock Line (SCL) to exchange data. Because both SDA and SCL lines are open-drain output, each line needs pull-up resistor.

  • Page 169: I2C Bit Transfer

    MC97F6108A User’s manual 16. Inter Integrated Circuit (I2C) 16.2 I2C bit transfer Data on the SDA line must be stable during HIGH period of the clock, SCL. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. The exceptions are START(S), repeated START(Sr) and STOP(P) condition where data line changes when clock line is high.

  • Page 170: Data Transfer

    16. Inter Integrated Circuit (I2C) MC97F6108A User’s manual 16.4 Data transfer Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer is unlimited. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first.

  • Page 171: Acknowledge

    MC97F6108A User’s manual 16. Inter Integrated Circuit (I2C) 16.5 Acknowledge The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse.

  • Page 172: Synchronization/ Arbitration

    16. Inter Integrated Circuit (I2C) MC97F6108A User’s manual 16.6 Synchronization/ arbitration Clock synchronization is performed using the wired-AND connection of I2C interfaces to the SCL line. This means that a HIGH to LOW transition on the SCL line will cause the devices concerned to start counting off their LOW period and it will hold the SCL line in that state until the clock HIGH state is reached.

  • Page 173: Block Operation

    MC97F6108A User’s manual 16. Inter Integrated Circuit (I2C) 16.7 Block Operation The I2C block as peripheral design is independently operating with main CPU operation. The operation of I2C block does a byte unit of I2C frame. After finishing a byte operation (transmit/receive data and clock) on I2C bus system, I2C block generate I2C interrupt for next byte operation.

  • Page 174: I2C Block Initialization Process

    16. Inter Integrated Circuit (I2C) MC97F6108A User’s manual 16.7.1 I2C block initialization process After power ON, it is necessary to have to initialize I2C block for that I2C Block provide I2C Slave device service I2C block will start operation (operation clock active) by setting IICEN bit on I2CMR register.

  • Page 175: I2C Interrupt Service

    MC97F6108A User’s manual 16. Inter Integrated Circuit (I2C) 16.7.2 I2C interrupt service I2C Interrupt service will use for next management action and data load/read from I2C block after I2C H/W block operation (as I2C Master/ Slave device). Because I2C block acts I2C data receiving/writing as a byte unit, I2C block make I2C interrupt for next action of I2C block.

  • Page 176: Master Transmitter

    16. Inter Integrated Circuit (I2C) MC97F6108A User’s manual 16.7.3 Master transmitter Main software is to have write/read data to/from slave I2C device. The software has to be ready to get number of data with internal RAM or sending data on internal RAM according to I2C bus protocol type of Slave device.
  • Page 177 MC97F6108A User’s manual 16. Inter Integrated Circuit (I2C) Master Read ( without sub address of Slave device ) I2CMR = IICEN+INTEN; // start generate I2CDR = Slave Address + Read mode; // load target Salve Address I2CMR |= SRT; // generate start condition...

  • Page 178: Slave Receiver

    16. Inter Integrated Circuit (I2C) MC97F6108A User’s manual 16.7.4 Slave receiver I2C Block that is under IIC enable and INTEN enable on I2CMR is monitoring I2C bus lines for being a start condition and self-address with I2CSAD. To have both signals of start signal and getting self- address, I2C block generate I2C interrupt with the status bits (SSEL, BUSY RXACK, SLAVE mode ...)

  • Page 179: Register Map

    MC97F6108A User’s manual 16. Inter Integrated Circuit (I2C) 16.8 Register map Table 24. Register Map Name Address Direction Default Description I2CMR I2C Mode Control Register I2CSR I2C Status Register I2CSCLLR SCL Low Period Register I2CSCLHR SCL High Period Register I2CSDAHR...

  • Page 180: I2C Register Description

    16. Inter Integrated Circuit (I2C) MC97F6108A User’s manual 16.9 I2C register description I2CMR (I2C Mode Control Register): DAH IICEN RESET INTEN ACKEN MASTER STOP START Initial value: 00H This is interrupt flag bit. No interrupt is generated or interrupt is cleared...
  • Page 181 MC97F6108A User’s manual 16. Inter Integrated Circuit (I2C) I2CSR (I2C Status Register): DBH GCALL TEND STOP SSEL MLOST BUSY TMODE RXACK Initial value: 00H GCALL This bit has different meaning depending on whether I2C is master or slave. Note 1) When I2C is a master, this bit represents whether it received AACK (Address ACK) from slave.
  • Page 182 16. Inter Integrated Circuit (I2C) MC97F6108A User’s manual I2CSCLLR (SCL Low Period Register): DCH SCLL7 SCLL6 SCLL5 SCLL4 SCLL3 SCLL2 SCLL1 SCLL0 Initial value: 3FH SCLL[7:0] This register defines the LOW period of SCL when I2C operates in master mode. The base clock is SCLK, the system clock, and the period is calculated by the formula : tSCLK×...
  • Page 183 MC97F6108A User’s manual 16. Inter Integrated Circuit (I2C) I2CSAR (I2C Slave Address Register): D7H SLA7 SLA6 SLA5 SLA4 SLA3 SLA2 SLA1 GCALLEN Initial value: FFH SLA[7:1] These bits configure the slave address of this I2C module when I2C operates in slave mode.

  • Page 184: Power Down Operation

    MC97F6108A User’s manual Power down operation MC97F6108A has three power-down modes to minimize the power consumption of the device. In power down mode, power consumption is reduced considerably. MC97F6108A provides three kinds of power saving functions such as IDLE mode, STOP1 mode and STOP2 mode. During one of these three modes, program will be stopped.

  • Page 185: Idle Mode

    MC97F6108A User’s manual 17. Power down operation 17.2 IDLE mode Power control register is set to ‘01h’ to enter into IDLE mode. In IDLE mode, internal oscillation circuits remain active. Oscillation continues and peripherals are operated normally, but CPU stops.

  • Page 186: Stop Mode

    17. Power down operation MC97F6108A User’s manual 17.3 STOP mode Power control register is set to ‘03H’ to enter into STOP mode. In STOP mode, the selected oscillator, system clock and peripheral clock is stopped, but basic interval timer and watchdog timer can be continued to operate with WDTRC OSC.

  • Page 187: Figure 85. Stop Mode Release Timing By Resetb

    MC97F6108A User’s manual 17. Power down operation CPU Clock RESETB Release STOP Command BIT Counter Clear & Start 2048 T TST = 32.7ms @ 16MHz Normal Operation STOP Mode Normal Operation �� = 1/f ������ = × ������ �������� ÷ ��������...

  • Page 188: Released Operation Of Stop Mode

    17. Power down operation MC97F6108A User’s manual 17.4 Released operation of STOP mode After STOP1, 2 mode is released, operation begins according to content of related interrupt register just before STOP mode starts (refer to Figure 86). If the global interrupt Enable Flag (IE.EA)is set to `1`, the STOP1, 2 mode is released by a certain interrupt of which interrupt enable flag is set to `1` and the CPU jumps to the relevant interrupt service routine.

  • Page 189: Register Map

    MC97F6108A User’s manual 17. Power down operation 17.5 Register map Table 26. Power Down Operation Register Map Name Address Direction Default Description PCON Power Control Register 17.6 Register description PCON (Power Control Register): 87H PCON7 – – – PCON3 PCON2...

  • Page 190: Reset

    Accumulator Stack Pointer (SP) Peripheral Clock Control Register Refer to the Peripheral Registers MC97F6108A has six types of reset sources as shown in the followings: External RESETB (In the case of RSTEN = '1')  Power ON RESET (POR) ...

  • Page 191: Reset Noise Canceller

    MC97F6108A User’s manual 18. Reset 18.2 RESET noise canceller The Figure 88 is the noise canceller time diagram for RESET Noise canceler. It has the noise cancel value of about 8us (@V =5V) to the low input of System Reset.

  • Page 192: Figure 90. Internal Reset Release Timing On Power-Up

    18. Reset MC97F6108A User’s manual Slow VDD Rise Time, min. 0.15V/ms =1.4V (Typ) nPOR BIT Overflows (Internal Signal) BIT Starts Internal RESETB Oscillation Figure 90. Internal RESET Release Timing On Power-Up Counting for configure option read start after POR is released...

  • Page 193: Figure 92. Boot Process Waveform

    MC97F6108A User’s manual 18. Reset :VDD Input :Internal OSC Reset Release Config Read Figure 92. Boot Process Waveform Table 28. Boot Process Description Process Description Remarks  No Operation 0.7V to 0.9V  1st POR level Detection About 1.2V to 1.6V Internal OSC (16MHz) ON ...

  • Page 194: External Resetb Input

    18. Reset MC97F6108A User’s manual 18.4 External RESETB input External RESETB is input to a Schmitt trigger. If the RESETB pin is held with low for at least 8us over within the operating voltage range and stable oscillation, it is applied and the internal state is initialized.

  • Page 195: Brown Out Detector Processor

    18.5 Brown out detector processor MC97F6108A has an On-chip brown-out detection circuit (BOD) for monitoring VDD level during operation by comparing it to a fixed trigger level. Trigger level for the BOD can be selected by configuring BODLS[2:0] bits to be 2.2V, 2.5V, 2.7V, 3.2V, 3.7V, 4.2V.

  • Page 196: Register Map

    18. Reset MC97F6108A User’s manual “H” “H” Internal nPOR “H” PAD RESETB (R00) BOD_RESETB .. 28 29 00 01 02 BIT (for Configure) 01 02 3F 40 00 01 02 03 BIT (for Reset) TCLK X 29H = about 5ms at 16MHz...

  • Page 197: Register Description For Reset Operation

    MC97F6108A User’s manual 18. Reset 18.7 Register description for reset operation RSFR (Reset Source Flag Register): 86H PORF EXTRF WDTRF OCDRF BODRF – – – – – – Initial value: 88H Power-On Reset flag bit. The bit is reset by writing ‘0’ to this bit.
  • Page 198 18. Reset MC97F6108A User’s manual BODR (BOD Control Register): 8FH – BODINTON – – ENBODST BODLS2 BODLS1 BODLS0 – – – Initial value: 01H BODINTON Select BOD reset or Interrupt Reset Interrupt ENBODST Select STOP mode BOD enable or disable...

  • Page 199: Memory Programming

    19. Memory programming Memory programming MC97F6108A has flash memory to which a program can be written, erased, and overwritten while mounted on the board. Serial ISP mode and byte-parallel ROM writer mode are supported. Flash of MC97F6108A features the followings: Flash Size: 8Kbytes ...

  • Page 200: Register Description

    19. Memory programming MC97F6108A User’s manual 19.1.2 Register description FEMR (Flash Mode Register): EAH FSEL ERASE PBUFF OTPE FEEN Initial value: 00H FSEL Select Flash memory. Deselect flash memory Select flash memory Enable program or program verify mode with VFY...
  • Page 201 MC97F6108A User’s manual 19. Memory programming FECR (Flash Control Register): EBH EXIT1 EXIT0 WRITE READ nFERST nPBRST Initial value: 03H Enable Flash bulk erase mode Disable bulk erase mode of Flash memory Enable bulk erase mode of Flash memory EXIT[1:0] Exit from program mode.
  • Page 202 19. Memory programming MC97F6108A User’s manual FESR (Flash Status Register): ECH PEVBSY VFYGOOD ROMINT WMODE EMODE VMODE Initial value: 80H PEVBSY Operation status flag. It is cleared automatically when operation starts. Operations are program, erase or verification Busy (Operation processing)
  • Page 203 MC97F6108A User’s manual 19. Memory programming FEARL (Flash address low Register): F2H ARL7 ARL6 ARL5 ARL4 ARL3 ARL2 ARL1 ARL0 Initial value: 00H ARL[7:0] Flash address low FEARM (Flash address middle Register): F3H ARM7 ARM6 ARM5 ARM4 ARM3 ARM2 ARM1...

  • Page 204: Figure 98. Read Device Internal Checksum (Full Size: 0X0000~0X1Fff)

    19. Memory programming MC97F6108A User’s manual Start OCD mode entry Write(OCD_CODE, 0xF555, 0xAA) Set checksum read mode Write(OCD_CODE, 0xFAAA, 0x55) Write(OCD_CODE, 0xF555, 0xA5) Write(OCD_XDATA, FEMR, 0x81) Set auto verify mode Write(OCD_CODE, FETR, 0x08) Write(OCD_CODE, FECR, 0x07) Busy check (FESR[7]=L) Read 24 - bit Checksum (H, M, L)

  • Page 205: Table 31. Program And Erase Time

    MC97F6108A User’s manual 19. Memory programming FEDR (Flash Data Register): F5H FEDR7 FEDR 6 FEDR 5 FEDR 4 FEDR 3 FEDR 2 FEDR 1 FEDR 0 Initial value: 00H FEDR[7:0] Flash and EEPROM data NOTES: Data register. In no program/erase/verify mode, READ/WRITE of FECR bits read or write data from FLASH to this register or from this register to Flash.

  • Page 206: Memory Map

    19. Memory programming MC97F6108A User’s manual 19.2 Memory map 19.2.1 Flash memory map Program memory uses 8Kbytes of Flash memory. It is read by byte and written by byte or page. One page is 32-bytes FFFFH pgm/ers/vfy Flash 1FFFH 8 Kbytes Code Memory...

  • Page 207: Serial In-System Program Mode

    MC97F6108A User’s manual 19. Memory programming 19.3 Serial in-system program mode Serial in-system program uses the interface of debugger which uses two wires. Refer to 23. Development tools in details about debugger. 19.3.1 Flash operation Configuration (This Configuration is just used for the description below) FEMR[4] &...

  • Page 208: Figure 102. The Sequence Of Bulk Erase Of Flash Memory

    19. Memory programming MC97F6108A User’s manual Master Reset Page Buffer Reset Page Buffer Load Configuration Reg.<0> Set Erase Erase Latency (500us) Page Buffer Reset Configuration Reg.<0> clear Reg.<6:5> setting Cell Read Pass/Fail? Figure 102. The Sequence of Bulk Erase of Flash Memory Flash read Enter OCD (=ISP) mode.
  • Page 209 MC97F6108A User’s manual 19. Memory programming Enable program mode Enter OCD(=ISP) mode. NOTE1 Set ENBDM bit of BCR. Enable debug and Request debug mode. Enter program/erase mode sequence. NOTE2 Write 0xAA to 0xF555. Write 0x55 to 0xFAAA. C. Write 0xA5 to 0xF555.
  • Page 210 19. Memory programming MC97F6108A User’s manual Flash page erase mode Enable program mode. Reset page buffer. FEMR: 1000_0001 FECR:0000_0010 Select page buffer. FEMR:1000_1001 Write ‘h00 to page buffer. (Data value is not important.) Set erase mode. FEMR:1001_0001 Set page address. FEARH:FEARM:FEARL=20’hx_xxxx Set FETCR.
  • Page 211 MC97F6108A User’s manual 19. Memory programming Flash OTP area read mode Enter OCD (=ISP) mode. Set ENBDM bit of BCR. Enable debug and Request debug mode. Select OTP area. FEMR:1000_0101 Read data from Flash. Flash OTP area write mode Enable program mode.
  • Page 212 19. Memory programming MC97F6108A User’s manual Flash OTP area erase mode Enable program mode. Reset page buffer. FEMR: 1000_0001 FECR:0000_0010 Select page buffer. FEMR:1000_1001 Write ‘h00 to page buffer. (Data value is not important.) Set erase mode and select OTP area. FEMR:1001_0101 Set page address.

  • Page 213: Table 32. Operation Mode

    MC97F6108A User’s manual 19. Memory programming Flash page buffer read Enable program mode. Select page buffer. FEMR:1000_1001 Read data from Flash. Summary of flash program/erase mode Table 32. Operation Mode Operation mode Description Flash read Read cell by byte. Flash write Write cell by bytes or page.

  • Page 214: Parallel Mode

    19. Memory programming MC97F6108A User’s manual 19.4 Parallel mode Parallel program mode transfers address and data in the byte unit. 3-byte address can be entered by one from the lease significant byte of address. If only LSB is changed, only one byte can be transferred.

  • Page 215: Parallel Mode Instruction Format

    MC97F6108A User’s manual 19. Memory programming 19.4.1 Parallel mode instruction format Table 34. Parallel Mode Instruction Format Instruction Signal Instruction Sequence n-byte data nALE read with 3- byte address PDATA ADDRL ADDRM ADDRH DATA0 DATA1 DATAn n-byte data nALE write with 3-...

  • Page 216: Parallel Mode Timing Diagram

    19. Memory programming MC97F6108A User’s manual 19.4.2 Parallel mode timing diagram 1 - byte read with 3 -byte address 1 - byte read with 2 -byte address 2 - byte read with 1 -byte address Write Write Write Read Write...

  • Page 217: Mode Entrance Method Of Isp Mode

    MC97F6108A User’s manual 19. Memory programming 19.5 Mode entrance method of ISP mode 19.5.1 Mode entrance method for ISP Table 35. Mode Entrance Method for ISP TARGET MODE DSDA DSCL DSDA OCD(ISP) ‘hC ‘hC ‘hC Release from worst 1.7V Power on reset...

  • Page 218: Security

    19.6 Security MC97F6108A provides Lock bits which can be left un-programmed (“0”) or can be programmed (“1”) to obtain the additional features listed in Table 37. The Lock bit can only be erased to “0” with the bulk erase command and a value of more than 0x80 at FETCR.

  • Page 219: Configure Option

    MC97F6108A User’s manual 19. Memory programming 19.7 Configure option For the configure option control, corresponding data should be written in the configure option area (003EH to 003FH) by programmer (writer tools). FUSE_CFG0 (Pseudo-Configure Data): OTP Address 2000H BSIZE1 BSIZE0 RSTEN –...

  • Page 220: Electrical Characteristics

    20. Electrical characteristics MC97F6108A User’s manual Electrical characteristics 20.1 Absolute maximum ratings Table 38. Absolute Maximum Ratings Parameter Symbol Rating Unit Remark Supply voltage -0.3~+6.5 – -0.3~+0.3 Normal voltage pin -0.3 ~ VDD+0.3 Voltage on any pin with respect to VSS -0.3 ~ VDD+0.3...

  • Page 221: Internal Rc Oscillator Characteristics

    MC97F6108A User’s manual 20. Electrical characteristics 20.3 Internal RC oscillator characteristics Table 40. Internal RC Oscillator Characteristics =-40°C ~ +85°C, VDD=2.7V ~ 5.5V, VSS=0V) Parameter Symbol Conditions Unit Frequency = 2.7 – 5.5V, T =-40°C ~ +85°C – – = +25°C ±1.0...

  • Page 222: A/D Converter Characteristics

    20. Electrical characteristics MC97F6108A User’s manual 20.6 A/D Converter characteristics Table 43. A/D Converter Characteristics =-40°C ~ +85°C, VDD=2.7V ~ 5.5V, VSS=0V) Parameter Symbol Conditions Unit Resolution – – – – Integral non-linearity AVREF=2.7V ~ 5.5V – – ±4 fx = 8MHz Differential non-linearity –...

  • Page 223: Brown Out Detector Characteristics

    MC97F6108A User’s manual 20. Electrical characteristics 20.8 Brown out Detector characteristics Table 45. Brown out Detector Characteristics =-40°C ~ +85°C, VDD=2.7V ~ 5.5V, VSS=0V) Parameter Symbol Conditions Unit BOD6 – BOD5 BOD4 Detection level BOD3 BOD2 BOD1 Hysteresis △V –...

  • Page 224: Dc Characteristics

    20. Electrical characteristics MC97F6108A User’s manual 20.10 DC characteristics Table 47. DC Characteristics = -40°C ~ +85°C, VDD= 2.7V ~ 5.5V, VSS= 0V, f = 16MHz) Parameter Symbol Conditions Unit Input high All input pins 0.8VDD – voltage Input All input pins –...

  • Page 225: 20.11 Ac Characteristics

    MC97F6108A User’s manual 20. Electrical characteristics 20.11 AC characteristics Table 48. AC Characteristics = -40°C ~ +85°C, VDD= 2.7V ~ 5.5V) Parameter Symbol Conditions Unit Operating frequency fMCP System clock cycle time tSYS 62.5 Oscillation stabilization time tMST1 (16MHz) External interrupt input width...

  • Page 226: 20.12 Analog Comparator Characteristics

    20. Electrical characteristics MC97F6108A User’s manual 20.12 Analog comparator characteristics Table 49. Analog Comparator DC Characteristics = -40°C ~ +85°C, VDD= 2.7V ~ 5.5V) Parameter Conditions Unit Operating voltage (VDD) Operating current (I COMP Power down current Input offset voltage...

  • Page 227: 20.14 Usart Characteristics

    MC97F6108A User’s manual 20. Electrical characteristics 20.14 USART characteristics Table 51. USART Characteristics = -40°C ~ +85°C, VDD=2.7V ~ 5.5V, f =8MHz) Parameter Symbol Unit Serial port clock cycle time 1800 x 16 2200 Output data setup to clock rising edge...

  • Page 228: 20.15 Spi Characteristics

    20. Electrical characteristics MC97F6108A User’s manual 20.15 SPI characteristics Table 52. SPI Characteristics =-40°C– +85°C, VDD=2.7V – 5.5V) Parameter Symbol Conditions Unit Output clock pulse period tSCK Internal SCK source – – Input clock pulse period External SCK source –...

  • Page 229: 20.16 I2C Characteristics

    MC97F6108A User’s manual 20. Electrical characteristics 20.16 I2C characteristics Table 53. I2C Characteristics =-40°C ~ +85°C, VDD=2.7V ~ 5.5V) Parameter Symbol Standard Mode High-Speed Mode Unit Clock frequency tSCL Clock high pulse width tSCLH – – Clock low pulse width tSCLL –...

  • Page 230: 20.17 Data Retention Voltage In Stop Mode

    20. Electrical characteristics MC97F6108A User’s manual 20.17 Data retention voltage in STOP mode Table 54. Data Retention Voltage in STOP Mode =-40°C ~ +85°C, VDD=2.7V ~ 5.5V) Parameter Symbol Conditions Unit Data retention supply voltage – – DDDR Data retention supply current VDDR= 2.7V,...

  • Page 231: 20.18 Internal Flash Rom Characteristics

    MC97F6108A User’s manual 20. Electrical characteristics 20.18 Internal Flash ROM characteristics Table 55. Internal Flash ROM Characteristics =-40°C ~ +85°C, VDD=2.7V ~ 5.5V, VSS= 0V) Parameter Symbol Condition Unit Sector write time – – Sector erase time – – Code write protection time –...

  • Page 232: 20.20 Operating Voltage Range

    20. Electrical characteristics MC97F6108A User’s manual 20.20 Operating voltage range Figure 115. Operating Voltage Range 20.21 Recommended circuit and layout This 0.1uF capacitor should be within 1cm f rom t he VDD pin of MCU on the PCB layout. DC Power 0.1uF...

  • Page 233: 20.22 Typical Characteristics

    MC97F6108A User’s manual 20. Electrical characteristics 20.22 Typical characteristics Graphs and tables provided in this section are only for design guidance and are not tested or guaranteed. In graphs or tables some data are out of specified operating range (e.g. out of specified VDD range).

  • Page 234: Figure 118. Output Low Voltage (Vol)

    20. Electrical characteristics MC97F6108A User’s manual Figure 118. Output Low Voltage (VOL)

  • Page 235: Package Information

    MC97F6108A User’s manual 21. Package information Package information This chapter provides MC97F6108A package information. 21.1 20 SOP package information Figure 119. 20 SOP Package Outline...

  • Page 236: 16 Sopn Package Information

    21. Package information MC97F6108A User’s manual 21.2 16 SOPN package information Figure 120. 16 SOPN Package Outline...

  • Page 237: Ordering Information

    MC97F6108A User’s manual 22. Ordering information Ordering information Table 57. MC97F6108A Device Ordering Information Device name Flash XRAM IRAM Package MC97F6108ADBN 8Kbytes 256bytes 256bytes 8inputs 20 SOP MC97F6108AMBN* 7inputs 16 SOPN * For available options or further information on the devices with an “*” mark, please contact the ABOV sales office.

  • Page 238: Development Tools

    ABOV semiconductor does not provide any compiler for MC97F6108A. It is recommended to consult a compiler provider. Since MC97F6108A has Mentor 8051EW as its core, and ROM is smaller than 64Kbytes in size, a developer can use any standard 8051 compiler of other providers.

  • Page 239: Programmers

    2 User VCC User GND DSCL DSDA Figure 122. Debugger (OCD1/OCD2) and Pinouts 23.3 Programmers 23.3.1 E-PGM+ E-PGM+ USB is a single programmer. A user can program MC97F6108A directly using the E-PGM+. DSDA DSCL Figure 123. E-PGM+ (Single Writer) and Pinouts...

  • Page 240: Ocd Ii Emulator

    23. Development tools MC97F6108A User’s manual 23.3.2 OCD II emulator OCD II emulator allows a user to write code on the device too, since OCD II debugger supports ISP (In System Programming). It doesn’t require additional H/W, except developer’s target system.

  • Page 241: Flash Programming

    23.4 Flash programming Program memory of MC97F6108A is a Flash type. This Flash ROM is accessed through four pins such as DSCL, DSDA, VDD, and VSS in serial data format. For more information about Flash memory programming, please refer to 19. Memory programming.

  • Page 242: Circuit Design Guide

    23. Development tools MC97F6108A User’s manual 23.4.2 Circuit design guide When programming Flash memory, the programming tool needs 4 signal lines, DSCL, DSDA, VDD, and VSS. If a user designs a PCB circuit, the user should consider the usage of these 4 signal lines for the on-board programming.

  • Page 243: On-Chip Debug System

    On-chip debug system MC97F6108A supports On-chip debug system (OCD II). We recommend developing and debugging program with MC97F6108A. On-chip debug system (OCD II) of MC97F6108A can be used for programming the non-volatile memories and on-chip debugging. Detail descriptions for programming via the OCD II interface can be found in this section.

  • Page 244: Figure 126. On-Chip Debugging System In Block Diagram

    23. Development tools MC97F6108A User’s manual Figure 126 shows a block diagram of the OCD II interface and the On-chip Debug system. Figure 126. On-Chip Debugging System in Block Diagram...

  • Page 245: Two-Pin External Interface

    MC97F6108A User’s manual 23. Development tools 23.5.1 Two-pin external interface Basic transmission packet 10-bit packet transmission using two-pin interface.  1-packet consists of 8-bit data, 1-bit parity and 1-bit acknowledge.  Parity is even of ‘1’ for 8-bit data in transmitter.

  • Page 246: Figure 128. Data Transfer On Twin Bus

    23. Development tools MC97F6108A User’s manual Packet transmission timing Figure 128. Data Transfer on Twin Bus Figure 129. Bit Transfer on Serial Bus Figure 130. Start and Stop Condition...

  • Page 247: Figure 131. Acknowledge On Serial Bus

    MC97F6108A User’s manual 23. Development tools Figure 131. Acknowledge on Serial Bus Figure 132. Clock Synchronization during Wait Procedure...

  • Page 248: Figure 133. Connection Of Transmission

    23. Development tools MC97F6108A User’s manual Connection of transmission Two-pin interface connection uses open-drain (wire-AND bidirectional I/O). Figure 133. Connection of Transmission...

  • Page 249: Appendix

    MC97F6108A User’s manual Appendix Appendix Instruction table Instructions are either1, 2 or 3bytes long as listed in the ‘Bytes’ column below. Each instruction takes either 1, 2 or 4 machine cycles to execute as listed in the following table. 1 machine cycle comprises 2 system clock cycles.

  • Page 250: Table 61. Instruction Table: Logical

    Appendix MC97F6108A User’s manual Table 61. Instruction Table: Logical Logical Mnemonic Description Bytes Cycles Hex code ANL A,Rn AND register to A 58-5F ANL A,dir AND direct byte to A ANL A,@Ri AND indirect memory to A 56-57 ANL A,#data...

  • Page 251: Table 62. Instruction Table: Data Transfer

    MC97F6108A User’s manual Appendix Table 62. Instruction Table: Data Transfer Data transfer Mnemonic Description Bytes Cycles Hex code MOV A,Rn Move register to A E8-EF MOV A,dir Move direct byte to A MOV A,@Ri Move indirect memory to A E6-E7...

  • Page 252: Table 63. Instruction Table: Boolean

    Appendix MC97F6108A User’s manual Table 63. Instruction Table: Boolean Boolean Mnemonic Description Bytes Cycles Hex code CLR C Clear carry CLR bit Clear direct bit SETB C Set carry SETB bit Set direct bit CPL C Complement carry CPL bit...

  • Page 253: Table 64. Instruction Table: Branching

    MC97F6108A User’s manual Appendix Table 64. Instruction Table: Branching Branching Mnemonic Description Bytes Cycles Hex code ACALL addr 11 Absolute jump to subroutine 11→F1 LCALL addr 16 Long jump to subroutine Return from subroutine RETI Return from interrupt AJMP addr 11 Absolute jump unconditional 01→E1...

  • Page 254: Table 65. Instruction Table: Miscellaneous

    Appendix MC97F6108A User’s manual Table 65. Instruction Table: Miscellaneous Miscellaneous Mnemonic Description Bytes Cycles Hex code No operation Table 66. Instruction Table: Additional Instructions Additional instructions (selected through EO[7:4]) Mnemonic Description Bytes Cycles Hex code MOVC M8051W/M8051EW-specific instruction @(DPTR++),A supporting...

  • Page 255: Revision History

    MC97F6108A User’s manual Revision history Revision history Date Version Description 2014.10.22 1.00 First creation 2015.09.01 1.01 Added VDD rising rate. Removed LVDRF flag in RSFR register. Removed IRCOFF in SCCR register. Removed LVROFF in BODR register. Changed timing for detecting the Comparator2 output when it is used to auto-period mode.
  • Page 256 ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements, modifications, and improvements to ABOV products and/or to this document at any time without notice. ABOV does not give warranties as to the accuracy or completeness of the information included herein. Purchasers should obtain the latest relevant information of ABOV products before placing orders.

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