Power Fail Processor - Abov MC80F0304 User Manual

MC80F0304/08/16

21. POWER FAIL PROCESSOR

circuitry to immunize against power noise. A configuration reg- The MC80F0304/0308/0316 has an on-chip power fail detection age Detector Register" on page 112.
ister, PFDR, can enable or disable the power fail detect circuitry. In the in-circuit emulator, power fail function is not implemented
Whenever V DD falls close to or below power fail voltage for opment of user program, this function may be experimented or and user can not experiment with it. Therefore, after final devel-
ing to PFDM bit of PFDR. Refer to "Figure 21-1 Power Fail Volt- 100ns, the power fail situation may reset or freeze MCU accord- evaluated.
7 6 5 4 3 2 R/W R/W 1 R/W 0
PFDR - - - - - PFDEN PFDM PFDS INITIAL VALUE: ---- -000 ADDRESS: 0F7 H
B
Power Fail Status 0: Normal operate
1: Set to "1" if power fail is detected
PFD Operation Mode
1 : MCU will be reset by power fail detection 0 : MCU will be frozen by power fail detection
* Cautions : Be sure to set bits 3 through 7 to "0". 0: Power fail detection disable PFD Enable Bit
1: Power fail detection enable
Figure 21-1 Power Fail Voltage Detector Register
RESET VECTOR
PFDS =1 YES
NO
RAM Clear
Initialize RAM Data PFDS = 0
Skip the
Initialize Registers Initialize All Ports initial routine
Function
Execution
Figure 21-2 Example S/W of Reset flow by Power fail
112 November 4, 2011 Ver 2.12