Communication Operation - Abov MC80F0304 User Manual

MC80F0304/08/16
Baud rate generator control register (BRGCR)
This register sets the serial clock for serial interface. BRGCR is Figure 16-5 shows the format of BRGCR.
set by an 8 bit memory manipulation instruction. The RESET in-
put sets BRGCR to -001_0000B.
R/W R/W R/W R/W R/W R/W R/W
BRGCR - 7 TPS2 6 TPS1 TPS0 5 4 BTCL 3 MDL3 MDL2 2 1 MDL1 MDL0 0 ADDRESS: 0E8 H
INITIAL VALUE: -001 0000 B
UART Input Clock Selection
0001: f 0000: f SCK SCK ÷ 16 ÷ 17
0010: f 0011: f SCK SCK ÷ 19 ÷ 18
0101: f 0100: f SCK ÷ 20 ÷ 21
0110: f 0111: f SCK SCK ÷ 22 ÷ 23
1000: f SCK SCK ÷ 24
1010: f 1001: f SCK SCK ÷ 26 ÷ 25
1100: f 1011: f SCK SCK ÷ 27 ÷ 28
1101: f 1110: f SCK ÷ 30 ÷ 29
1111: Setting prohibited SCK
UART Source Clock Selection for 5 bit count
000: ACLK
001: f 010: f XIN XIN ÷ 4 ÷ 2
011: f 100: f XIN XIN ÷ 16 ÷ 8
101: f 110: f XIN ÷ 32 ÷ 64
111: f XIN XIN ÷ 128
Caution Writing to BRGCR during a communication operation may cause abnormal output from the baud rate generator and
disable further communication operations. Therefore, do not write to BRGCR during a communication operation.
Remarks 1. f SCK : Source clock for 5 bit counter
Figure 16-5 Baud Rate Generator Control Register (BRGCR) Format

16.3 Communication operation

The transmit operation is enabled when bit 7 (TXE) of the asyn- ASIMR is used to sample the RxD pin. Once reception of one
chronous serial interface mode register (ASIMR) is set to 1. The data frame is completed, a receive completion interrupt request
transmit shift register (TXR). The timing of the transmit comple- transmit operation is started when transmit data is written to the (INT_RX) occurs. Even if an error has occurred, the receive data in which the error occurred is still transferred to RXR. When
tion interrupt request is shown in Figure 16-6 . ASIMR bit 1 (ISRM) is cleared to 0 upon occurrence of an error,
chronous serial interface mode register (ASIMR) is set to 1, and The receive operation is enabled when bit 6 (RXE) of the asyn- not occur in case of error occurrence. Figure 16-6 shows the tim- and INT_RX occurs. When ISRM bit is set to 1, INT_RX does
input via the RxD pin is sampled. The serial clock specified by ing of the asynchronous serial interface receive completion inter-
November 4, 2011 Ver 2.12 89