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Abov MC96FR364B User Manual

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MC96FR364B
ABOV SEMICONDUCTOR Co., Ltd.
8-BIT MICROCONTROLLERS
MC96FR364B
User's Manual (Rev.1.4)
November, 2018 Rev.1.4
1

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  • Page 1 MC96FR364B ABOV SEMICONDUCTOR Co., Ltd. 8-BIT MICROCONTROLLERS MC96FR364B User’s Manual (Rev.1.4) November, 2018 Rev.1.4...

  • Page 2: Revision History

    MC96FR364B REVISION HISTORY REVISION 0.0 (February 19, 2013) Preliminary Version REVISION 1.0 (July 23, 2013) Initial Version REVISION 1.1 (December 11, 2014)  9.2.11 PORT 3  The address of P3 Data register is changed from 9F to C0 REVISION 1.2 (January 8, 2016) ...
  • Page 3 Additional information of this manual may be served by ABOV Semiconductor offices in Korea or Distributors. ABOV Semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, ABOV Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.

  • Page 4: Table Of Contents

    MC96FR364B Table of Contents REVISION HISTORY ............................2 Table of Contents ..............................4 List of Figures ............................... 6 MC96FR364B ............................... 9 1. OVERVIEW ............................... 9 1.1 Description ..............................9 1.2 Features ................................ 9 1.3 Ordering Information ..........................10 1.4 Development Tools ............................ 12 2.
  • Page 5 MC96FR364B 10.9 Generation of Branch Address to Interrupt Service Routine(ISR) ............57 10.10 Saving and Restoring General Purpose Registers .................. 58 10.11 Interrupt Timing ............................. 58 10.12 Interrupt Registers ..........................59 11. Peripheral Units .............................. 65 11.1 Clock Generator ............................65 11.2 Basic Interval Timer (BIT) ........................

  • Page 6: List Of Figures

    Figure 1-3 E-PGM+ ..........................13 Figure 1-4 PGMPlusLC-II ........................14 Figure 1-5 Gang programmer ....................... 14 Figure 2-1 Block Diagram of MC96FR364B ..................15 Figure 3-1 28 TSSOP Pinout MC96FR364BR ..................16 Figure 4-1 PKG DIMENSION (28 TSSOP) ..................18 Figure 6-1 General I/O ..........................
  • Page 7 MC96FR364B Figure 11-10 Timer 0,1 Operation in 8-bit Input Capture Mode ............79 Figure 11-11 Example of Capture Interval Calculation in 8-bit Input Capture Mode ......79 Figure 11-12 Block Diagram of Timer 0, 1 in 16-bit Capture Mode ............ 80 Figure 11-13 Block Diagram of Timer 1 in PWM mode ..............
  • Page 8 MC96FR364B Figure 11-54 Formats and States in the Slave Receiver Mode ............152 Figure 12-1 Wake-up from SLEEP mode by an interrupt ..............158 Figure 12-2 SLEEP mode release by an external reset ............... 158 Figure 12-3 Wake-up from STOP mode by an interrupt ..............159 Figure 12-4 STOP mode release by an external reset .................

  • Page 9: Mc96Fr364B

    CMOS 8-bit Flash Microcontroller : UR 1. OVERVIEW 1.1 Description The MC96FR364B is an advanced 8-bit microcontroller based on CMOS process with 64K Bytes of Flash. This is a powerful device which provides a highly flexible and cost effective solution to many embedded control applications.

  • Page 10: Ordering Information

    MC96FR364B FLASH : 1 • Operating Frequency • Flash secure protection 1 ~ 12MHz • Analog Comparator for IR learning • Operating Voltage 1.75 ~ 3.6V (@ 1 ~ 12MHz) • Power On Reset • Operating Temperature • Programmable Brown-Out Detector -20 ~ +70℃...

  • Page 11: Figure 1-1 Device Nomenclature

    MC96FR364B 1.3.1 Device Nomenclature Device nomenclature MC96FR364Bx MC96FR364Bx Family Name X=none MC96FR364B series MC96FR364BD series Package type TSSOP RoHS Halogen Free Packing Tape & Reel Figure 1-1 Device Nomenclature November, 2018 Rev.1.4...

  • Page 12: Development Tools

    1.4.1 Compiler ABOV semiconductor does not provide any compiler for MC96FR364B. As the CPU core of MC96FR364B is Mentor 8051, you can use all kinds of third party’s standard 8051 compiler. 1.4.2 OCD emulator and debugger OCD(On Chip Debugger) program is a debugging software for ABOV semiconductor’s 8051 MCU series.

  • Page 13: Figure 1-3 E-Pgm

    MC96FR364B 1.4.3.1 E-PGM+ E-PGM+ is a single write tool for ABOV MCUs. Features : Support ABOV / ADAM devices   2~5 times faster than S-PGM+  Main controller : 32 bit MCU @72MHz  Buffer memory : 1MB Enter Key Connector.

  • Page 14: Figure 1-4 Pgmpluslc-Ii

    MC96FR364B 2. VDD 4. GND 6. Serial Clock (DSCL) 8. Serial Data (DSDA) Figure 1-4 PGMPlusLC-II 1.4.3.3 E-GANG4(6) The gang programmer, E-GANG4/(6) can program maximum4(6) MCUs at a time. So it is mainly used in mass production line. As gang programmer is standalone type, it does not require host PC.

  • Page 15: Block Diagram

    P14/SS1 SPI1 P15/XCK1 Figure 2-1 Block Diagram of MC96FR364B *Note: P32, P33, P34, and P35 do not have a pin in the PKG, but the port setting must be set to Input pull up, so there is no leakage current.

  • Page 16: Pin Configurations

    MC96FR364B 3. PIN CONFIGURATIONS 28 TSSOP (MC96FR364BR) REMOUT XOUT P22/INT3/SDA/DSDA P20/RESETB P21/INT2/SCL/DSCL P10/KS8/MOSI1 P07/KS7 P11/KS9/MISO1 P06/KS6 P12/KS10/INT0 P05/KS5/EC3 P13/KS11/INT1 P04/KS4/EC0 P14/KS12/SS1/INT2 P03/KS3/T3/PWM3 P15/KS13/XCK1/INT3 P02/KS2/T2 P16/KS14/MOSI0 P01/KS1/T1/PWM1 P17/KS15/MISO0 P00/KS0/T0 P30/SS0/EC2/EXTREF P37/INT1/SS0/SDA P31/XCK0/SENSOR P36/INT0/XCK0/SCL Figure 3-1 28 TSSOP Pinout MC96FR364BR November, 2018 Rev.1.4...

  • Page 17: Package Dimension

    MC96FR364B 4. PACKAGE DIMENSION November, 2018 Rev.1.4...

  • Page 18: Figure 4-1 Pkg Dimension (28 Tssop)

    MC96FR364B Figure 4-1 PKG DIMENSION (28 TSSOP) November, 2018 Rev.1.4...

  • Page 19: Pin Description

    MC96FR364B 5. PIN DESCRIPTION Function @RESET Shared with Name - 8-bit I/O port, P0. Input KS0/T0 - Can be set in input or output mode bitwise. KS1/T1/PWM1 - Internal pull-up resistor can be activated by KS2/T2 setting PxnPU bit in PxPU register when this port is used as input port.
  • Page 20 MC96FR364B Function @RESET Shared with Name - 8-bit I/O port, P3. Input SS0/EC2/EXTR - Can be set in input or output mode bitwise. - Internal pull-up resistor can be activated by XCK0/ SENSOR setting PxnPU bit in PxPU register when this SIGNAL port is used as input port.

  • Page 21: Port Structures

    MC96FR364B 6. PORT STRUCTURES 6.1 General Purpose I/O Port LevelShift ( 1.8V to ExtVDD) LevelShift (ExtVDD to 1.8V) BODOUT0 PxBPC (pull-up control) PxPU (pull-up selection) PxOD (open-drain) (data) SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE SUB-FUNC DIRECTION PxIO (direction) R(400Ω) PORTx INPUT...

  • Page 22: External Interrupt I/O Port

    MC96FR364B 6.2 External Interrupt I/O Port LevelShift ( 1.8V to ExtVDD) LevelShift (ExtVDD to 1.8V) BODOUT0 PxBPC (pull-up control) PxPU (pull-up selection) PxOD (open-drain) (data) SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE SUB-FUNC DIRECTION PxIO (direction) R(400Ω) EXTERNAL INTERRUPT POLARITY INTERRUPT ENABLE...

  • Page 23: Remout Port

    MC96FR364B 6.3 REMOUT Port Data Figure 6-3 REMOUT port November, 2018 Rev.1.4...

  • Page 24: Electrical Characteristics

    MC96FR364B 7. ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings Parameter Symbol Rating Unit -0.3~+4.0 Supply Voltage -0.3~+0.3 -0.3~VDD+0.3 -0.3~VDD+0.3 Normal Voltage Pin ∑ ∑ Total Power Dissipation Storage Temperature TSTG -45~+125 ℃ Table 7-1 Absolute Maximum Ratings NOTE Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

  • Page 25: Voltage Dropout Converter(Vdc) Characteristics

    RUN mode. STOP When the MC96FR364B enters STOP mode to save current consumption, all internal logics stop operation including x-tal oscillator . In this mode, the MC96FR364B makes the VDC to enter “STOP” mode , leading to least current consumption mode.

  • Page 26: Power-On Reset Characteristics

    7.5 POWER-ON RESET CHARACTERISTICS Parameter Symbol Condition Unit Operating Voltage Operating Temperature ℃ RESET Release Level Operating Current SIDD Table 7-5 Power-On Reset Characteristics 7.6 DC CHARACTERISTICS (VDD =1.75~3.6V, VSS =0V, f =12.0MHz, TA=-20~+70℃) Parameter Symbol Condition Unit Input Low Voltage P0,P1,P2,P3 (Schmitt Trigger Input) -0.5 0.2VDD...

  • Page 27: Ac Characteristics

    7.7 AC CHARACTERISTICS (VDD=3.3V±10%, VSS=0V, TA=-20~+70℃) Parameter Symbol Unit Operating Frequency fMCP System Clock Cycle Time tSYS 1000 Oscillation Stabilization Time (8MHz) tMST1 XIN, XOUT External Clock “H” or “L” Pulse Width tCPW External Clock Transition Time tRCP,tFCP Interrupt Input Width INT0~INT3 tSYS RESETB Input Pulse “L”...

  • Page 28: Usart Characteristics

    7.8 USART CHARACTERISTICS The following table and figure show the timing condition of USART in SPI or Synchronous mode of operation. The USART is one of peripherals in MC96FR364B. NOTE1 (VDD =3.3V±10%, VSS =0V, TA=-20~+70℃) Parameter Symbol NOTE2 Unit System clock period...

  • Page 29: Figure 7-2 Spi Master Mode Timing (Ucpha = 0, Msb First)

    /SS0 (OUTPUT) LEAD XCK0 0.8VDD (UCPOL=0) 0.2VDD (OUTPUT) XCKL XCKH XCK0 (UCPOL=1) (OUTPUT) MISO BIT 6 … 1 (INPUT) MOSI BIT 6 … 1 (OUTPUT) Figure 7-2 SPI master mode timing (UCPHA = 0, MSB first) /SS0 (OUTPUT) LEAD XCKx 0.8VDD (UCPOL=0) 0.2VDD...

  • Page 30: Figure 7-4 Spi Slave Mode Timing (Ucpha = 0, Msb First)

    /SS0 (OUTPUT) LEAD XCK0 0.8VDD (UCPOL=0) 0.2VDD (OUTPUT) XCKL XCKH XCK0 (UCPOL=1) (OUTPUT) MISO BIT 6 … 1 (INPUT) MOSI BIT 6 … 1 (OUTPUT) Figure 7-4 SPI slave mode timing (UCPHA = 0, MSB first) /SS0 (INPUT) LEAD XCKx 0.8VDD (UCPOL=0) 0.2VDD...

  • Page 31: Remout Port Characteristics

    7.9 REMOUT PORT CHARACTERISTICS IOL(mA) VDD=4V VDD=3V VDD=2V VOL(V) Figure 7-6 IOL vs VOL VOH(V) VDD=2V VDD=3V VDD=4V IOH(mA) Figure 7-7 IOH vs VOH November, 2018 Rev.1.4...

  • Page 32: Typical Characteristics

    7.10 TYPICAL CHARACTERISTICS These graphs and tables provided in this section are for design guidance only and are not tested or guaranteed. In some graphs or tables the data presented are outside specified operating range (e.g. outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range.

  • Page 33: Memory

    But the Program Memory can be erased or programmed by ISP(In System Programming) method. The MC96FR364B can assign maximum 64KB. Data Memory is composed of Internal RAM (IRAM), External RAM (XRAM). IRAM is read-writable and address space is 256B including Stack Pointer.

  • Page 34: Iram

    8.2 IRAM Upper Special Function 128 Bytes Registers Internal RAM 128 Bytes (Indirect Addressing) (Direct Addressing) Lower 128 Bytes Internal RAM (Direct or Indirect Addressing) Figure 8-2 DATA MEMORY (IRAM) Internal Data Memory is mapped in Figure 8-2. The memory space is shown divided into three blocks, which are generally referred to as the Lower 128, the Upper 128, and SFR space.

  • Page 35: Figure 8-3 Lower 128 Byte Of Iram

    RAM will contain 0BB Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space in MC96FR364B. 8.2.2 Direct And Indirect Address Area The 128 bytes of RAM which can be accessed by both direct and indirect addressing can be divided into 3 segments as listed below and shown in Figure 8.3.
  • Page 36 Their names and addresses are given in the Table 8.9. Note these SFRs are implemented using flip- flops within the core, not as RAM. The MC96FR364B has special registers which are provided by M8051 core. These are Program Counter(PC), Accumulator(A), B register(B), the Stack Pointer(SP), the Program Status Word(PSW), general purpose register(R0~R7) and DPTR (Data pointer register).

  • Page 37: Figure 8-4 Psw Register

    Data Pointer Register (DPTR) The Data Pointer (DPTR) is a 16-bit register which is used to form 16- bit addresses for External Data Memory accesses (MOVX A, @DPTR and MOVX @DPTR, A), for program byte moves (MOVC A, @A+DPTR) and for indirect program jumps (JMP @A+DPTR). Two true 16-bit operations are allowed on the Data Pointer –...

  • Page 38: Xram

    8.3 XRAM There’s another kind of RAM called XRAM (External RAM) in MC96FR364B and the size is 1792B, 0000 through 06FF . This address space is assigned to XDATA NOTE region and used for data storage. 06FF Upper 1792 Bytes...

  • Page 39: Registers

    8.4 Registers 8.4.1 SFR Map Reserved M8051 Compatible NOTE 0H/8H 1H/9H 2H/AH 3H/BH 4H/CH 5H/DH 6H/EH 7H/FH CFGCR UCTRL11 UCTRL12 UCTRL13 USTAT1 UBAUD1 UDATA1 --00_0000 WTCR0H WTCR0L WTCR1H WTCR1L WTCR2H WTCR2L KITSR 0000_0000 FARH FARM FARL FTCR UCTRL01 UCTRL02 UCTRL03 USTAT0 UBAUD0 UDATA0...
  • Page 40 8.4.2 XSFR Map Page Buffer (64Bytes) 0H/8H 1H/9H 2H/AH 3H/BH 4H/CH 5H/DH 6H/EH 7H/FH 8040 8038 PBUF_38 PBUF_39 PBUF_3A PBUF_3B PBUF_3C PBUF_3D PBUF_3E PBUF_3F 8030 PBUF_30 PBUF_31 PBUF_32 PBUF_33 PBUF_34 PBUF_35 PBUF_36 PBUF_37 8028 PBUF_28 PBUF_29 PBUF_2A PBUF_2B PBUF_2C PBUF_2D PBUF_2E PBUF_2F 8020...
  • Page 41 8.4.3 Compiler Compatible SFR Refer to section 8.2.3 for detailed description of these registers. ACC (Accumulator) Initial value : 00 Accumulator B (B Register) Initial value : 00 B Register SP (Stack Pointer) Initial value : 07 Stack Pointer DPL (Data Pointer Low Byte) Initial value : 00 Data Pointer Low Byte DPH (Data Pointer High Byte)
  • Page 42 Initial value : 00 Carry Flag. Receives carry out from bit 1 for ALU operands. Auxiliary Carry Flag. Receives carry out from bit 1 of addition operands. General Purpose Status Flag Register Bank Selection bit 1 Register Bank Selection bit 0 Overflow Flag.

  • Page 43: I/O Ports

    9.1 Introduction The MC96FR364B has four I/O ports (P0, P1, P2, P3). Each port can be easily configured by software whether to use internal pull up resistor or not, whether to use open drain output or not, or whether the pin is input or output.
  • Page 44 9.2.6 Pin Change Interrupt Enable Register (P0PC) P0 port support Pin Change Interrupt (PCI) function. Pin Change Interrupt will trigger if any pin changes its status when P0nPC is set to 1. At reset, PCI function is disabled for all P0 pins. 9.2.7 Register Map Name Address...
  • Page 45 9.2.8 PORT 0 P0 (P0 Data Register) Initial value : 00 P0[7:0] I/O Data P0IO (P0 Direction Register) P07IO P06IO P05IO P04IO P03IO P02IO P01IO P00IO Initial value : 00 P0IO[7:0] P0 Direction Input Output P0PU (P0 Pull-up Resistor Selection Register) 2F00 P07PU P06PU...
  • Page 46 Changed to input port and pull-up resistor is activated P0PC (P0 Pin Change Interrupt Enable Register) P07PC P06PC P05PC P04PC P03PC P02PC P01PC P00PC Initial value : 00 P0PC[7:0] Control Pin Change Interrupt function Disable PCI function Enable PCI function 9.2.9 PORT 1 P1 (P1 Data Register) Initial value : 00...
  • Page 47 P1OD[7:0] Control P1 port type when configured as output port. Push-pull type output drive Open-drain type output drive P1BPC (P1 Pull-up Control Register) 2F51 P17BPC P16BPC P15BPC P14BPC P13BPC P12BPC P11BPC P10BPC Initial value : 00 P1BPC[7:0] Control port direction and use of internal pull-up resistor when external VDD drops below V level.
  • Page 48 are switched to input state and internal pull up resistor is disabled. Because the floating input states can make the device to enter OCD-like mode, the internal pull up resistors of P22 and P21 ports are always activated while the device is in reset state to prevent wrong mode entering. P2OD (P2 Open-drain Selection Register) 2F0A P22OD...
  • Page 49 Initial value : 3C P3PU[7:0] P3 Pull-up Control Disable pull-up Enable pull-up P3OD (P3 Open-drain Selection Register) 2F0B P37OD P36OD P35OD P34OD P33OD P32OD P31OD P30OD Initial value : 00 P3OD[7:0] Control P0 port type when configured as output port. Push-pull type output drive Open-drain type output drive P3BPC (P3 Pull-up Control Register)
  • Page 50 External Interrupt 2 is triggered on P21 External Interrupt 2 is triggered on P14 INT1SWAP Select the source of External Interrupt 1 External Interrupt 1 is triggered on P37 External Interrupt 1 is triggered on P13 INT0SWAP Select the source of External Interrupt 0 External Interrupt 0 is triggered on P36 External Interrupt 0 is triggered on P12 November, 2018 Rev.1.4...

  • Page 51: Interrupt Controller

    Interrupt controller has 4 Interrupt Enable Registers (IE, IE1, IE2, IE3) and 2 Interrupt Priority Registers (IP, IP1). There are 16 interrupt sources in MC96FR364B and overall control is done by EA bit in IE register. When EA is set to 0, all interrupt requests are ignored. When EA is set to 1, each interrupt request is accepted or not by INTnE bit in IEx registers.

  • Page 52: External Interrupt

    10.2 External Interrupt The External Interrupts are triggered by the INT0, INT1, INT2, INT3 pins. The External Interrupts can be triggered by a falling or rising edge or a low or high level. The trigger mode and trigger level is controlled by External Interrupt Edge Register (EIEDGE) and External Interrupt Polarity Register (EIPOLA).

  • Page 53: Block Diagram

    10.3 Block Diagram IE[A8 IP[B8 IP1[F8 EIEDGE EIPOLA EIFLAG.0[`AC Priority High FLAG0 INT0 EIFLAG.1[AC FLAG1 INT1 EIFLAG.2[AC FLAG2 INT2 EIFLAG.3[AC FLAG3 INT3 INT5 IE1[A9 Reserved INT6 INT7 BODIF INT8 USTAT0.5 [E5 UART RX0 USTAT0.7/6 [E5 UART TX0 USTAT1.5 UART RX1 Release IE2[AA Stop/Sleep...

  • Page 54: Interrupt Vectors

    10.4 Interrupt Vectors There are 16 interrupt sources which are from internal peripherals or from external pin inputs. When a interrupt is requested while EA bit in IE register and its individual enable bit INTnE in IEx register is set, the CPU executes a long call instruction (LCALL) to the vector address listed in Table 10-2. As can be seen in the table, all interrupt vector has 8 bytes address space except for reset vector.

  • Page 55: Effective Time Of Interrupt Request

    finish current instruction and jump to the interrupt service routine. After executing the service routine, the program address is retrieved from the stack by executing RETI instruction to restart from the position where the interrupt is accepted. The following figure shows the sequence. NOTE Interrupt flags due to USART TX, KEYSCAN and FLASH are not auto-cleared when the CPU accepts the request.

  • Page 56: Multiple Interrupts

    EA & INTnE set Next Instruction Setting both EA bit and individual interrupt enable bit INTnE makes the pending interrupt active after executing the next instruction. Next Instruction Figure 10-4 Effective time of interrupt request after setting IEx registers 10.7 Multiple Interrupts If more than two interrupts are requested simultaneously, one of higher priority level is serviced first and others remain pending.

  • Page 57: Interrupt Service Procedure

    IP1 registers. Other interrupts having lower group priority than INT0 cannot be serviced until INT0 service routine is finished even if the INT0 interrupt handler allows those interrupt requests. Example) Software Multi Interrupt INT1 : IE, #01H ;Enable INT0 only IE1, #00H ;Disable other interrupts IE, #0FFH...

  • Page 58: Saving And Restoring General Purpose Registers

    10.10 Saving and Restoring General Purpose Registers INTxx : PUSH PSW PUSH DPL Main Task PUSH DPH Interrupt PUSH B Service Task PUSH ACC ∙ Saving ∙ Register Interrupt_Processing: ∙ ∙ Restoring POP ACC Register POP B POP DPH POP DPL POP PSW RETI Figure 10-8 Processing General registers while an interrupt is serviced...

  • Page 59: Interrupt Registers

    vector address to the CPU, M8051W and the CPU acknowledges the request at the first cycle of the next command to jump to the interrupt vector address. NOTE command cycle C?P? : L=Last cycle, 1=1 cycle or 1 phase, 2=2 cycle or 2 phase 10.12 Interrupt Registers...
  • Page 60 10.12.5 External Interrupt Edge Register (EIEDGE) External Interrupt Edge Register decides the trigger mode of external interrupt, edge or level mode. To make a external interrupt triggered by a falling or rising edge, write ‘00 ’ to the corresponding bit position.
  • Page 61 10.12.8 Register Description IE (Interrupt Enable Register) INT5E INT4E- INT3E INT2E INT1E INT0E R/W- Initial value : 00 Globla Interrupt Enable Bit Ignore interrupt request from any interrupt source. Accept interrupt request INT5E Enable or disable Pin Change Interrupt Disable Enable INT4E Enable or disable External Interrupt 3...
  • Page 62 Disable Enable INT6E Reserved Disable enable IE2 (Interrupt Enable Register 2) INT17E INT16E- INT15E INT14E INT13E INT12E R/W- Initial value : 00 INT17E Enable or disable I2C interrupt Disable Enable INT16E Enable or disable Timer 3 Interrupt Disable Enable INT15E Enable or disable Timer 2 Interrupt Disable Enable...
  • Page 63 Enable INT19E Enable or disable KEYSCAN Interrupt Disable Enable INT18E REMOCON (Carrier generator) Interrupt Diable Enable IP (Interrupt Priority Register) R/W- Initial value : 00 IP1 (Interrupt Priority Register 1) IP15 IP14 IP13 IP12 IP11 IP10 R/W- Initial value : 00 IP[5:0], Select Interrupt Group Priority IP1[5:0]...
  • Page 64 EDGEnF Selects the trigger mode of each external interrupt pin. Trigger mode is also affected by the EDGEnR bit. External interrupt is triggered by level (default) External interrupt is triggered by a falling edge When EDGEnR and EDGEnF bits are set at the same time, an external interrupt is triggered by both rising and falling edge.

  • Page 65: Peripheral Units

    The clock generator module plays a main role in making a stable operating clock, SCLK. There’s only one clock source in MC96FR364B, which is the output of main oscillator, XINCLK, connected to the XIN and XOUT pins. The main clock input XINCLK is divided by 2, 4 or 8, and one of the divided clocks is used as internal operating clock, SCLK, according to the DIV[1:0] bits in SCCR register.
  • Page 66 SCCR System and Clock Control Register Table 11-1 Register Map of Clock Generator 11.1.4 Register Description SCCR (System and Clock Control Register) ROSCEN DIV1 DIV0 BCLKS MOSCEN CLKSEL R/W- Initial value : 08 ROSCEN The operation of RING Oscillation at stop mode. Ring-Oscillator is disabled at stop mode.

  • Page 67: Basic Interval Timer (Bit)

    11.2 Basic Interval Timer (BIT) 11.2.1 Overview BIT module is a 8-bit counter used to guarantee oscillator stabilization time when MC96FR364B is reset or waken from STOP mode. The BIT counter is clocked by a clock divided from system clock(SCLK) and the divide ratio is selected from BCK[2:0] bits in BCCR register, from 16 to 2048. At reset, the BIT counter is clocked by a clock which is divided by 512 from SCLK.
  • Page 68 11.2.4 Register Description BCCR (BIT Clock Control Register) BITF BCK2 BCK1 BCK0 BCLR PRD2 PRD1 PRD0 Initial value : 57 BITF Reflects the state of BIT interrupt. To clear this flag, write ‘0’ to this bit position. The BIT interrupt occurs when BIT counter reaches to the pre- defined value.
  • Page 69 Initial value : 00 BIT[7:0] BIT counter value November, 2018 Rev.1.4...

  • Page 70: Watch Dog Timer (Wdt)

    BIT overflow period and WDTR value, and is calculated as follows. WDT Interrupt Interval = (BIT overflow period) x (WDTR + 1) NOTE MC96FR364B has only one clock source, XINCLK, and in STOP mode, the main oscillator stops. Also, the WDT/BIT module stops operation. 11.3.2 Block Diagram...
  • Page 71 11.3.3 Register Map Name Address Default Description WDTR Watch Dog Timer Register WDTCR Watch Dog Timer Counter Register WDTMR Watch Dog Timer Mode Register Table 11-3 Register Map of WDT 11.3.4 Register Description WDTR (Watch Dog Timer Register, Write Case) WDTR7 WDTR 6 WDTR 5...

  • Page 72: Figure 11-4 Wdt Interrupt And Reset Timing

    WDT interrupt not occurred WDT interrupt occurred 11.3.5 WDT Interrupt Timing Source Clock BIT Overflow WDTCR[7:0] Counter Clear WDTR[7:0] WDTCL Occur Match WDTIF WDTR  0000_0011b Detect Interrupt WDTRESETB RESET Figure 11-4 WDT Interrupt and Reset Timing November, 2018 Rev.1.4...

  • Page 73: Timer/Pwm

    11.4 TIMER/PWM 11.4.1 8-bit Timer/Event Counter 0, 1 11.4.1.1 Overview Timer 0 and Timer 1 can be used as either separate 8-bit Timer/Counter or one combined 16-bit Timer/Counter. Each 8-bit Timer/Event Counter module has a multiplexer, 8-bit timer data register, 8- bit counter register, mode control register, input capture register and comparator.

  • Page 74: Figure 11-5 Block Diagram Of Timer 0,1 In 8-Bit Timer/Counter Mode

    11.4.1.2 8-Bit Timer/Counter Mode 8-bit Timer/Counter Mode is selected when the T0CR and T1CR registers are configured as follows. ADDRESS : B2 T0CR T0EN T0_PE CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST INITIAL VALUE : 0000_0000 ADDRESS : B4 T1CR POL1 16BIT PWM1E CAP1...

  • Page 75: Figure 11-6 Interrupt Period Of Timer 0, 1

    Match with T0DR/T1DR T0DR/T1DR Value Count Pulse Period Up-count TIME Interrupt Period x (n+1) Timer 0, 1 (T0IF, T1IF) Occur Occur Occur Interrupt Interrupt Interrupt Interrupt Figure 11-6 Interrupt Period of Timer 0, 1 T0DR/T1DR Value Disable Enable Clear&Start STOP Up-count TIME Timer 0, 1...

  • Page 76: Figure 11-8 Block Diagram Of Timer 0, 1 In 16-Bit Timer/ Counter Mode

    11.4.1.3 16-bit Timer/Counter Mode When Timer 0, 1 are configured as 16-bit Timer/Counter Mode, Timer 0 becomes the lower part of the new 16-bit counter. When the lower 8-bit counter T0 matches T0DR and higher 8-bit counter T1 matches T1DR simultaneously, a 16-bit timer interrupt is issued via Timer 0 interrupt(not Timer 1). Both T0 and T1 should use the same clock source, which leads to the configuration, T1CK1=1, T1CK0=1 and 16BIT=1 in T1CR register.
  • Page 77 11.4.1.4 8-bit Capture Mode By setting CAP0(CAP1) to ‘1’ in T0CR(T1CR) register, Timer 0(Timer 1) operates in Capture Mode. Basic timer function is still effective even in capture mode. So when the counter value reaches to the pre-defined data value in data register, an interrupt can be issued. When an external interrupt generating condition is detected on port P36(P37), the counter value is captured into capture register CDR0(CDR1).

  • Page 78: Figure 11-9 Block Diagram Of Timer 0, 1 In 8-Bit Capture Mode

    ADDRESS : B2 T0CR T0EN T0_PE CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST INITIAL VALUE : 0000_0000 ADDRESS : B4 T1CR POL1 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST INITIAL VALUE : 0000_0000 T0ST T0EN&T0CN ÷2 8-bit Timer2 Counter ÷4 ÷16 T0(8-bit) ÷64 SCLK...

  • Page 79: Figure 11-10 Timer 0,1 Operation In 8-Bit Input Capture Mode

    CDR0, CDR1 Load T0/T1 Value Count Pulse Period Up-count TIME Ext. INT0 PIN Interrupt Request (INT0F,INT1F) Interrupt Interval Period Figure 11-10 Timer 0,1 Operation in 8-bit Input Capture Mode T0, T1 Interrupt Request (T0F,T1F) Ext. INT0 PIN Interrupt Request (INT0F,INT1F) Interrupt Interval Period = FF + FF + YY...

  • Page 80: Figure 11-12 Block Diagram Of Timer 0, 1 In 16-Bit Capture Mode

    11.4.1.5 16-bit Capture Mode If two 8-bit timers are combined to operate as a single 16-bit timer, this new timer can be in 16-bit Capture Mode. The operating mechanism is just like a 8-bit timer in capture mode except counter and capture register is 16-bit wide which are concatenated T0+T1 and CDR0+CDR1.

  • Page 81: Figure 11-13 Block Diagram Of Timer 1 In Pwm Mode

    Frequency Resolution T1CK[1:0]=00 (125ns) T1CK[1:0]=01 (250ns) T1CK[1:0]=10 (2us) 10-bit 7.8KHz 3.9KHz 0.49KHz 9-bit 15.6KHz 7.8KHz 0.98KHz 8-bit 31.2KHz 15.6KHz 1.95KHz 7-bit 62.4KHz 31.2KHz 3.91KHz Table 11-5 PWM Frequency vs. Resolution (In case frequency of SCLK(=f ) is 8MHz) SCLK The POL bit in T1CR register determines the polarity of PWM waveform. Setting POL=1 makes PWM waveform high for duty value.

  • Page 82: Figure 11-14 Example Of Pwm Waveform

    Source Clock SCLK T1/PWM1 POL0 = 1 T1/PWM1 POL0 = 1 Duty Cycle(1+80 )X250ns = 32.25us Period Cycle(1+3FF )X250ns = 256us  3.9kHz T1CK[1:0] = 00 PW1H3 PW1H2 PWM1PR(8-bit) SCLK PWM1HR = 03 PWM1PR = FF PWM1DR = 80 PW1H1 PW1H0 PWM1DR(8-bit) Figure 11-14 Example of PWM Waveform (In case frequency of SCLK(=f...
  • Page 83 T1DR Timer 1 Data Register PWM1PR Timer 1 PWM Period Register Timer 1 Register PWM1DR Timer 1 PWM Duty Register CDR1 Capture 1 Data Register PWM1HR Timer 1 PWM High Register Table 11-6 Register Map of Timer 0, 1 11.4.1.8 Register Description T0CR (Timer 0 Mode Control Register) T0EN T0_PE...
  • Page 84 Initial value : 00 T0[7:0] T0 Counter value T0DR (Timer 0 Data Register, Write Case) T0D7 T0D6 T0D5 T0D4 T0D3 T0D2 T0D1 T0D0 Initial value : FF T0D[7:0] T0 Compare data CDR0 (Capture 0 Data Register, Read Case) CDR07 CDR06 CDR05 CDR04 CDR03...
  • Page 85 Stops counting Clear counter and starts up-counting T1DR (Timer 1 Data Register, Write Case) T1D7 T1D6 T1D5 T1D4 T1D3 T1D2 T1D1 T1D0 Initial value : FF T1D[7:0] T1 Compare data PWM1PR (Timer 1 PWM Period Register, Write Case) T1PP7 T1PP6 T1PP5 T1PP4 T1PP3...
  • Page 86 Initial value : 00 T1_PE Controls whether to output Timer 1 output or not through I/O pin. Note this bit is write-only. Timer 1 output does not come out through I/O pin Timer 1 output overrides the normal port functionality of I/O pin PW1H[3:2] High (bit [9:8]) value of PWM period PW1H[1:0]...

  • Page 87: Figure 11-16 Block Diagram Of 16-Bit Timer 2 In Output Compare Or Event Counter Mode

    ADDRESS : CE EC2E T2_PE CAP2 T2CK2 T2CK1 T2CK0 T2CN T2CR T2ST INITIAL VALUE : 0000_0000 EC2 (or IRSensor) T2ST T2CN ÷1 16-bit Timer2 Counter ÷2 ÷4 Clear ÷8 (8-bit) (8-bit) SCLK ÷16 ÷64 ÷256 Timer2 T2IF Interrupt Comparator T2DRH T2DRL (8-bit) (8-bit)

  • Page 88: Figure 11-18 Block Diagram Of Timer 2 In Carrier Counting Mode

    When T2H+T2L reaches to the value of T2DRH+T2DRL, an interrupt is requested if enabled. When a compare-match occurs, the counter values T2H and T2L are captured into the capture registers CDR2H and CDR2L respectively. At the same time, the counter is cleared to 0000 and starts up- counting.
  • Page 89 Timer 2 Counter Low T2DRL Timer 2 Data Register Low CDR2L Timer 2 Capture Data Register Low Table 11-7 Register Map of Timer 2 11.4.2.6 Register Description CDR2H, T2DRH and T2H registers share peripheral address. Reading T2DRH gives CDR0 in Capture Mode, T2H in Output Compare Mode.
  • Page 90 T2L7 T2L6 T2L5 T2L4 T2L3 T2L2 T2L1 T2L0 Initial value : 00 T2L[7:0] T2 Counter Low T2DRL (Timer 2 Data Register Low, Write Case) T2DRL7 T2DRL6 T2DRL5 T2DRL4 T2DRL3 T2DRL2 T2DRL1 T2DRL0 Initial value : FF T2DRL[7:0] T2 Compare Data Low CDR2L (Capture Data Register 2 Low, Read Case) CDR2L7 CDR2L6...
  • Page 91 11.4.3 16-bit Timer 3 11.4.3.1 Overview 16-bit Timer 3 is composed of Multiplexer, Timer Data Register High/Low, Timer Register High/Low, Input Capture Register High/Low, Mode Control Register, PWM Duty High/Low and PWM Period High/Low Register. Timer 3 is can be clocked by Carrier Signal(CRF) from Carrier Generator module or by an internal clock source deriving from clock divider logic where the base clock is SCLK.

  • Page 92: Figure 11-19 Block Diagram Of Timer 3 In Output Compare Or Event Counter Mode

    ADDRESS : CA PWM3 T3CR EC3E CAP3 T3CK2 T3CK1 T3CK0 T3CN T3ST INITIAL VALUE : 0000_0000 ADDRESS : C9 T3CR2 T3REQ T2REQ T1REQ T0REQ T3_PE INITIAL VALUE : 0000_--00 EC3 (or IRSensor) T3ST T3CN ÷1 16-bit Timer3 Counter ÷2 ÷4 Clear ÷8 (8-bit)

  • Page 93: Figure 11-20 Block Diagram Of Timer 3 In Capture Mode

    ADDRESS : CA T3CR PWM3 EC3E CAP3 T3CK2 T3CK1 T3CK0 T3CN T3ST INITIAL VALUE : 0000_0000 ADDRESS : C9 T3CR2 T3REQ T2REQ T1REQ T0REQ T3_PE INITIAL VALUE : 0000_--00 EC3 (or IRSensor) T3ST T3CN ÷1 ÷2 16-bit Counter ÷4 ÷8 T3H(8-bit) T3L(8-bit) SCLK...

  • Page 94: Figure 11-21 Block Diagram Of Timer 3 In Carrier Counting Mode

    ADDRESS : CA T3CR PWM3 EC3E CAP3 T3CK2 T3CK1 T3CK0 T3CN T3ST INITIAL VALUE : 0000_0000 ADDRESS : DF IRCC2 T3EDG T3EDG T2EDG T2EDG T3IR T2IR INITIAL VALUE : 0000_0000 T3ST T3CN 16-bit Timer3 Counter Clear IRSensor (8-bit) (8-bit) Timer3 T3IF Interrupt Comparator...

  • Page 95: Figure 11-22 Block Diagram Of Timer 3 In Pwm Mode

    ADDRESS : CA T3CR PWM3 EC3E CAP3 T3CK2 T3CK1 T3CK0 T3CN T3ST INITIAL VALUE : 0000_0000 ADDRESS : C9 T3CR2 T3REQ T2REQ T1REQ T0REQ T3_PE INITIAL VALUE : 0000_--00 16-bit Timer3 PWM Period Register PWM3PRH PWM3PRL (8-bit) (8-bit) T3_PE ÷1 T3ST T3CN ÷2...

  • Page 96: Figure 11-23 Example Of Pwm Waveform (In Case Of F Sclk =4Mhz)

    Source Clock SCLK T3/PWM3 POL0 = 1 T3/PWM3 POL0 = 1 Duty Cycle(1+0080 )X500ns = 64.50us Period Cycle(1+03FF )X500ns = 512us  1.95kHz T3CK[2:0] = 00 PWM3PRH(8-bit) PWM3PRL(8-bit) SCLK PWM3PRH = 03 PWM3PRL = FF PWM3DRH = 00 PWM3DRH(8-bit) PWM3DRL(8-bit) PWM3DRL = 80 Figure 11-23 Example of PWM waveform (In case of f =4MHz)
  • Page 97 CDR3L, PWM3DRL and T3L registers share peripheral address. When PWM mode is enabled, reading this address gives PWM3DRL. When PWM mode is disabled, reading this address gives CDR3L in Capture Mode or T3L in Output Compare Mode. Writing this address alters PWM3DRL when PWM3E bit is ‘1’.
  • Page 98 Timer 2 interrupt not occurred Timer 2 interrupt occurred T1REQ NOTE Timer 1 Interrupt Flag Timer 1 interrupt not occurred Timer 1 interrupt occurred T0REQ NOTE Timer 0 Interrupt Flag Timer 0 interrupt not occurred Timer 0 interrupt occurred POL3 Selects polarity of PWM PWM waveform is low for duty value PWM waveform is high for duty value...
  • Page 99 CDR3H (Capture Data Register 3 High, Read Case) CDR3H7 CDR3H6 CDR3H5 CDR3H4 CDR3H3 CDR3H2 CDR3H1 CDR3H0 Initial value : 00 CDR3H[7:0] T3 Capture Data High PWM3DRH (PWM3 Duty Register High, Write Case) T3PDH7 T3PDH6 T3PDH5 T3PDH4 T3PDH3 T3PDH2 T3PDH1 T3PDH0 Initial value : 00 T3PDH[7:0] PWM3 Duty High...
  • Page 100 P3PPH7 P3PPH6 P3PPH5 P3PPH4 P3PPH3 P3PPH2 P3PPH1 P3PPH0 Initial value : FF P3PPH[7:0] PWM3 Period High NOTE Writing is effective only when PWM3E = 1 and T3ST = 0. November, 2018 Rev.1.4...

  • Page 101: Watch Timer With Event Capture Function (Wt)

    11.5 Watch Timer with event capture function (WT) 11.5.1 Overview The watch timer (WT) has the function for RTC (Real Time Clock) operation. This module consists of the clock source select circuit, timer counter circuit, output select circuit and control registers. To activate watch timer, determine the input clock source, output interval and then set WTEN bit in Watch Timer Mode Register (WTMR).

  • Page 102: Figure 11-25 Block Diagram Of Watch Timer In Ir Capture Mode

    IRCC1 CAP0/1/2EN (=Capture & IRCEN SINGLE PHASE WTIR Clear source) WTCR0H/L WTCR1H/L WTCR2H/L WTCL WTCL WTCL CAP0EN CAP1EN CAP2EN ÷1 OVF = T x WTIR 14-bit Up Counter ÷2 (WTIR) SCLK ÷3 ÷4 WTIF WTDR1:WTDR0 CP r SCLK WTMR WTEN OVFDIS WTCL WTCK1 WTCK0...
  • Page 103 11.5.3 Register Map Name Address Default Description WTMR Watch Timer Mode Register WTDR1 Watch Timer Data Register 1 WTDR0 Watch Timer Data Register 0 WTSR Watch Timer Status Register WTDRH Watch Timer Data Register High WTCR0H Watch Timer Capture Register0 High WTCR0L Watch Timer Capture Register0 Low WTCR1H...
  • Page 104 Initial value : 3F WTDR[13:8] Select WT overflow period. Reading this register returns the high 8-bit WTIR counter value. WT Interrupt Interval = (Twck x 2^14) x (7-bit WTDRH) + (Twck x 14-bit WTDR) WTDR0 (Watch Timer Data Register 0) WTDR7 WTDR6 WTDR5...
  • Page 105 WTCR0L (Watch Timer Capture Register 0 Low) WTCR007 WTCR006 WTCR005 WTCR004 WTCR003 WTCR002 WTCR001 WTCR000 Initial value : FF WTCR0[7:0] When WT is in IR capture mode, the low 8-bit of WTIR counter is captured to this register at the first falling edge (when PHASE bit is ‘0’) or first rising edge (when PHASE bit is ‘1’) of input carrier signal.
  • Page 106 captured to this register at the second falling edge (when PHASE bit is ‘0’) or second rising edge (when PHASE bit is ‘1’) of input carrier signal. This register is initialized by setting WTCL bit in WTMR. The WT interrupt is requested only when overflow condition occurs. That is when WT is in IR capture mode, the interrupt is not issued even when capture event is generated.

  • Page 107: Ir Capture Control (Ircc)

    11.6 IR Capture Control (IRCC) 11.6.1 Overview MC96FR364B has an IR capture module which receives and captures the incoming digital IR signal to detect the IR carrier frequency and count the carrier number. With this module, the Watch Timer and Timer 2 can be configured to operate in IR capture mode by setting IRCEN bit in IRCC1 register.
  • Page 108 11.6.3 Register Map Name Address Default Description IRCC0 IR Capture Control Register 0 IRCC1 IR Capture Control Register 1 IRCC2 IR Capture Control Register 2 Table 11-11 Register Map of IR Capture Control module 11.6.4 Register Description IRCC0 (IR Capture Control Register 0) IRAEN SENOEN REFSEL...
  • Page 109 No IRI input is generated IRI interrupt is generated on the condition by IREDGE[1:0] bits IREDGE[1:0] Select IRI interrupt triggering condition. IRI interrupt is disabled Interrupt is triggered on falling edge of IRI input Interrupt is triggered on rising edge of IRI input Interrupt is triggered on both edge of IRI input IRPOL Select the polarity of WT input source.
  • Page 110 Both edge The next table shows register setting for Timer 2 and 3 for IR capture features. IRCEN CAP2(3) T2(3)IR T2(3)EDGE[1:0] Timer 2(3) Operating Mode Normal 16-bit Counter Normal 16-bit Capture 01, 10, 11 IR Capture (Envelop detect) Count IR Carrier Table 11-12 Operating modes of Timer 2(3) November, 2018 Rev.1.4...

  • Page 111: Carrier Generator

    11.7 Carrier Generator 11.7.1 Overview MC96FR364B has a specific module to generate carrier signal for remote control application. The internal carrier(CRF) signal is AND-ed with register value(RODR) and outputs through REMOUT port. The frequency and duty ratio of carrier signal is controlled by two 8-bit registers, CFRH and CFRL.
  • Page 112 11.7.3 Register Map Name Address Default Description Remocon Mode Register RMR2 2F56 Remocon Mode Register 2 RDCH Remocon Data Counter High CFRH Carrier Frequency Register High CFRL Carrier Frequency Register Low RDCL Remocon Data Counter Low RODR Remocon Output Data Register Remocon Output Buffer RDBH Remocon Data Buffer High...
  • Page 113 Carrier Frequency Enable. This bit enables CRC counter. Carrier Frequency is not generated. Carrier Frequency is generated and goes out through the REMOUT port with RODR value and-ed. NOTE is the frequency of system clock, SCLK. SCLK RMR2 (Remocon Mode Register 2) 2F56 Initial value : 00 Carrier Mask Enable...
  • Page 114 RDB7 RDB6 RDB5 RDB4 RDB3 RDB2 RDB1 RDB0 Initial value : FF RDB[7:0] Remote Data Low Buffer (Lower byte of RDB). The RDB is transferred to RDR when interrupt occurs. RDRH (Remocon Data Register High) RDR15 RDR14 RDR13 RDR12 RDR11 RDR10 RDR9 RDR8...

  • Page 115: Figure 11-30 Period Of Carrier Signal And Remote Data Pulse

    Initial value : 00 Remote Data Output ROB (Remocon Output Buffer) Initial value : 00 Remote Data Output Buffer 11.7.5 Carrier Signal and Data Pulse The Remote Out signal(=CGOUT in Block Diagram) on REMOUT port is generated from carrier signal and RODR value.

  • Page 116: Figure 11-31 Remout By Crf & Rob (In Case Of Cen=1, Rdpe=1)

    11.7.6 Examples of REMOUT control Three examples of controlling REMOUT port are shown below. RDPE RDRH RDRL RDRH Match with RDRH/RDRL Remocon Interrupt 0 or 1 RODR = 01 RODR=00 RODR=01 REMOUT : Min. 0.5us ~ Max. 32.64ms @ 4MHz Figure 11-31 REMOUT by CRF &...

  • Page 117: Figure 11-33 Remout By Rodr

    In the last figure, RODR is updated directly by writing to this register when the 16-bit Timer 2, 3 interrupts occur. As shown, the REMOUT waveforms are different according to CEN bit. The function of “rdpe_disable_mode_init” is a prerequisite for RDPE disable mode. void rdpe_disable_mode_init() RMR = 0x08;...
  • Page 118 Registers CR_CLK=PS1 CR_CLK=PS3 Registers CR_CLK=PS1 CR_CLK=PS3 CFRH CFRL (us) (us) (us) (us) CFRH CFRL (us) (us) (us) (us) 8.00 8.00 32.00 32.00 0.25 0.25 1.00 1.00 8.25 8.25 33.00 33.00 0.50 0.50 2.00 2.00 8.50 8.50 34.00 34.00 0.75 0.75 3.00 3.00 8.75...

  • Page 119: Key Scan

    11.8 Key Scan 11.8.1 Overview Port 0 and Port 1 can be used as key input sources. If KEY interrupt is enabled, this can be a wake- up source in STOP mode. Usually Port 0(Port 1) is used as output strobe lines, and Port 1(Port 0) is used as key input sources.
  • Page 120 11.8.3 Register Map Name Address Default Description SMRR0 Standby Mode Release Register 0 SMRR1 Standby Mode Release Register 1 SRLC0 Standby Release Level Control Register 0 SRLC1 Standby Release Level Control Register 1 KITSR Key Interrupt Trigger Selection Register Table 11-15 Register Map of KEYSCAN module 11.8.4 Register Description SMRR0 (Standby Mode Release Register 0) SMRR07...
  • Page 121 SRLC1 (Standby Release Level Control Register 1) SRLC17 SRLC16 SRLC15 SRLC14 SRLC13 SRLC12 SRLC11 SRLC10 Initial value : 00 SRLC1[7:0] Selects the trigger level of key input & interrupt when Port 1 is used as key input source. Triggered by a low level Triggered by a high level KITSR (Key Interrupt Trigger Select Register) KITSR...

  • Page 122: Usart0/1

    11.9 USART0/1 11.9.1 Overview The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are listed below. - Full Duplex Operation (Independent Serial Receive and Transmit Registers) - Asynchronous or Synchronous Operation - Master or Slave Clocked Synchronous and SPI Operation - Supports all four SPI Modes of Operation (Mode 0, 1, 2, 3) - LSB First or MSB First Data Transfer @SPI mode...

  • Page 123: Figure 11-35 The Block Diagram Of Usart

    11.9.2 Block Diagram UBAUD SCLK Baud Rate Generator Master Clock Sync Logic XCKx Control UMSEL[1:0] Rx Interrupt RXDx/ MISOx Clock Control Recovery Data Receive Shift Register Recovery (RXSR) UMSEL1&UMSEL0 DOR/PE/FE UDATA[0] Master Checker (Rx) UDATA[1] Stop bit UMSEL0 (Rx) Generator UPM0 Parity TXDx/...

  • Page 124: Figure 11-36 The Block Diagram Of Clock Generation

    11.9.3 Clock Generation UBAUD SCLK (UBAUD+1) Prescaling Up-Counter txclk SCLK MASTER Edge Sync Register UMSEL0 Detector UCPOL XCKx rxclk Figure 11-36 The Block Diagram of Clock Generation The Clock generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation and those are Normal Asynchronous, Double Speed Asynchronous, Master Synchronous and Slave Synchronous.

  • Page 125: Figure 11-37 Synchronous Mode Xckn Timing

    11.9.4 External Clock (XCK) External clocking is used by the synchronous or spi slave modes of operation. External clock input from the XCK pin is sampled by a synchronization logic to remove meta-stability. The output from the synchronization logic must then pass through an edge detector before it can be used by the Transmitter and Receiver.

  • Page 126: Figure 11-38 Frame Format

    - 1 start bit - 5, 6, 7, 8 or 9 data bits - no, even or odd parity bit - 1 or 2 stop bits A frame starts with the start bit followed by the least significant data bit (LSB). Then the next data bits, up to a total of nine, are succeeding, ending with the most significant bit (MSB).
  • Page 127 11.9.8 USART Transmitter The USART Transmitter is enabled by setting the TXE bit in UCTRL1 register. When the Transmitter is enabled, the normal port operation of the TXD(=MOSI) pin is overridden by the serial output pin of USART. The baud-rate, operation mode and frame format must be setup once before doing any transmissions.
  • Page 128 11.9.8.4 Disabling Transmitter Disabling the Transmitter by clearing the TXE bit will not become effective until ongoing transmission is completed. When the Transmitter is disabled, the TXD(=MOSI) pin is used as normal General Purpose I/O (GPIO) or primary function pin. 11.9.9 USART Receiver The USART Receiver is enabled by setting the RXE bit in the UCTRL1 register.

  • Page 129: Figure 11-39 Start Bit Sampling

    The Frame Error (FE) flag indicates the state of the first stop bit. The FE flag is zero when the stop bit was correctly detected as one, and the FE flag is one when the stop bit was incorrect, ie detected as zero.

  • Page 130: Figure 11-40 The Sampling Of Data And Parity Bit

    When the Receiver is enabled (RXE=1), the clock recovery logic tries to find a high to low transition on the RXD(=MISO) line, the start bit condition. After detecting high to low transition on RXD(=MISO) line, the clock recovery logic uses samples 8,9, and 10 for Normal mode, and samples 4, 5, and 6 for Double Speed mode to decide if a valid start bit is received.
  • Page 131 11.9.10 SPI Mode The USART can be set to operate in industrial standard SPI compliant mode. The SPI mode has the following features. Full duplex, three-wire synchronous data transfer Master or Slave operation Supports all four SPI modes of operation (mode0, 1, 2, and 3) Selectable LSB first or MSB first data transfer Double buffered transmit and receive Programmable transmit bit rate...

  • Page 132: Figure 11-42 Spi Clock Formats When Ucpha=0

    (UCPOL=0) (UCPOL=1) SAMPLE MOSI MSB First BIT7 BIT6 … BIT2 BIT1 BIT0 LSB First BIT0 BIT1 … BIT5 BIT6 BIT7 MISO /SS OUT (MASTER) /SS IN (SLAVE) Figure 11-42 SPI Clock Formats when UCPHA=0 When UCPHA=0, the slave begins to drive its MISO output with the first data bit value when SS goes to active low.

  • Page 133: Figure 11-43 Spi Clock Formats When Ucpha=1

    (UCPOL=0) (UCPOL=1) SAMPLE MOSI MSB First BIT7 BIT6 … BIT2 BIT1 BIT0 LSB First BIT0 BIT1 … BIT5 BIT6 BIT7 MISO /SS OUT (MASTER) /SS IN (SLAVE) Figure 11-43 SPI Clock Formats when UCPHA=1 When UCPHA=1, the slave begins to drive its MISO output when SS goes active low, but the data is not defined until the first XCK edge.
  • Page 134 UCTRL12 USART1 Control 2 Register UCTRL13 USART1 Control 3 Register USTAT1 USART1 Status Register UBAUD1 USART1 Baud Rate Generation Register UDATA1 USART1 Data Register Table 11-18 Register map of USART 11.9.12 Register Description UCTRLx1 (USART0[1] Control 1 Register) / FA USIZE1 USIZE0 UMSEL1...
  • Page 135 with UCPOL bit, selects one of two clock formats for different kinds of synchronous serial peripherals. Leading edge means first XCK edge and trailing edge means 2 or last clock edge of XCK in one XCK pulse. And Sample means detecting of incoming receive bit, Setup means preparing transmit data.
  • Page 136 controls the direction of XCK pin. Slave mode operation and XCK is input pin. Master mode operation and XCK is output pin LOOPS Controls the Loop Back mode of USART, for test mode Normal operation Loop Back mode DISXCK In Synchronous mode of operation, selects the waveform of XCK output.
  • Page 137 CPU is in stop mode. This flag can be used to generate a WAKE interrupt. This bit is set only when in asynchronous mode of operation. NOTE No WAKE interrupt is generated. WAKE interrupt is generated. SOFTRST This is an internal reset and only has effect on USART. Writing ‘1’ to this bit initializes the internal logic of USART and is auto cleared.
  • Page 138 11.9.13 Baud Rate Setting (example) fOSC=1.00MHz fOSC=1.8432MHz fOSC=2.00MHz Baud U2X=0 U2X=1 U2X=0 U2X=1 U2X=0 U2X=1 Rate UBAU ERRO UBAU ERRO UBAU ERRO UBAU ERRO UBAU ERRO UBAU ERRO 2400 0.2% 0.2% 0.0% 0.0% 0.2% 0.2% 4800 0.2% 0.2% 0.0% 0.0% 0.2% 0.2% 9600...
  • Page 139 76.8K -7.0% 0.2% 0.0% 0.0% 0.0% 0.0% 115.2 8.5% -3.5% 0.0% 0.0% 0.0% 0.0% 230.4 8.5% 8.5% 0.0% 0.0% 0.0% 0.0% 250K 0.0% 0.0% -7.8% -7.8% -7.8% 5.3% 0.5M 0.0% -7.8% -7.8% -7.8% -7.8% November, 2018 Rev.1.4...

  • Page 140: I 2 C

    11.10 I 11.10.1 Overview The I C is one of industrial standard serial communication protocols, and which uses 2 bus lines Serial Data Line (SDA) and Serial Clock Line (SCL) to exchange data. Because both SDA and SCL lines are open-drain output, each line needs pull-up resistor. The features are as shown below. Compatible with I C bus standard Multi-master operation...

  • Page 141: Figure 11-45 Bit Transfer On The I C-Bus

    11.10.3 I C Bit Transfer The data on the SDA line must be stable during HIGH period of the clock, SCL. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. The exceptions are START(S), repeated START(Sr) and STOP(P) condition where data line changes when clock line is high.

  • Page 142: Figure 11-47 Stop Or Repeated Start Condition

    the most significant bit (MSB) first. If a slave can’t receive or transmit another complete byte of data until it has performed some other function, it can hold the clock line SCL LOW to force the master into a wait state. Data transfer then continues when the slave is ready for another byte of data and releases clock line SCL.

  • Page 143: Figure 11-49 Clock Synchronization During Arbitration Procedure

    11.10.7 Synchronization / Arbitration Clock synchronization is performed using the wired-AND connection of I C interfaces to the SCL line. This means that a HIGH to LOW transition on the SCL line will cause the devices concerned to start counting off their LOW period and it will hold the SCL line in that state until the clock HIGH state is reached.
  • Page 144 11.10.8 Operation The I C is byte-oriented and interrupt based. Interrupts are issued after all bus events except for a transmission of a START condition. Because the I C is interrupt based, the application software is free to carry on other operations during a I C byte transfer.
  • Page 145 3), move to step 6 after transmitting the data in I2CDR and if transfer direction bit is ‘1’ go to master receiver section. 7. 1-Byte of data is being transmitted. During data transfer, bus arbitration continues. 8. This is ACK signal processing stage for data packet transmitted by master. I C holds the SCL LOW.

  • Page 146: Figure 11-51 Formats And States In The Master Transmitter Mode

    The next figure depicts above process for master transmitter operation of I Master SLA+R S or Sr Receiver SLA+W 0x86 0x22 STOP 0x0E 0x87 LOST DATA STOP LOST LOST& Slave Receiver (0x1D) 0x0F 0x1D 0x1F or Transmitter (0x1F) 0x46 0x22 STOP 0x0E Other master continues...
  • Page 147 11.10.8.2 Master Receiver To operate I C in master receiver, follow the recommended steps below. 1. Enable I C by setting IICEN bit in I2CMR. This provides main clock to the peripheral. 2. Load SLA+R into the I2CDR where SLA is address of slave device and R is transfer direction from the viewpoint of the master.

  • Page 148: Figure 11-52 Formats And States In The Master Receiver Mode

    load SLA+R/W into the I2CDR and set the START bit in I2CMR. After doing one of the actions above, write arbitrary value to I2CSR to release SCL line. In case of 1) and 2), move to step 7. In case of 3), move to step 9 to handle STOP interrupt. In case of 4), move to step 6 after transmitting the data in I2CDR, and if transfer direction bit is ‘0’...
  • Page 149 11.10.8.3 Slave Transmitter To operate I C in slave transmitter, follow the recommended steps below. 1. If the main operating clock (SCLK) of the system is slower than that of SCL, load value 0x00 into I2CSDAHR to make SDA change within one system clock period from the falling edge of SCL.

  • Page 150: Figure 11-53 Formats And States In The Slave Transmitter Mode

    The next figure shows flow chart for handling slave transmitter function of I IDLE S or Sr SLA+R GCALL 0x97 0x1F LOST& 0x17 DATA 0x22 STOP 0x47 0x46 IDLE From master to slave / Interrupt, SCL line is held low Master command or Data Write From slave to master Interrupt after stop command...
  • Page 151 11.10.8.4 Slave Receiver To operate I C in slave receiver, follow the recommended steps below. 1. If the main operating clock (SCLK) of the system is slower than that of SCL, load value 0x00 into I2CSDAHR to make SDA change within one system clock period from the falling edge of SCL.

  • Page 152: Figure 11-54 Formats And States In The Slave Receiver Mode

    IDLE S or Sr SLA+W GCALL 0x95 0x1D LOST& 0x15 DATA 0x20 STOP 0x44 0x45 IDLE From master to slave / Interrupt, SCL line is held low Master command or Data Write From slave to master Interrupt after stop command Arbitration lost as master and 0xxx LOST&...
  • Page 153 11.10.10 I C Register description C Registers are composed of I C Mode Control Register (I2CMR), I C Status Register (I2CSR), SCL Low Period Register (I2CSCLLR), SCL High Period Register (I2CSCLHR), SDA Hold Time Register (I2CSDAHR), I C Data Register (I2CDR), and I C Slave Address Register (I2CSAR).
  • Page 154 I2CSR (I C Status Register) GCALL TEND STOP SSEL MLOST BUSY TMODE RXACK Initial value : 00 GCALL This bit has different meaning depending on whether I C is master or slave. Note 1) When I C is a master, this bit represents whether it received AACK (Address ACK) from slave.
  • Page 155 I2CSCLLR (SCL Low Period Register) SCLL7 SCLL6 SCLL5 SCLL4 SCLL3 SCLL2 SCLL1 SCLL0 Initial value : 3F SCLL[7:0] This register defines the LOW period of SCL when I C operates in master mode. The base clock is SCLK, the system clock, and the period is calculated by the formula : t ×...
  • Page 156 I2CSAR (I C Slave Address Register) SLA07 SLA06 SLA05 SLA04 SLA03 SLA02 SLA01 SLA00 Initial value : 00 SLA0[7:1] These bits configure the slave address of this I C module when I operates in slave mode. GCALLEN This bit decides whether I C allows general call address or not when I C operates in slave mode.

  • Page 157: Power Management

    12. POWER MANAGEMENT 12.1 Overview MC96FR364B supports two kinds of power saving modes, SLEEP and STOP. In these modes, the program execution is stopped. There’s also BOD mode caused by voltage drop, which is almost the same as STOP mode.

  • Page 158: Stop Mode

    CPU Clock External Interrupt Release Normal Operation SLEEP Mode Normal Operation Figure 12-1 Wake-up from SLEEP mode by an interrupt CPU Clock RESETB Release Set PCON to 01 BIT Counter 64 T Clear & Start TST = 65.5ms @ 8Mhz Normal Operation SLEEP Mode Normal Operation...

  • Page 159: Figure 12-3 Wake-Up From Stop Mode By An Interrupt

    �������� ÷ �������� Figure 12-4 STOP mode release by an external reset MC96FR364B acts in a little different manner after it awakes from STOP mode according to the external power condition after wake-up event. In stop mode, the main oscillator is halted and any internal peripheral does not operate normally. So only an interrupt from external world can wake the device up from STOP mode.

  • Page 160: Bod Mode

    higher than the BOD stop level(=V ), the device wakes up normally to resume program BODOUT0 execution. Otherwise if the checked voltage level is below the V , it remains in STOP mode. BODOUT0 This continues unless the power level is recovered. Thereafter the device wakes up by another interrupt when the power level detected by BOD is sufficient.

  • Page 161: Register Map

    - BOD ON (BODEN=1) VDD Low? - Entry into BOD mode due to voltage drop - Main OSC. stops BOD mode - VDC enters STOP mode - BOD is enabled - Commence BOD mode release sequence on wake-up VDD rise ? event (VDD rise) - Wakes up successfully when voltage is higher than Wait Until VDC is Stable...

  • Page 162: Reset

    13. RESET 13.1 Overview When a reset event occurs, the CPU immediately stops whatever it is doing and all internal logics except for BODR register is initialized. The external reset pin(P20) shares normal I/O pin and the functionality is defined by fuse configuration(FUSE_CONF register). The hardware configuration right after reset event is as follows.

  • Page 163: Noise Canceller For External Reset Pin

    NOTE Unlike other reset sources, BOD reset does not take place as soon as BODOUT0 goes HIGH(=voltage drops below BOD stop level). On detecting low voltage while the device is in normal run mode, the device enters BOD(STOP) mode first. And then by detecting voltage rise, the power control logic wakes the device up to give a reset signal.

  • Page 164: Figure 13-4 Reset Release Timing When Power Is Supplied (Vdd Rises Slowly)

    Slow VDD Rise Time, max 0.02v/ms =1.4V (Typ) nPOR BIT Overflows (Internal Signal) BIT Starts Internal RESETb Oscillation Figure 13-4 Reset Release Timing when Power is supplied (VDD Rises Slowly) Counting for config read start after POR is released Internal nPOR PAD RESETB (P20) “H”...

  • Page 165: Figure 13-6 Operation According To Power Level

    :VDD Input : OSC (XIN) ⑥ ④ Reset Release Config Read ② ⑦ ⑤ ① ③ Figure 13-6 Operation according to Power Level The above figure shows internal operation according to the voltage level and time. And the following table is short description about the figure. Process Description Remarks...

  • Page 166: External Resetb Input

    13.6 External RESETB Input External reset pin is a Schmitt Trigger type input. External reset input should be asserted low at least for 8us(typically) for normal reset function when operating voltage and output of main oscillator are stable. When the external reset input goes high, the internal reset is released after 64ms of stability time in case external clock frequency is 8MHz.

  • Page 167: Brown Out Detector

    13.7 Brown Out Detector The MC96FR364B includes a system to protect against low voltage conditions in order to preserve memory contents and control MCU system states during supply voltage variations. The system is comprised of a power-on-reset(nPOR) and an BOD with 4 voltage level indicators. The BOD is enabled when BODEN in BODR is high.

  • Page 168: Register Map

    “H” “H” Internal nPOR “H” PAD RESETB (R20) BOD_RESETB .. F1 F2 BIT (for Config) 00 01 02 BIT (for Reset) FE FF 00 01 02 03 01 02 250us X F2 = about 60ms Config Read 250us X FF = about 64ms RESET_SYSB Main OSC Off...
  • Page 169 No external reset detected after clear External reset occurred WDTRF NOTE Watchdog reset event No WDT reset detected after clear WDT reset occurred OCDRF NOTE On-chip debugger reset event No OCD reset detected after clear OCD reset occurred NOTE BODRF Brown-out detector reset event No BOD reset detected after clear BOD reset occurred...
  • Page 170 CFGCR (Configuration Control Register) SWRM STUE Initial value : 10 SWRM The monitor of Software reset Software reset was not asserted. Sofware reset was asserted. STUE Configuration register update is enabled at stop mode. Hardware will not update configuration register at stop mode. Hardware will update configuration register at stop mode.

  • Page 171: On-Chip Debug System

    14. On-chip Debug System 14.1 Overview 14.1.1 Description The On-chip debug system(OCD) of MC96FR364B is used to program/erase the non-volatile memory or debug the device. The main features are shown as follows. 14.1.2 Features • Two-wire external interface : 1-wire serial clock input, 1-wire bi-directional serial data bus •...

  • Page 172: Two-Pin External Interface

    Target MCU internal circuit Format converter DSCL Control DSDA DBG Register Address bus Internal data bus User I/O Data memory Code memory Peripherals - EEPROM - FLASH - SRAM Figure 14-1 Block Diagram of On-Chip Debug System 14.2 Two-pin external interface 14.2.1 Basic transmission packet ...

  • Page 173: Figure 14-2 10-Bit Transmission Packets

    Figure 14-2 10-bit transmission packets 14.2.2 Packet transmission timing 14.2.2.1 Data transfer Figure 14-3 Data transfer on the twin bus November, 2018 Rev.1.4...

  • Page 174: Figure 14-4 Bit Transfer On The Serial Bus

    14.2.2.2 Bit transfer DSDA DSCL data line change stable: of data data valid allowed except Start and Stop Figure 14-4 Bit transfer on the serial bus 14.2.2.3 Start and stop condition DSDA DSDA DSCL DSCL START condition STOP condition Figure 14-5 Start and stop condition 14.2.2.4 Acknowledge bit Data output by transmitter...

  • Page 175: Figure 14-7 Clock Synchronization During Wait Procedure

    Acknowledge bit Acknowledge bit transmission transmission Minimum 500ns wait HIGH start HIGH Host PC DSCL OUT Start wait Target Device DSCL OUT minimum 1 T SCLK for next byte Maximum 5 T SCLK transmission DSCL Internal Operation Figure 14-7 Clock synchronization during wait procedure 14.2.3 Connection of transmission Two-pin interface connection uses open-drain (wired-AND bidirectional I/O).

  • Page 176: Flash Memory Controller

    15.1 Overview 15.1.1 Description The MC96FR364B has 64KB of embedded FLASH memory. On reset, this non-volatile memory is used as code memory. In user application program, parts of this non-volatile memory can be updated. Program and erase is performed by ISP via OCD or parallel ROM writer in byte size.

  • Page 177: Register Map

    Boot Area Size FFFF BSIZE[1:0] = 00  512B (0000 ~ 01FF = 01 1024B (0000 ~ 03FF = 10 2048B (0000 ~ 07FF 32KB = 11 4096B (0000 ~ 0FFF 1FFF 7FFF Bank0 (64Kbytes) 16KB 0FFF 3FFF 07FF 03FF 512B 01FF 1FFF...

  • Page 178: Register Description

    15.4 Register Description 15.4.1 FLASH Control Registers Description FMR (FLASH Mode Register) PBUFF FSEL ESEL OTPE READ nFERST Initial value : 01 FLASH Bulk Erase Enable. FLASH Bulk Erase Disabled FLASH Bulk Erase Enabled PBUFF Select Flash Page Buffer. Main cell selected. Page buffer selected.
  • Page 179 FADDR15 FADDR14 FADDR13 FADDR12 FADDR11 FADDR10 FADDR9 FADDR8 Initial value : 00 FADDR[15:8] Flash Address Middle (Write) Checksum result in auto verify mode (Read, PCRCRD=0) CRC result in auto verify mode (Read, PCRCRD=1) FARL (FLASH Address Register Low) FADDR7 FADDR6 FADDR5 FADDR4 FADDR3...
  • Page 180 going, active low. This bit is auto-set when operation is done. Busy (Operation processing) Operation completed VFYGOOD Auto-verification result flag Auto-verification failed Auto-verification succeeded PCRCRD CRC calculation data read control. For correct operation, clear the FARH, FARM and FARL before starting CRC or setting READ bit in FEMR.
  • Page 181 The CSUMH, CSUMM and CSUML registers are test purpose only. CSUMH (FLASH Read Check Sum Register High) 2F06 CSUM23 CSUM22 CSUM21 CSUM20 CSUM19 CSUM18 CSUM17 CSUM16 Initial value : 00 CSUM[23:16] FLASH Read Checksum in auto-verify mode CSUMM (FLASH Read Check Sum Register Middle) 2F07 CSUM15 CSUM14...
  • Page 182 FSLTA1 (FLASH Secure Lock Top Address 1 Register) 2F64 FSLTA15 FSLTA14 FSLTA13 FSLTA12 FSLTA11 FSLTA10 FSLTA9 FSLTA8 Initial value : 00 FSLTA[15:8] Flash Secure Lock Top Address FSLTA0 (FLASH Secure Lock Top Address 0 Register) 2F65 FSLTA7 FSLTA6 FSLTA5 FSLTA4 FSLTA3 FSLTA2 FSLTA1...
  • Page 183 FSUTA[7:0] Flash Secure Unlock Top Address FSCTRL (FLASH Secure Control Register) 2F6C UCTRL LCTRL Initial value : 00 UCTRL FLASH unlock control FLASH unlock control is disabled FLASH unlock control is enabled LCTRL FLASH lock control FLASH lock control is disabled FLASH lock control is enabled FSLBAx, FSLTAx, FSUBAx, FSUTAx and FSCTRL registers are used for code write protedction.

  • Page 184: Memory Map

    15.5 Memory map As described previously, MC96FR364B has 64KB of Program Memory called FLASH. It is needed to write page address into FARH, FARM and FARL registers to program or erase the non-volatile memory. 15.5.1 FLASH area division FFFF pgm/ers/vfy...

  • Page 185: Serial In-System Program Mode

    14. 15.6.1 ISP or Self Programming Sequence In MC96FR364B, the commands needed to update FLASH is commenced by FECR register only. PROGRAM or ERASE sequence is as follows : 1. Set Erase or Program time : FETCR(EE...
  • Page 186 F000 is erased and programmed. Example: ////////////////////////////////////////////////////////// // Project : Write data to EEPROM at 0xF000 // Device : MC96FR364B // Oscillator : 4MHz // Compiler : Keil uvision C Compiler V7.20 ///////////////////////////////////////////////////////// #include <intrins.h> #include "MC96FR364B.h"...
  • Page 187 // PGM or ERASE Timing, normally the same values are set. #define PGMTIME 0x4F // 2.5ms @4MHz #define ERSTIME 0x4F // 2.5ms @4MHz void page_buffer_reset(); void flash_page_write(unsigned int addr, unsigned char *wdata); void flash_page_erase(unsigned int addr); void flash_program_enter(); void flash_program_exit(); xdata unsigned char pagerom[FLASH_PBUFF_SIZE] _at_ 0x8000;...
  • Page 188 for (i=0; I < FLASH_PBUFF_SIZE; i++) { pagerom[i] = 0x00; // Step 5 FARL = (unsigned char) addr; FARM = (unsigned char) (addr>>8); // Step 8 FECR = 0x0B; // Step 9 : It is optional because the CPU clock halts while in program or erase operation. while(FESR>>7 == 0x00);...

  • Page 189: Security

    Load data to page buffer. Table 15-3 FLASH operating mode 15.7 Security The MC96FR364B provides one LOCKF bit to protect memory contents from illegal attempt to read. The LOCKF bit can be erased only by bulk erase operation. USER MODE...

  • Page 190: Flash Memory Operating Mode

    15.8 FLASH Memory operating mode 15.8.1.1 Electrical Characteristics FLASH 64KB IP Spec Description Symbol Condition Unit Operating Temperature Temp Commercial ℃ Supply Voltage 1.62 1.98 Ground Clock Frequency fCLK VDD=1.8V Clock Period tPER VDD=1.8V Access Time VDD=1.8V Setup Time VDD=1.8V Address Hold Time VDD=1.8V Address Setup Time...

  • Page 191: Etc

    16. Etc.. 16.1 FUSE Control Register FUSE_CONF (Pseudo-Configure Data) 2F5D BSIZE1 BSIZE0 RSTDIS LOCKB LOCKF Initial value : 00 BSIZE[1:0] Selects the size of Boot Area 512B 1024B 2048B 4096B RSTDIS Enables or disables external reset function P20/RESETB is used as a external reset input P20/RESETB is used as a normal I/O pin LOCKB Lock Boot Area...

  • Page 192: Appendix

    17. APPENDIX A. Instruction Table The instruction length of M8051W can be 1, 2, or 3 bytes as listed in the following table. It takes 1, 2, or 4 cycles for the CPU to execute an instruction. The cycle is composed of two internal clock periods. ARITHMETIC Mnemonic Description...
  • Page 193 XRL A, @Ri Exclusive-OR indirect memory to A 66-67 XRL A,#data Exclusive-OR immediate to A XRL dir,A Exclusive-OR A to direct byte XRL dir,#data Exclusive-OR immediate to direct byte CLR A Clear A CPL A Complement A SWAP A Swap Nibbles of A RL A Rotate A left RLC A...
  • Page 194 ANL C,bit AND direct bit to carry ANL C,/bit AND direct bit inverse to carry ORL C,bit OR direct bit to carry ORL C,/bit OR direct bit inverse to carry MOV C,bit Move direct bit to carry MOV bit,C Move carry to direct bit BRANCHING Mnemonic Description...

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