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Abov MC97F2664 User Manual

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MC97F2664
ABOV SEMICONDUCTOR Co., Ltd.
8-BIT MICROCONTROLLERS
MC97F2664
User's Manual (Ver. 1.4)
April 11, 2014 Ver. 1.4
1

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Summary of Contents for Abov MC97F2664

  • Page 1 MC97F2664 ABOV SEMICONDUCTOR Co., Ltd. 8-BIT MICROCONTROLLERS MC97F2664 User’s Manual (Ver. 1.4) April 11, 2014 Ver. 1.4...
  • Page 2 Additional information of this manual may be served by ABOV Semiconductor offices in Korea or Distributors. ABOV Semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, ABOV Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.

  • Page 3: Table Of Contents

    MC97F2664 Table of Contents 1. Overview ................................10 1.1 Description ..............................10 1.2 Features ..............................11 1.3 Ordering Information ..........................12 1.4 Development Tools ............................ 13 2. Block Diagram ..............................15 3. Pin Assignment ..............................16 4. Package Diagram .............................. 20 5.
  • Page 4 MC97F2664 9.9 P6 Port ............................... 88 9.10 P7 Port ..............................90 10. Interrupt Controller ............................92 10.1 Overview ..............................92 10.2 External Interrupt ............................93 10.3 Block Diagram ............................94 10.4 Interrupt Vector Table ..........................95 10.5 Interrupt Sequence ........................... 96 10.6 Effective Timing after Controlling Interrupt Bit ..................
  • Page 5 MC97F2664 List of Figures Figure 1.1 OCD2 Debugger and Pin Description ..................13 Figure 1.2 PGMplusUSB (Single Writer) ....................14 Figure 1.3 StandAlone PGMplus (Single Writer) ..................14 Figure 1.4 StandAlone Gang8 (for Mass Production) ................14 Figure 2.1 Block Diagram ........................15 Figure 3.1 MC97F2664L 64LQFP-1010 Pin Assignment ................
  • Page 6 MC97F2664 Figure 10.5 Effective Timing of Interrupt Flag Register ................97 Figure 10.6 Effective Timing of Interrupt ....................98 Figure 10.7 Interrupt Response Timing Diagram ..................99 Figure 10.8 Correspondence between Vector Table Address and the Entry Address of ISP ....99 Figure 10.9 Saving/Restore Process Diagram and Sample Source ............
  • Page 7 MC97F2664 Figure 11.44 Asynchronous Start Bit Sampling (USIn, where n = 0 and 1) .......... 188 Figure 11.45 Asynchronous Sampling of Data and Parity Bit (USIn, where n = 0 and 1) ..... 188 Figure 11.46 Stop Bit Sampling and Next Start Bit Sampling (USIn, where n = 0 and 1) ..... 189 Figure 11.47 USI0/1 SPI Clock Formats when CPHAn=0 (where n = 0 and 1) ........
  • Page 8 MC97F2664 List of Tables Table 1-1 Ordering Information of MC97F2664 ..................12 Table 5-1 Normal Pin Description ......................24 Table 7-1 Absolute Maximum Ratings ....................31 Table 7-2 Recommended Operating Conditions ..................31 Table 7-3 A/D Converter Characteristics ....................32 Table 7-4 Power-on Reset Characteristics .....................
  • Page 9 MC97F2664 Table 11-18 CPOLn Functionality (where n = 0 and 1) ................. 190 Table 11-19 USI0/1 Register Map (where n = 0 and 1) ................ 207 Table 11-20 Examples of USI0BD and USI1BD Settings for Commonly Used Oscillator Frequencies 216 Table 11-21 ADC Register Map ......................

  • Page 10: Overview

    1. Overview 1.1 Description The MC97F2664 is advanced CMOS 8-bit microcontroller with 64k bytes of FLASH. This is powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. This provides the following features : 64k bytes of FLASH, 256 bytes of IRAM, 4,096 bytes of XRAM , general...

  • Page 11: Features

    MC97F2664 1.2 Features • CPU • Low Voltage Indicator - 8 Bit CISC Core (8051 Compatible) - 13 level detect (2.00V/ 2.10V/ 2.20V/ 2.32V/ 2.44V/ 2.59V/ 2.75V/ 2.93V/ 3.14V/ 3.38V/ • ROM (FLASH) Capacity 3.67V/ 4.00V/ 4.40V) - 64k Bytes •...

  • Page 12: Ordering Information

    MC97F2664 1.3 Ordering Information Table 1-1 Ordering Information of MC97F2664 Device name ROM size IRAM size XRAM size Package MC97F2664L 64 LQFP-1010 MC97F2664L14 64 LQFP-1414 64k bytes FLASH 256 bytes 4,096 bytes MC97F2664UB 64 QFN MC97F2464Q 44 MQFP-1010 April 11, 2014 Ver. 1.4...

  • Page 13: Development Tools

    1.4.1 Compiler We do not provide the compiler. Please contact the third parties. The core of MC97F2664 is Mentor 8051. And, device ROM size is smaller than 64k bytes. Developer can use all kinds of third party’s standard 8051 compiler.

  • Page 14: Figure 1.2 Pgmplususb (Single Writer)

    MC97F2664 1.4.3 Programmer Single programmer: PGMplus USB: It programs MCU device directly. Figure 1.2 PGMplusUSB (Single Writer) StandAlone PGMplus: It programs MCU device directly. Figure 1.3 StandAlone PGMplus (Single Writer) OCD emulator: It can write code in MCU device too, because OCD debugging supports ISP (In System Programming).

  • Page 15: Block Diagram

    MC97F2664 2. Block Diagram DSDA DSCL RUNFLAG AN0-AN7/P10-P17 Low Voltage AN8-AN14/P01-P07 12-Bit A/D Converter Indicator AVREF/P00 On-Chip Debug T0O/PWM0O/P50 Buzzer BUZO/P33 EINT10/P50 8-Bit Timer 0 EC0/P54 MOSI3/P70 MISO3/P71 T1O/PWM1O/P51 SPI3 SCK3/P72 EINT11/P51 8-Bit Timer 1 SS3/P73 EC1/P55 M8051 Core MOSI2/P34...

  • Page 16: Pin Assignment

    MC97F2664 3. Pin Assignment P56/EC2 P03/AN10 P55/EC1 P02/AN9 P54/EC0 P01/AN8 P53/EINT13/T3O/PWM3O P00/AVREF P52/EINT12/T2O/PWM2O P17/EINT7/AN7 P51/EINT11/T1O/PWM1O P16/EINT6/AN6 P50/EINT10/T0O/PWM0O P15/EINT5/AN5 MC97F2664L P47/RXD3 P14/EINT4/AN4 P46/TXD3 (64-LQFP-1010) P13/EINT3/AN3 P45/RXD2 P12/EINT2/AN2 P44/TXD2 P11/EINT1/AN1 P43/SS1 P10/EINT0/AN0 P42/SCK1 P27/EINTA P41/RXD1/SCL1/MISO1 P26/EINT9 P40/TXD1/SDA1/MOSI1 P25/EINT8 P70/MOSI3 P24/RXD4 Figure 3.1 MC97F2664L 64LQFP-1010 Pin Assignment NOTES) 1.

  • Page 17: Figure 3.2 Mc97F2664L14 64Lqfp-1414 Pin Assignment

    MC97F2664 P56/EC2 P03/AN10 P55/EC1 P02/AN9 P54/EC0 P01/AN8 P53/EINT13/T3O/PWM3O P00/AVREF P52/EINT12/T2O/PWM2O P17/EINT7/AN7 P51/EINT11/T1O/PWM1O P16/EINT6/AN6 P50/EINT10/T0O/PWM0O P15/EINT5/AN5 MC97F2664L14 P47/RXD3 P14/EINT4/AN4 P46/TXD3 (64-LQFP-1414) P13/EINT3/AN3 P45/RXD2 P12/EINT2/AN2 P44/TXD2 P11/EINT1/AN1 P43/SS1 P10/EINT0/AN0 P42/SCK1 P27/EINTA P41/RXD1/SCL1/MISO1 P26/EINT9 P40/TXD1/SDA1/MOSI1 P25/EINT8 P70/MOSI3 P24/RXD4 Figure 3.2 MC97F2664L14 64LQFP-1414 Pin Assignment NOTES) 1.

  • Page 18: Figure 3.1 Mc97F2664Ub 64Qfn Pin Assignment

    MC97F2664 P56/EC2 P03/AN10 P55/EC1 P02/AN9 P54/EC0 P01/AN8 P53/EINT13/T3O/PWM3O P00/AVREF P52/EINT12/T2O/PWM2O P17/EINT7/AN7 P51/EINT11/T1O/PWM1O P16/EINT6/AN6 P50/EINT10/T0O/PWM0O P15/EINT5/AN5 MC97F2664 P47/RXD3 P14/EINT4/AN4 P46/TXD3 (64-QFN) P13/EINT3/AN3 P45/RXD2 P12/EINT2/AN2 P44/TXD2 P11/EINT1/AN1 P43/SS1 P10/EINT0/AN0 P42/SCK1 P27/EINTA P41/RXD1/SCL1/MISO1 P26/EINT9 P40/TXD1/SDA1/MOSI1 P25/EINT8 P70/MOSI3 P24/RXD4 Figure 3.3 MC97F2664UB 64QFN Pin Assignment NOTES) 1.

  • Page 19: Figure 3.3 Mc97F2464 44Mqfp-1010 Pin Assignment

    MC97F2664 P57/EC3/RESETB P02/AN9 P51/EINT11/T1O/PWM1O P01/AN8 P50/EINT10/T0O/PWM0O P00/AVREF P47/RXD3 P17/EINT7/AN7 MC97F2464Q P46/TXD3 P16/EINT6/AN6 P45/RXD2 P15/EINT5/AN5 (44-MQFP-1010) P44/TXD2 P14/EINT4/AN4 P43/SS1 P13/EINT3/AN3 P42/SCK1 P12/EINT2/AN2 P41/RXD1/SCL1/MISO1 P11/EINT1/AN1 P40/TXD1/SDA1/MOSI1 P10/EINT0/AN0 Figure 3.4 MC97F2464 44MQFP-1010 Pin Assignment NOTES) 1. On On-Chip Debugging, ISP uses P6[3:2] pin as DSDA, DSCL.

  • Page 20: Package Diagram

    MC97F2664 4. Package Diagram Figure 4.1 64-Pin LQFP-1010 Package April 11, 2014 Ver. 1.4...

  • Page 21: Figure 4.2 64-Pin Lqfp-1414 Package

    MC97F2664 Figure 4.2 64-Pin LQFP-1414 Package April 11, 2014 Ver. 1.4...

  • Page 22: Figure 4.3 64-Pin Qfn Package

    MC97F2664 Figure 4.3 64-Pin QFN Package April 11, 2014 Ver. 1.4...

  • Page 23: Figure 4.4 44-Pin Mqfp-1010 Package

    MC97F2664 Figure 4.4 44-Pin MQFP-1010 Package April 11, 2014 Ver. 1.4...

  • Page 24: Pin Description

    MC97F2664 5. Pin Description Table 5-1 Normal Pin Description Function @RESET Shared with Name Port 0 is a bit-programmable I/O port which can Input AVERF be configured as an input, a push-pull output, or an open-drain output. A pull-up resistor can be specified in 1-bit unit.
  • Page 25 MC97F2664 Table 5-1 Normal Pin Description (Continued) Function @RESET Shared with Name EINT10/T0O/PWM0O Port 5 is a bit-programmable I/O port which Input can be configured as a schmitt-trigger input, EINT11/T1O/PWM1O a push-pull output, or an open-drain output. EINT12/T2O/PWM2O A pull-up resistor can be specified in 1-bit unit.
  • Page 26 MC97F2664 Table 5-1 Normal Pin Description (Continued) Function @RESET Shared with Name P53/T3O/PWM3O EINT13 External interrupt and Timer 3 capture input Input P30/T4O/PWM4O EINT14 External interrupt and Timer 4 capture input Input P31/T5O/PWM5O EINT15 External interrupt and Timer 5 capture input...
  • Page 27 MC97F2664 Table 5-1 Normal Pin Description (Continued) Function @RESET Shared with Name SCK3 Serial 3 clock input/output Input P72/EC4 MOSI0 SPI 0 master output, slave input Input P63/TXD0/SDA0/DSDA MOSI1 SPI 1 master output, slave input Input P40/TXD1/SDA1 MOSI2 SPI 2 master output, slave input...
  • Page 28 MC97F2664 Table 5-1 Normal Pin Description (Continued) PIN Name Function @RESET Shared with A/D converter analog input channels Input RESETB System reset pin with a pull-up resistor when it Input P57/EC3 is selected as the RESETB by CONFIGURE OPTION (NOTE3)

  • Page 29: Port Structures

    MC97F2664 6. Port Structures 6.1 General Purpose I/O Port Level Shift (1.8V to ExtVDD) Level Shift (ExtVDD to 1.8V) PULL-UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE SUB-FUNC DIRECTION DIRECTION REGISTER CMOS or Schmitt Level Input...

  • Page 30: External Interrupt I/O Port

    MC97F2664 6.2 External Interrupt I/O Port Level Shift (1.8V to ExtVDD) Level Shift (ExtVDD to 1.8V) PULL-UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE SUB-FUNC DIRECTION DIRECTION REGISTER EXTERNAL INTERRUPT POLARITY REG. INTERRUPT ENABLE FLAG CMOS or...

  • Page 31: Electrical Characteristics

    MC97F2664 7. Electrical Characteristics 7.1 Absolute Maximum Ratings Table 7-1 Absolute Maximum Ratings Parameter Symbol Rating Unit Note – Supply Voltage -0.3 ~ +6.5 -0.3 ~ VDD+0.3 Voltage on any pin with respect to VSS -0.3 ~ VDD+0.3 Maximum current output sourced by (I...

  • Page 32: A/D Converter Characteristics

    MC97F2664 7.3 A/D Converter Characteristics Table 7-3 A/D Converter Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V) Parameter Symbol Conditions Unit – – –- – Resolution – – Integral Linear Error ±6 Differential Linearity – – ±1 AVREF= 2.7V –...

  • Page 33: Power-On Reset Characteristics

    MC97F2664 7.4 Power-On Reset Characteristics Table 7-4 Power-on Reset Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V) Parameter Symbol Conditions Unit – – – RESET Release Level – – VDD Voltage Rising Time 0.05 V/ms – –...

  • Page 34: Internal Rc Oscillator Characteristics

    MC97F2664 7.6 Internal RC Oscillator Characteristics Table 7-6 High Internal RC Oscillator Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V) Parameter Symbol Conditions Unit = 2.0 – 5.5 V – – Frequency = 0°C to +50 °C ±1.5...

  • Page 35: Dc Characteristics

    MC97F2664 7.8 DC Characteristics Table 7-8 DC Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V, f = 16MHz) Parameter Symbol Conditions Unit – P1, P2, P3, P5, P6, RESETB 0.8VDD Input High Voltage – All input pins except VIH1 0.7VDD...
  • Page 36 MC97F2664 Table 7-9 DC Characteristics (Continued) = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V, f = 16MHz) Parameter Symbol Condition Unit – = 16MHz, VDD= 5V±10% – = 12MHz, VDD= 3V±10% (RUN) – = 16MHz, VDD= 5V±10% –...

  • Page 37: Ac Characteristics

    MC97F2664 7.9 AC Characteristics Table 7-9 AC Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) Parameter Symbol Conditions Unit – – μs RESETB input low width Input, VDD= 5V – – Interrupt input high, low width All interrupt, VDD= 5V...

  • Page 38: Spi Characteristics

    MC97F2664 7.10 SPI Characteristics Table 7-10 SPI Characteristics = -40°C – +85°C, VDD= 1.8V – 5.5V) Parameter Symbol Conditions Unit – – Output Clock Pulse Period Internal SCK source – – Input Clock Pulse Period External SCK source Output Clock High, Low –...

  • Page 39: Uart Characteristics

    MC97F2664 7.11 UART Characteristics Table 7-11 UART Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, f =11.1MHz) Parameter Symbol Unit Serial port clock cycle time 1250 x 16 1650 – Output data setup to clock rising edge x 13 –...

  • Page 40: I2C Characteristics

    MC97F2664 7.12 I2C Characteristics Table 7-12 I2C Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) Standard Mode High-Speed Mode Parameter Symbol Unit Clock frequency – – Clock High Pulse Width SCLH – – Clock Low Pulse Width SCLL –...

  • Page 41: Data Retention Voltage In Stop Mode

    MC97F2664 7.13 Data Retention Voltage in Stop Mode Table 7-13 Data Retention Voltage in Stop Mode = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) Parameter Symbol Conditions Unit – – Data retention supply voltage DDDR – – μA Data retention supply current VDDR= 1.8V,...

  • Page 42: Internal Flash Rom Characteristics

    MC97F2664 7.14 Internal Flash Rom Characteristics Table 7-14 Internal Flash Rom Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V) Parameter Symbol Condition Unit – – Sector Write Time – – Sector Erase Time – – Hard-Lock Time –...

  • Page 43: Main Clock Oscillator Characteristics

    MC97F2664 7.16 Main Clock Oscillator Characteristics Table 7-16 Main Clock Oscillator Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) Oscillator Parameter Condition Unit 1.8V – 5.5V – Crystal Main oscillation frequency 2.7V – 5.5V – 12.0 3.0V – 5.5V –...

  • Page 44: Sub Clock Oscillator Characteristics

    MC97F2664 7.17 Sub Clock Oscillator Characteristics Table 7-17 Sub Clock Oscillator Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) Oscillator Parameter Condition Unit Crystal Sub oscillation frequency 32.768 1.8V – 5.5V – External Clock SXIN input frequency SXIN SXOUT Figure 7.12 Crystal Oscillator...

  • Page 45: Main Oscillation Stabilization Characteristics

    MC97F2664 7.18 Main Oscillation Stabilization Characteristics Table 7-18 Main Oscillation Stabilization Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) Oscillator Parameter Unit fx > 1MHz – – Crystal Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage –...

  • Page 46: Operating Voltage Range

    MC97F2664 7.20 Operating Voltage Range =0.4 to 16MHz) =32 to 38KHz) 16.0MHz 32.768KHz 12.0MHz 4.2MHz 0.4MHz Supply voltage (V) Supply voltage (V) Figure 7.16 Operating Voltage Range April 11, 2014 Ver. 1.4...

  • Page 47: Recommended Circuit And Layout

    MC97F2664 7.21 Recommended Circuit and Layout This 0.1uF capacitor should be within 1cm from the VDD pin of MCU on the VDD VCC PCB layout. DC Power 0.1uF 0.1uF The MCU power line (VDD and VSS) should be separated from the high-...

  • Page 48: Recommended Circuit And Layout With Smps Power

    MC97F2664 7.22 Recommended Circuit and Layout with SMPS Power SMPS Side MCU Side SMPS MC97F2664 1. The C1 capacitor is to flatten out the voltage of the SMPS power, VCC. √ Recommended C1: 470uF/25V more. 2. The R1 and C2 are the RC filter for VDD and suppress the ripple of VCC.

  • Page 49: Typical Characteristics

    MC97F2664 7.23 Typical Characteristics These graphs and tables provided in this section are only for design guidance and are not tested or guaranteed. In graphs or tables some data are out of specified operating range (e.g. out of specified VDD range). This is only for information and devices are guaranteed to operate properly only within the specified range.

  • Page 50: Figure 7.21 Sub Run (Idd3) Current

    MC97F2664 120.0 100.0 80.0 -40℃ 60.0 +25℃ +85℃ 40.0 20.0 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V Figure 7.21 SUB RUN (IDD3) Current 35.0 30.0 25.0 -40℃ 20.0 +25℃ 15.0 +85℃ 10.0 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V Figure 7.22 SUB IDLE (IDD4) Current...

  • Page 51: Figure 7.23 Stop (Idd5) Current

    MC97F2664 5.00 4.00 3.00 -40℃ +25℃ 2.00 +85℃ 1.00 0.00 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V Figure 7.23 STOP (IDD5) Current April 11, 2014 Ver. 1.4...

  • Page 52: Memory

    DPTR register. MC97F2664 provides on-chip 64k bytes of the ISP type flash program memory, which can be read and written to. Internal data memory (IRAM) is 256 bytes and it includes the stack area. External data memory (XRAM) is 4,096 bytes and it can be used as the extended stack area 8.1 Program Memory...

  • Page 53: Figure 8.1 Program Memory

    MC97F2664 FFFFH 64K Bytes 0000H Figure 8.1 Program Memory 64k Bytes Including Interrupt Vector Region April 11, 2014 Ver. 1.4...

  • Page 54: Data Memory

    MC97F2664 8.2 Data Memory Figure 8-2 shows the internal data memory space available. Upper 128 Bytes Special Function Registers Internal RAM 128 Bytes (Indirect Addressing) (Direct Addressing) Lower 128 Bytes Internal RAM (Direct or Indirect Addressing) Figure 8.2 Data Memory Map The internal data memory space is divided into three blocks, which are generally referred to as the lower 128 bytes, upper 128 bytes, and SFR space.

  • Page 55: Figure 8.3 Lower 128 Bytes Ram

    MC97F2664 7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70 6F 6E 6D 6C 6B 6A 69 68 67 66 65 64 63 62 61 60 5F 5E 5D 5C 5B 5A 59 58...

  • Page 56: Xram Memory

    MC97F2664 8.3 XRAM Memory MC97F2664 has 4,096 bytes XRAM. This area has no relation with RAM/FLASH. It can be read and written to through SFR with 8-bit unit. 107FH Extended Special Function Registers 128 Bytes (Indirect Addressing) 1000H 0FFFH External RAM...

  • Page 57: Sfr Map

    MC97F2664 8.4 SFR Map 8.4.1 SFR Map Summary Table 8-1 SFR Map Summary – Reserved M8051 compatible 00H/8H 01H/9H 02H/0AH 03H/0BH 04H/0CH 05H/0DH 06H/0EH 07H/0FH 0F8H XBANK FSADRH FSADRM FSADRL FIDR FMCR MODINR 0F0H P35DB BUZCR BUZDR SPWRL SPWRH XSPCR...

  • Page 58: Table 8-2 Extended Sfr Map Summary

    MC97F2664 Table 8-2 Extended SFR Map Summary Reserved 00H/8H 01H/9H 02H/0AH 03H/0BH 04H/0CH 05H/0DH 06H/0EH 07H/0FH 1078H 1070H 1068H 1060H 1058H T9CRL T9CRH T9ADRL T9ADRH T9BDRL T9BDRH 1050H ADCCRL ADCCRH ADCDRL ADCDRH 1048H UART4CR1 UART4CR2 UART4CR3 UART4ST UART4BD UART4DR 1040H UART3CR1 UART3CR2 UART3CR3...

  • Page 59: Table 8-3 Sfr Map

    MC97F2664 8.4.2 SFR Map Table 8-3 SFR Map @Reset Address Function Symbol P0 Data Register Stack Pointer Data Pointer Register Low Data Pointer Register High Data Pointer Register Low 1 DPL1 Data Pointer Register High 1 DPH1 – – Low Voltage Indicator Control Register LVICR –...
  • Page 60 MC97F2664 Table 8-3 SFR Map (Continued) @Reset Address Function Symbol P4 Data Register P1 Direction Register P1IO – – – – Extended Operation Register External Interrupt Flag 0 Register EIFLAG0 External Interrupt Flag 1 Register EIFLAG1 – – – External Interrupt Flag 2 Register...
  • Page 61 MC97F2664 Table 8-3 SFR Map (Continued) @Reset Address Function Symbol – Timer 3 Control Register T3CR Timer 3 Counter Register T3CNT Timer 3 Data Register T3DR Timer 3 Capture Data Register T3CDR – – – P7 Data Register P4 Direction Register...
  • Page 62 MC97F2664 Table 8-3 SFR Map (Continued) @Reset Address Function Symbol Accumulator Register P1 Debounce Enable Register P1DB – – Timer 7 Control Low Register T7CRL – – – Timer 7 Control High Register T7CRH Timer 7 A Data Low Register...

  • Page 63: Table 8-4 Extended Sfr Map

    MC97F2664 Table 8-4 Extended SFR Map @Reset Address Function Symbol 1000H P0 Open-drain Selection Register P0OD 1001H P1 Open-drain Selection Register P1OD 1002H P2 Open-drain Selection Register P2OD 1003H P3 Open-drain Selection Register P3OD 1004H P4 Open-drain Selection Register P4OD...
  • Page 64 MC97F2664 Table 8-4 Extended SFR Map (Continued) @Reset Address Function Symbol 1020H USI0 Status Register 1 USI0ST1 1021H USI0 Status Register 2 USI0ST2 1022H USI0 Baud Rate Generation Register USI0BD 1023H USI0 SDA Hold Time Register USI0SDHR 1024H USI0 Data Register...
  • Page 65 MC97F2664 Table 8-4 Extended SFR Map (Continued) @Reset Address Function Symbol – – – 1040H UART3 Control Register 1 UART3CR1 1041H UART3 Control Register 2 UART3CR2 – – – – 1042H UART3 Control Register 3 UART3CR3 1043H UART3 Status Register...
  • Page 66 MC97F2664 8.4.3 Compiler Compatible SFR ACC (Accumulator Register) : E0H Initial value : 00H Accumulator B (B Register) : F0H Initial value : 00H B Register SP (Stack Pointer) : 81H Initial value : 07H Stack Pointer XSP (Extend Stack Pointer) : 91H...
  • Page 67 MC97F2664 DPL (Data Pointer Register Low) : 82H Initial value : 00H Data Pointer Low DPH (Data Pointer Register High) : 83H Initial value : 00H Data Pointer High DPL1 (Data Pointer Register Low 1) : 84H DPL1 Initial value : 00H...
  • Page 68 MC97F2664 EO (Extended Operation Register) : A2H – – – – TRAP_EN DPSEL2 DPSEL1 DPSEL0 – – – – Initial value : 00H Select the Instruction (Keep always ‘0’). TRAP_EN Select MOVC @(DPTR++), A Select Software TRAP Instruction DPSEL[2:0] Select Banked Data Pointer Register...
  • Page 69 MC97F2664 SINTCR(System Interrupt Control Register) : F7H – – – – – – SPOVIE SPOVIFR – – – – – – Initial value : 00H SPOVIE Enable or Disable Stack Pointer Overflow Interrupt Disable Enable When SPOVF Interrupt occurs, this bit becomes ‘1’. The flag is SPOVIFR cleared only by writing a ‘0’...

  • Page 70: I/O Ports

    9.1 I/O Ports The MC97F2664 has eight groups of I/O ports (P0 ~ P7). Each port can be easily configured by software as I/O pin, internal pull up and open-drain pin to meet various system configurations and design requirements. Also P1, P2, P3, and P5 include function that can generate interrupt according to change of state of the pin.

  • Page 71: Table 9-1 Port Register Map

    MC97F2664 9.2.7 Register Map Table 9-1 Port Register Map Name Address Default Description P0 Data Register P0IO P0 Direction Register P0OD 1000H (XSFR) P0 Open-drain Selection Register P0PU 1008H (XSFR) P0 Pull-up Resistor Selection Register P0FSR 1010H (XSFR) P0 Function Selection Register...
  • Page 72 MC97F2664 Table 9-1 Port Register Map (CONTINUED) Name Address Default Description P6 Data Register P6IO P6 Direction Register P6OD 1006H (XSFR) P6 Open-drain Selection Register P6PU 100EH (XSFR) P6 Pull-up Resistor Selection Register P6FSR 1016H (XSFR) P6 Function Selection Register...

  • Page 73: P0 Port

    MC97F2664 9.3 P0 Port 9.3.1 P0 Port Description P0 is 8-bit I/O port. P0 control registers consist of P0 data register (P0), P0 direction register (P0IO), P0 pull-up resistor selection register (P0PU), and P0 open-drain selection register (P0OD). Refer to the port function selection registers for the P0 function selection.
  • Page 74 MC97F2664 P0FSR (Port 0 Function Selection Register) : 1010H (XSFR) P0FSR7 P0FSR6 P0FSR5 P0FSR4 P0FSR3 P0FSR2 P0FSR1 P0FSR0 Initial value : 00H P0FSR7 P07 Function select I/O Port AN14 Function P0FSR6 P06 Function select I/O Port AN13 Function P0FSR5 P05 Function select...

  • Page 75: P1 Port

    MC97F2664 9.4 P1 Port 9.4.1 P1 Port Description P1 is 8-bit I/O port. P1 control registers consist of P1 data register (P1), P1 direction register (P1IO), debounce enable register (P1DB), P1 pull-up resistor selection register (P1PU), and P1 open-drain selection register (P1OD) .
  • Page 76 MC97F2664 P1DB (P1 Debounce Enable Register) : E1H P17DB P16DB P15DB P14DB P13DB P12DB P11DB P10DB Initial value : 00H P17DB Configure Debounce of P17 Port Disable Enable P16DB Configure Debounce of P16 Port Disable Enable P15DB Configure Debounce of P15 Port...
  • Page 77 MC97F2664 P1FSR (Port 1 Function Selection Register) : 1011H (XSFR) P1FSR7 P1FSR6 P1FSR5 P1FSR4 P1FSR3 P1FSR2 P1FSR1 P1FSR0 Initial value : 00H P1FSR7 P17 Function select I/O Port (EINT7 function possible when input) AN7 Function P1FSR6 P16 Function select I/O Port (EINT6 function possible when input)

  • Page 78: P2 Port

    MC97F2664 9.5 P2 Port 9.5.1 P2 Port Description P2 is 8-bit I/O port. P2 control registers consist of P2 data register (P2), P2 direction register (P2IO), debounce enable register (P2DB), P2 pull-up resistor selection register (P2PU) and P2 open-drain selection register (P2OD).
  • Page 79 MC97F2664 P2DB (P2 Debounce Enable Register) : E9H DBCLK1 DBCLK0 P27DB P26DB P25DB P22DB P21DB P20DB Initial value : 00H DBCLK[1:0] Configure Debounce Clock of Port DBCLK1 DBCLK0 description fx/1 fx/4 fx/4096 Reserved P27DB Configure Debounce of P27 Port Disable...
  • Page 80 MC97F2664 P2FSR (Port 2 Function Selection Register) : 1012H (XSFR) – – – – P2FSR3 P2FSR2 P2FSR1 P2FSR0 – – – – Initial value : 00H P2FSR3 P23 Function select I/O Port TXD4 Function P2FSR2 P22 Function select I/O Port (EINT19 function possible when input)

  • Page 81: P3 Port

    MC97F2664 9.6 P3 Port 9.6.1 P3 Port Description P3 is 8-bit I/O port. P3 control registers consist of P3 data register (P3), P3 direction register (P3IO), debounce enable register (P35DB),P3 pull-up resistor selection register (P3PU) and P3 open-drain selection register (P3OD).
  • Page 82 MC97F2664 P35DB (P35 Debounce Enable Register) : F1H – P53DB P52DB P51DB P50DB P32DB P31DB P30DB – Initial value : 00H P53DB Configure Debounce of P53 Port Disable Enable P52DB Configure Debounce of P52 Port Disable Enable P51DB Configure Debounce of P51 Port...
  • Page 83 MC97F2664 P3FSR (Port 3 Function Selection Register) : 1013H (XSFR) P3FSR7 P3FSR6 P3FSR5 P3FSR4 P3FSR3 P3FSR2 P3FSR1 P3FSR0 Initial value : 00H P3FSR7 P36 Function select I/O Port (EC8 function possible when input) SCK2 Function P3FSR6 P35 Function select I/O Port (EC7 function possible when input)

  • Page 84: P4 Port

    MC97F2664 9.7 P4 Port 9.7.1 P4 Port Description P4 is 8-bit I/O port. P4 control registers consist of P4 data register (P4), P4 direction register (P4IO), P4 pull-up resistor selection register (P4PU) and P4 open-drain selection register (P4OD). Refer to the port function selection registers for the P4 function selection.
  • Page 85 MC97F2664 P4FSR (Port 4 Function Selection Register) : 1014H (XSFR) – – – P4FSR4 P4FSR3 P4FSR2 P4FSR1 P4FSR0 – – – Initial value : 00H P4FSR4 P46 Function select I/O Port TXD3 Function P4FSR3 P44 Function Select I/O Port TXD2 Function...

  • Page 86: P5 Port

    MC97F2664 9.8 P5 Port 9.8.1 P5 Port Description P5 is 8-bit I/O port. P5 control registers consist of P5 data register (P5), P5 direction register (P5IO), P5 pull-up resistor selection register (P5PU) and P5 open-drain selection register (P5OD). Refer to the port function selection registers for the P5 function selection.
  • Page 87 MC97F2664 P5FSR (Port 5 Function Selection Register) : 1015H (XSFR) – – – – P5FSR3 P5FSR2 P5FSR1 P5FSR0 – – – – Initial value : 00H P5FSR3 P53 Function Select I/O Port (EINT13 function possible when input) T3O/PWM3O Function P5FSR2...

  • Page 88: P6 Port

    MC97F2664 9.9 P6 Port 9.9.1 P6 Port Description P6 is 8-bit I/O port. P6 control registers consist of P6 data register (P6), P6 direction register (P6IO), P6 pull-up resistor selection register (P6PU) and P6 open-drain selection register (P6OD). Refer to the port function selection registers for the P6 function selection.
  • Page 89 MC97F2664 P6FSR (Port 6 Function Selection Register) : 1016H (XSFR) – P6FSR6 P6FSR5 P6FSR4 P6FSR3 P6FSR2 P6FSR1 P6FSR0 – Initial value : 00H P6FSR6 P67 Function select I/O Port SXOUT Function P6FSR5 P66 Function select I/O Port SXIN Function P6FSR4...

  • Page 90: P7 Port

    MC97F2664 9.10 P7 Port 9.10.1 P7 Port Description P7 is 5-bit I/O port. P7 control registers consist of P7 data register (P7), P7 direction register (P7IO), P7 pull-up resistor selection register (P7PU) and P7 open-drain selection register (P7OD). Refer to the port function selection registers for the P7 function selection.
  • Page 91 MC97F2664 P7FSR (Port 7 Function Selection Register) : 1017H (XSFR) – – – – P7FSR3 P7FSR2 P7FSR1 P7FSR0 – – – – Initial value : 00H P7FSR3 P73 Function Select I/O Port EC6 Function P7FSR2 P72 Function select I/O Port (EC4 function possible when input)

  • Page 92: Interrupt Controller

    10. Interrupt Controller 10.1 Overview The MC97F2664 supports up to 24 interrupt sources. The interrupts have separate enable register bits associated with them, allowing software control. They can also have four levels of priority assigned to them. The non-maskable interrupt source is always enabled with a higher priority than any other interrupt source, and is not controllable by software.

  • Page 93: External Interrupt

    MC97F2664 10.2 External Interrupt The external interrupt on EINT0~A and EINT10~19 pins receive various interrupt request depending on the external interrupt polarity 0 high/low register (EIPOL0H/L), external interrupt polarity 1 high/low register (EIPOL1H/L), and external interrupt polarity 2 high/low register (EIPOL2H/L), as shown in Figure 10.1. Also each external interrupt source has enable/disable bits.

  • Page 94: Block Diagram

    MC97F2664 10.3 Block Diagram IP0L IP0H IP1L IP1H USI0 Rx IP2L IP2H IP3L IP3H USI1 Rx Priority High UART2 Rx UART3 Rx SPI2 EIPOL0H/L EIFLAG0.0 FLAG0 EINT0 EIFLAG0.1 FLAG1 EINT1 EIFLAG0.2 EINT2 FLAG2 EIFLAG0.3 FLAG3 EINT3 EIFLAG0.4 FLAG4 EINT4 EIFLAG0.5...

  • Page 95: Interrupt Vector Table

    MC97F2664 10.4 Interrupt Vector Table The interrupt controller supports 24 interrupt sources as shown in the Table 10-2. When interrupt is served, long call instruction (LCALL) is executed and program counter jumps to the vector address. All interrupt requests have their own priority order.

  • Page 96: Interrupt Sequence

    MC97F2664 10.5 Interrupt Sequence An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to ‘0’ by a reset or an instruction. Interrupt acceptance always generates at last cycle of the instruction. So instead of fetching the current instruction, CPU executes internally LCALL instruction and saves the PC at stack.

  • Page 97: Effective Timing After Controlling Interrupt Bit

    MC97F2664 10.6 Effective Timing after Controlling Interrupt Bit Case a) Control Interrupt Enable Register (IE, IE1, IE2, IE3) Interrupt Enable Register command After executing IE set/clear, enable register is effective. Next Instruction Next Instruction Figure 10.4 Effective Timing of Interrupt Enable Register...

  • Page 98: Multi Interrupt

    MC97F2664 10.7 Multi Interrupt If two requests of different priority levels are received simultaneously, the request of higher priority level is served first. If more than one interrupt request are received, the interrupt polling sequence determines which request is served first by hardware. However, for special features, multi-interrupt processing can be executed by software.

  • Page 99: Interrupt Enable Accept Timing

    MC97F2664 10.8 Interrupt Enable Accept Timing Max. 4 Machine Cycle 4 Machine Cycle System Clock Interrupt goes Active Interrupt Interrupt Processing Latched Interrupt Routine : LCALL & LJMP Figure 10.7 Interrupt Response Timing Diagram 10.9 Interrupt Service Routine Address Basic Interval Timer...

  • Page 100: Interrupt Timing

    MC97F2664 10.11 Interrupt Timing Interrupt sampled here CLP2 CLP1 CLP2 C1P1 C1P2 C2P1 C2P2 SCLK INT_SRC INTR_ACK LAST_CYC INTR_LCALL 8-Bit interrupt Vector INT_VEC {8’h00, INT_VEC} PROGA Figure 10.10 Timing Chart of Interrupt Acceptance and Interrupt Return Instruction Interrupt sources are sampled at the last cycle of a command. If an interrupt source is detected the lower 8-bit of interrupt vector (INT_VEC) is decided.
  • Page 101 MC97F2664 10.12.3 External Interrupt Flag Register (EIFLAG0, EIFLAG1, EIFLAG2) The external interrupt flag 0 register (EIFLAG0), external interrupt flag 1 register (EIFLAG1) and external interrupt flag 2 register (EIFLAG2) are set to ‘1’ when the external interrupt generating condition is satisfied. The flag is cleared when the interrupt service routine is executed.

  • Page 102: Interrupt Register Description

    MC97F2664 10.12.5 Register Map Table 10-2 Interrupt Register Map Name Address Default Description Interrupt Enable Register Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Enable Register 3 IP0L Interrupt Priority 0 Low Register IP0H Interrupt Priority 0 High Register...
  • Page 103 MC97F2664 10.13.1 Register Description for Interrupt IE (Interrupt Enable Register) : A8H – INT5E INT4E INT3E INT2E INT1E INT0E – Initial value : 00H Enable or Disable All Interrupt bits All Interrupt disable All Interrupt enable INT5E Enable or Disable External Interrupt 0 ~ 7 (EINT0 ~ EINT7)
  • Page 104 MC97F2664 IE1 (Interrupt Enable Register 1): A9H – – INT11E INT10E INT9E INT8E INT7E INT6E – – Initial value: 00H INT11E Enable or Disable External interrupt 10 ~ 17 (EINT10 ~ EINT17) Disable Enable INT10E Enable or Disable SPI3 interrupt...
  • Page 105 MC97F2664 IE2 (Interrupt Enable Register 2) : AAH –- – INT17E INT16E INT15E INT14E INT13E INT12E – – Initial value : 00H INT17E Enable or Disable Timer 0/1/2/3 match interrupt Disable Enable INT16E Enable or Disable External interrupt 8 ~ A/18 ~ 19...
  • Page 106 MC97F2664 IE3 (Interrupt Enable Register 3) : ABH – – INT23E INT22E INT21E INT20E INT19E INT18E – – Initial value : 00H INT23E Enable or Disable Timer 0/1/2/3 overflow interrupt Disable Enable INT22E Enable or Disable BIT Interrupt Disable Enable...
  • Page 107 MC97F2664 IP0L (Interrupt Priority 0 Low Register) : 92H – – IP0L5 IP0L4 IP0L3 IP0L2 IP0L1 IP0L0 – – Initial value : 00H IP0H (Interrupt Priority 0 High Register) : 93H – – IP0H5 IP0H4 IP0H3 IP0H2 IP0H1 IP0H0 –...
  • Page 108 MC97F2664 IP2L (Interrupt Priority 2 Low Register) : 9CH – – IP2L5 IP2L4 IP2L3 IP2L2 IP2L1 IP2L0 – – Initial value : 00H IP2H (Interrupt Priority 2 High Register) : 9DH – – IP2H5 IP2H4 IP2H3 IP2H2 IP2H1 IP2H0 –...
  • Page 109 MC97F2664 EIFLAG0 (External Interrupt Flag 0 Register) : A3H FLAG7 FLAG6 FLAG5 FLAG4 FLAG3 FLAG2 FLAG1 FLAG0 Initial value : 00H When an External Interrupt 0 ~ 7 is occurred, the flag becomes ‘1’. EIFLAG0[6:5] The flag is cleared by writing ‘0’ to the bit. Writing “1” has no effect.
  • Page 110 MC97F2664 EIFLAG1 (External Interrupt Flag 1 Register) : A4H FLAG17 FLAG16 FLAG15 FLAG14 FLAG13 FLAG12 FLAG11 FLAG10 Initial value : 00H EIFLAG1[7:0] When an External Interrupt 10 ~ 17 is occurred, the flag becomes ‘1’. The flag is cleared by writing ‘0’ to the bit. So, the flag should be cleared by software.
  • Page 111 MC97F2664 EIFLAG2(External Interrupt Flag 2 Register) : A5H – – – FLAG19 FLAG18 FLAGA FLAG9 FLAG8 – – – Initial value : 00H EIFLAG2[4:0] When an External Interrupt 8 ~ A/18 ~ 19 is occurred, the flag becomes ‘1’. The flag is cleared by writing ‘0’ to the bit. So, the flag should be cleared by software.

  • Page 112: Peripheral Hardware

    MC97F2664 11. Peripheral Hardware 11.1 Clock Generator 11.1.1 Overview As shown in Figure 11.1, the clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and the peripheral hardware. It contains main/sub-frequency clock oscillator. The main/sub clock operation can be easily obtained by attaching a crystal between the XIN/SXIN and XOUT/SXOUT pin, respectively.

  • Page 113: Table 11-1 Clock Generator Register Map

    MC97F2664 11.1.3 Register Map Table 11-1 Clock Generator Register Map Name Address Default Description SCCR System and Clock Control Register OSCCR Oscillator Control Register 11.1.4 Clock Generator Register Description The clock generator register uses clock control for system operation. The clock generation consists of System and clock control register and oscillator control register.
  • Page 114 MC97F2664 OSCCR (Oscillator Control Register) : C8H – – IRCS2 IRCS1 IRCS0 IRCE XCLKE SCLKE – – Initial value : 08H IRCS[2:0] Internal RC Oscillator Post-divider Selection IRCS2 IRCS1 IRCS0 Description INT-RC/32 (0.5MHz) INT-RC/16 (1MHz) INT-RC/8 (2MHz) INT-RC/4 (4MHz) INT-RC/2 (8MHz)

  • Page 115: Basic Interval Timer

    11.2 Basic Interval Timer 11.2.1 Overview The MC97F2664 has one 8-bit basic interval timer that is free-run and can’t stop. Block diagram is shown in Figure 11.2. In addition, the basic interval timer generates the time base for watchdog timer counting. It also provides a basic interval timer interrupt (BITIFR).

  • Page 116: Table 11-2 Basic Interval Timer Register Map

    MC97F2664 11.2.3 Register Map Table 11-2 Basic Interval Timer Register Map Name Address Default Description BITCNT Basic Interval Timer Counter Register BITCR Basic Interval Timer Control Register 11.2.4 Basic Interval Timer Register Description The basic interval timer register consists of basic interval timer counter register (BITCNT) and basic interval timer control register (BITCR).
  • Page 117 MC97F2664 BITCR (Basic Interval Timer Control Register) : 8BH – BITIFR BITCK1 BITCK0 BCLR BCK2 BCK1 BCK0 – Initial value : 01H When BIT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ BITIFR to this bit or auto clear by INT_ACK signal. Writing “1” has no effect.

  • Page 118: Watch Dog Timer

    MC97F2664 11.3 Watch Dog Timer 11.3.1 Overview The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or something like that, and resumes the CPU to the normal state. The watchdog timer signal for malfunction detection can be used as either a CPU reset or an interrupt request.

  • Page 119: Figure 11.4 Watch Dog Timer Block Diagram

    MC97F2664 11.3.3 Block Diagram clear WDT Clock To RESET WDTCNT Circuit WDTEN To interrupt WDTIFR block clear WDTDR INT_ACK WDTCL WDTRSON WDTCR Figure 11.4 Watch Dog Timer Block Diagram 11.3.4 Register Map Table 11-3 Watch Dog Timer Register Map Name...
  • Page 120 MC97F2664 11.3.6 Register Description for Watch Dog Timer WDTCNT (Watch Dog Timer Counter Register: Read Case) : 8EH WDTCNT 7 WDTCNT 6 WDTCNT 5 WDTCNT 4 WDTCNT3 WDTCNT 2 WDTCNT 1 WDTCNT 0 Initial value : 00H WDTCNT[7:0] WDT Counter...

  • Page 121: Watch Timer

    MC97F2664 11.4 Watch Timer 11.4.1 Overview The watch timer has the function for RTC (Real Time Clock) operation. It is generally used for RTC design. The internal structure of the watch timer consists of the clock source select circuit, timer counter circuit, output select circuit, and watch timer control register.

  • Page 122: Table 11-4 Watch Timer Register Map

    MC97F2664 11.4.3 Register Map Table 11-4 Watch Timer Register Map Name Address Default Description WTCNT Watch Timer Counter Register WTDR Watch Timer Data Register WTCR Watch Timer Control Register 11.4.4 Watch Timer Register Description The watch timer register consists of watch timer counter register (WTCNT), watch timer data register (WTDR), and watch timer control register (WTCR).
  • Page 123 MC97F2664 WTCR (Watch Timer Control Register) : 8FH – WTEN WTIE WTIFR WTIN1 WTIN0 WTCK1 WTCK0 – Initial value : 00H WTEN Control Watch Timer Disable Enable WTIE Enable or Disable Watch Timer Interrupt Disable Enable When WT Interrupt occurs, this bit becomes ‘1’. For clearing bit, WTIFR write ‘0’...

  • Page 124: Timer 0/1/2/3

    MC97F2664 11.5 Timer 0/1/2/3 11.5.1 Overview The 8-bit timer 0/1/2/3 consists of multiplexer, timer 0/1/2/3 counter register, timer 0/1/2/3 data register, timer 0/1/2/3 capture data register, and timer 0/1/2/3 control register (TnCNT, TnDR, TnCDR, TnCR). It has three operating modes:...

  • Page 125: Figure 11.6 8-Bit Timer/Counter Mode For Timer 0/1/2/3 (Where N = 0, 1, 2, And 3)

    MC97F2664 11.5.2 8-Bit Timer/Counter Mode The 8-bit timer/counter mode is selected by control register as shown in Figure 11.6. The 8-bit timer have counter and data register. The counter register is increased by internal or external clock input. Timer 0/1/2/3 can use the input clock with one of 2, 4, 8, 32, 128, 512 and 2048 prescaler division rates (TnCK[2:0]).

  • Page 126: Figure 11.8 8-Bit Pwm Mode For Timer 0/1/2/3 (Where N = 0, 1, 2, And 3)

    MC97F2664 11.5.3 8-Bit PWM Mode The timer 0/1/2/3 has a high speed PWM (Pulse Width Modulation) function. In PWM mode, TnO/PWMnO pin outputs up to 8-bit resolution PWM output. This pin should be configured as a PWM output by setting the T0O/PWM0O, T1O/PWM1O,T2O/PWM2O and T3O/PWM3O function by P5FSR0, P5FSR1, P5FSR2, and P5FSR3 bit.

  • Page 127: Figure 11.9 Pwm Output Waveforms In Pwm Mode For Timer 0/1/2 (Where N = 0, 1, 2, And 3)

    MC97F2664 PWM Mode(TnMS = 01b) Set TnEN Timer n clock TnCNT TnDR Tn Overflow Interrupt 1. TnDR = 4AH TnPWM Tn Match Interrupt 2. TnDR = 00H TnPWM Tn Match Interrupt 3. TnDR = FFH TnPWM Tn Match Interrupt Figure 11.9 PWM Output Waveforms in PWM Mode for Timer 0/1/2 (Where n = 0, 1, 2, and 3)

  • Page 128: Figure 11.10 8-Bit Capture Mode For Timer 0/1/2/3 (Where N = 0, 1, 2, And 3)

    MC97F2664 11.5.4 8-Bit Capture Mode The timer 0/1/2/3 capture mode is set by TnMS[1:0] as ‘1x’. The clock source can use the internal/external clock. Basically, it has the same function as the 8-bit timer/counter mode and the interrupt occurs when TnCNT is equal to TnDR.

  • Page 129: Figure 11.11 Input Capture Mode Operation For Timer 0/1/2/3 (Where N = 0, 1, 2, And 3)

    MC97F2664 TnCDR Load TnCNT Value Count Pulse Period Up-count TIME Ext. EINT1n PIN Interrupt Request (FLAG1n) Interrupt Interval Period Figure 11.11 Input Capture Mode Operation for Timer 0/1/2/3 (Where n = 0, 1, 2, and 3) TnCNT Interrupt Request (TnIFR) Ext.

  • Page 130: Figure 11.13 8-Bit Timer 0/1/2/3 Block Diagram (Where N = 0, 1, 2, And 3)

    MC97F2664 11.5.5 Block Diagram Clear TnOVIE To interrupt block TnOVIFR fx/2 fx/4 8-bit Timer n Counter fx/8 Clear TnCC TnCNT (8Bit) fx/32 Match signal TnMIE fx/128 Clear To interrupt fx/512 Match TnEN block TnIFR fx/2048 Comparator Clear TnDR (8Bit) TnMS[1:0]...

  • Page 131: Table 11-6 Timer 0/1/2/3 Register Map

    MC97F2664 11.5.6 Register Map Table 11-6 Timer 0/1/2/3 Register Map Name Address Default Description TnCNT B3H/B6H/BBH/BEH R Timer n Counter Register TnDR B4H/B7H/BCH/BFH R/W Timer n Data Register TnCDR B4H/B7H/BCH/BFH R Timer n Capture Data Register TnCR B2H/B5H/BAH/BDH R/W Timer n Control Register...
  • Page 132 MC97F2664 TnCR (Timer n Control Register) : B2H/B5H/BAH/BDH, n=0, 1, 2, and 3 – TnEN TnMS1 TnMS0 TnCK2 TnCK1 TnCK0 TnCC – Initial value : 00H TnEN Control Timer n Timer n disable Timer n enable TnMS[1:0] Control Timer n Operation Mode...
  • Page 133 MC97F2664 TINTCR(Timer Interrupt Control Register) : 95H T3MIE T2MIE T1MIE T0MIE T3OVIE T2OVIE T1OVIE T0OVIE Initial value : 00H T3MIE Enable or Disable Timer 3Match Interrupt Disable Enable T2MIE Enable or Disable Timer 2 Match Interrupt Disable Enable T1MIE Enable or Disable Timer 1 Match Interrupt...
  • Page 134 MC97F2664 TIFLAG0(Timer Interrupt Flag Register) : 96H T3OVIFR T3IFR T2OVIFR T2IFR T1OVIFR T1IFR T0OVIFR T0IFR Initial value : 00H When T3 overflow interrupt occurs, this bit becomes ‘1’. The flag T3OVIFR is cleared only by writing a ‘0’ to the bit. So, the flag should be cleared by software.

  • Page 135: Timer 4/5

    MC97F2664 11.6 Timer 4/5 11.6.1.1 Overview The 16-bit timer 4/5 consists of multiplexer, timer 4/5 A data register high/low, timer 4/5 B data register high/low and timer 4/5 control register high/low (TnADRH, TnADRL, TnBDRH, TnBDRL, TnCRH, TnCRL). It has four operating modes:...

  • Page 136: Figure 11.14 16-Bit Timer/Counter Mode For Timer 4/5 ( Where N= 4 And 5)

    MC97F2664 ADDRESS:CBH/D3H – – – – TnEN TnMS1 TnMS0 TnCC TnCRH INITIAL VALUE : 0000_0000B – – – – ADDRESS:CAH/D2H – TnCK2 TnCK1 TnCK0 TnIFR TnPOL TnECE TnCNTR TnCRL INITIAL VALUE : 0000_0000B – 16-bit A Data Register TnADRH/TnADRL A Match...

  • Page 137: Figure 11.16 16-Bit Capture Mode For Timer 4/5 ( Where N= 4 And 5)

    MC97F2664 11.6.3 16-Bit Capture Mode The 16-bit timer 4/5 capture mode is set by TnMS[1:0] as ‘01’. The clock source can use the internal/external clock. Basically, it has the same function as the 16-bit timer/counter mode and the interrupt occurs when TnCNTH/TnCNTL is equal to TnADRH/TnADRL.

  • Page 138: Figure 11.17 Input Capture Mode Operation For Timer 4/5 ( Where N= 4 And 5)

    MC97F2664 TnBDRH/L Load TnCNTH/L Value Count Pulse Period Up-count TIME Ext. EINT1n PIN Interrupt Request (FLAG1n) Interrupt Interval Period Figure 11.17 Input Capture Mode Operation for Timer 4/5 ( where n= 4 and 5) FFFF FFFF TnCNTH/L Interrupt Request (TnIFR) Ext.

  • Page 139: Figure 11.19 16-Bit Ppg Mode For Timer 4/5 ( Where N= 4 And 5)

    MC97F2664 11.6.4 16-Bit PPG Mode The timer 4/5 has a PPG (Programmable Pulse Generation) function. In PPG mode, TnO/PWMnO pin outputs up to 16-bit resolution PWM output. This pin should be configured as a PWM output by setting P3FSR0,P3FSR1 to ‘1’. The period of the PWM output is determined by the TnADRH/TnADRL. And the duty of the PWM output is determined by the TnBDRH/TnBDRL.

  • Page 140: Figure 11.20 16-Bit Ppg Mode Timming Chart For Timer 4/5 ( Where N= 4 And 5)

    MC97F2664 Repeat Mode(TnMS = 11b) and "Start High"(TnPOL = 0b). Clear and Start Set TnEN Timer n clock Counter TnADRH/L Tn Interrupt 1. TnBDRH/L(5) < TnADRH/L PWMnO B Match A Match 2. TnBDRH/L >= TnADRH/L PWMnO A Match 3. TnBDRH/L = "0000H"...

  • Page 141: Figure 11.21 16-Bit Timer 4/5 Block Diagram ( Where N= 4 And 5)

    MC97F2664 11.6.5 Block Diagram 16-bit A Data Register TnADRH/TnADRL A Match Reload TnCC TnEN TnECE TnCK[2:0] INT_ACK Buffer Register A To other block Clear Edge Detector A Match To interrupt TnIFR fx/1 block TnEN Comparator fx/2 A Match Clear fx/4...
  • Page 142 MC97F2664 11.6.6.1 Timer/Counter 4/5 Register Description The timer/counter 4/5 register consists of timer 4/5 A data high register (TnADRH), timer 4/5 A data low register (TnADRL), timer 4/5 B data high register (TnBDRH), timer 4/5 B data low register (TnBDRL), timer 4/5 control high register (TnCRH) and timer 4/5 control low register (TnCRL).
  • Page 143 MC97F2664 TnCRH (Timer n Control High Register) : CBH/D3H, n= 4 and 5 – – – – TnEN TnMS1 TnMS0 TnCC – – – – Initial value : 00H TnEN Control Timer n Timer n disable Timer n enable (Counter clear and start)
  • Page 144 MC97F2664 TnCRL (Timer n Control Low Register) : CAH/D2H, n= 4 and 5 – TnCK2 TnCK1 TnCK0 TnIFR TnPOL TnECE TnCNTR – Initial value : 00H TnCK[2:0] Select Timer n clock source. fx is main system clock frequency TnCK2 TnCK1 TnCK0 Description...

  • Page 145: Timer 6/7/8/9

    MC97F2664 11.7 Timer 6/7/8/9 11.7.1.1 Overview The 16-bit timer 6/7/8/9 consists of multiplexer, timer 6/7/8/9 A data register high/low, timer 6/7/8/9 B data register high/low and timer 6/7/8/9 control register high/low (TnADRH, TnADRL, TnBDRH, TnBDRL, TnCRH, TnCRL). It has four operating modes:...

  • Page 146: Figure 11.22 16-Bit Timer/Counter Mode For Timer 6/7/8/9 ( Where N= 6,7,8, And 9)

    MC97F2664 ADDRESS:DBH/E3H/EBH/1059H – – – – TnEN TnMS1 TnMS0 TnCC TnCRH INITIAL VALUE : 0000_0000B – – – – ADDRESS:DAH/E2H/EAH/1058H – TnCK2 TnCK1 TnCK0 TnIFR TnPOL TnECE TnCNTR TnCRL INITIAL VALUE : 0000_0000B – 16-bit A Data Register TnADRH/TnADRL A Match...

  • Page 147: Figure 11.24 16-Bit Capture Mode For Timer 6/7/8/9 ( Where N= 6,7,8, And 9)

    MC97F2664 11.7.3 16-Bit Capture Mode The 16-bit timer 6/7/8/9 capture mode is set by TnMS[1:0] as ‘01’. The clock source can use the internal/external clock. Basically, it has the same function as the 16-bit timer/counter mode and the interrupt occurs when TnCNTH/TnCNTL is equal to TnADRH/TnADRL. The TnCNTH, TnCNTL values are automatically cleared by match signal.

  • Page 148: Figure 11.25 Input Capture Mode Operation For Timer 6/7/8/9 ( Where N= 6,7,8, And 9)

    MC97F2664 TnBDRH/L Load TnCNTH/L Value Count Pulse Period Up-count TIME Ext. EINT1n PIN Interrupt Request (FLAG1n) Interrupt Interval Period Figure 11.25 Input Capture Mode Operation for Timer 6/7/8/9 ( where n= 6,7,8, and 9) FFFF FFFF TnCNTH/L Interrupt Request (TnIFR) Ext.

  • Page 149: Figure 11.27 16-Bit Ppg Mode For Timer 6/7/8/9 ( Where N= 6,7,8, And 9)

    MC97F2664 11.7.4 16-Bit PPG Mode The timer 6/7/8/9 has a PPG (Programmable Pulse Generation) function. In PPG mode, TnO/PWMnO pin outputs up to 16-bit resolution PWM output. This pin should be configured as a PWM output by setting P3FSR2,P2FSR0,P2FSR1,P2FSR2 to ‘1’. The period of the PWM output is determined by the TnADRH/TnADRL.

  • Page 150: Figure 11.28 16-Bit Ppg Mode Timming Chart For Timer 6/7/8/9 ( Where N= 6,7,8, And 9)

    MC97F2664 Repeat Mode(TnMS = 11b) and "Start High"(TnPOL = 0b). Clear and Start Set TnEN Timer n clock Counter TnADRH/L Tn Interrupt 1. TnBDRH/L(5) < TnADRH/L PWMnO B Match A Match 2. TnBDRH/L >= TnADRH/L PWMnO A Match 3. TnBDRH/L = "0000H"...

  • Page 151: Figure 11.29 16-Bit Timer 6/7/8/9 Block Diagram ( Where N= 6,7,8, And 9)

    MC97F2664 11.7.5 Block Diagram 16-bit A Data Register TnADRH/TnADRL A Match Reload TnCC TnEN TnECE TnCK[2:0] TnMIE Buffer Register A To other block Clear Edge To interrupt Detector A Match block TnIFR fx/1 TnEN Comparator fx/2 A Match Clear fx/4...
  • Page 152 MC97F2664 11.7.6.1 Timer/Counter 6/7/8/9 Register Description The timer/counter 6/7/8/9 register consists of timer 6/7/8/9 A data high register (TnADRH), timer 6/7/8/9 A data low register (TnADRL), timer 6/7/8/9 B data high register (TnBDRH), timer 6/7/8/9 B data low register (TnBDRL), timer 6/7/8/9 control high register (TnCRH), timer 6/7/8/9 control low register (TnCRL), and timer interrupt flag register(TIFLAG1).
  • Page 153 MC97F2664 TnCRH (Timer n Control High Register) : DBH/E3H/EBH/1059H (SFR/SFR/SFR/XSFR), n= 6, 7, 8, and 9 – – – TnEN TnMIE TnMS1 TnMS0 TnCC – – – Initial value : 00H TnEN Control Timer n Timer n disable Timer n enable (Counter clear and start)
  • Page 154 MC97F2664 TnCRL (Timer n Control Low Register) : DAH/E2H/EAH/1058H (SFR/SFR/SFR/XSFR), n= 6, 7, 8, and 9 – – TnCK2 TnCK1 TnCK0 TnPOL TnECE TnCNTR – – Initial value : 00H TnCK[2:0] Select Timer n clock source. fx is main system clock frequency...
  • Page 155 MC97F2664 TIFLAG1(Timer Interrupt Flag 1 Register) : 97H – – – – T9IFR T8IFR T7IFR T6IFR – – – – Initial value : 00H When T9 interrupt occurs, this bit becomes ‘1’ The flag is cleared T9IFR only by writing a ‘0’ to the bit. So, the flag should be cleared by software.

  • Page 156: Buzzer Driver

    MC97F2664 11.8 Buzzer Driver 11.8.1 Overview The Buzzer consists of 6 bit counter, buzzer data register (BUZDR), and buzzer control register (BUZCR). The Square Wave (244.140Hz~125.0 kHz @f = 2MHz) is outputted through P33/BUZO pin. In buzzer data register (BUZDR),BUZDR[5:0] controls the buzzer frequency (look at the following expression) and BUZDIV[1:0] selects divided by DIV block .

  • Page 157: Table 11-12 Buzzer Driver Register Map

    MC97F2664 11.8.3 Register Map Table 11-12 Buzzer Driver Register Map Name Address Default Description BUZDR Buzzer Data Register BUZCR Buzzer Control Register 11.8.4 Buzzer Driver Register Description Buzzer driver consists of buzzer data register (BUZDR) and buzzer control register (BUZCR).
  • Page 158 MC97F2664 BUZCR (Buzzer Control Register) : F2H – – – – BUCK2 BUCK1 BUCK0 BUZEN – – – – Initial value : 00H BUCK[2:0] Buzzer Driver Source Clock Selection BUCK2 BUCK1 BUCK0 Description fx/1 fx/2 fx/4 fx/8 fx/16 fx/32 fx/64...

  • Page 159: Spi 2/3

    11.9 SPI 2/3 11.9.1 Overview There is serial peripheral interface (SPI 2/3) one channel in MC97F2664. The SPI 2/3 allows synchronous serial data transfer between the external serial devices. It can do Full-duplex communication by 4-wire (MOSI2/3, MISO2/3, SCK2/3, SS2/3), support master/slave mode, can select serial clock (SCK2/3) polarity, phase and whether LSB first data transfer or MSB first data transfer.
  • Page 160 MC97F2664 11.9.3 Data Transmit / Receive Operation User can use SPI 2/3 for serial data communication by following step 1. Select SPI 2/3 operation mode(master/slave, polarity, phase) by control register SPInCR. 2. When the SPI 2/3 is configured as a Master, it selects a Slave by SS2/3 signal (active low).

  • Page 161: Figure 11.32 Spi 2/3 Transmit/Receive Timing Diagram At Cpha = 0 (Where N = 2 And 3)

    MC97F2664 11.9.5 SPI 2/3 Timing Diagram SCKn (CPOLn = 0) SCKn (CPOLn = 1) MISOn/MOSIn (Output) MOSIn/MISOn (Input) SPInIFR Figure 11.32 SPI 2/3 Transmit/Receive Timing Diagram at CPHA = 0 (Where n = 2 and 3) SCKn (CPOLn = 0)

  • Page 162: Table 11-13 Spi 2/3 Register Map

    MC97F2664 11.9.6 Register Map Table 11-13 SPI 2/3 Register Map Name Address Default Description SPInSR C4H/C7H SPI n Status Register SPInDR C3H/C6H SPI n Data Register SPInCR C2H/C5H SPI n Control Register 11.9.7 SPI 2/3 Register Description The SPI 2/3 register consists of SPI 2/3 control register (SPInCR), SPI 2/3 status register (SPInSR) and SPI 2/3 data register (SPInDR) 11.9.8 Register Description for SPI 2/3...
  • Page 163 MC97F2664 SPInSR (SPI 2/3 Status Register) : C4H/C7H, n= 2, 3 – – – SPIInFR WCOLn SS_HIGHn FXCHn SPInSSEN – – – Initial value : 00H When SPI 2/3 Interrupt occurs, this bit becomes ‘1’. If SPI 2/3 interrupt is SPIIFRn enable, this bit is auto cleared by INT_ACK signal.
  • Page 164 MC97F2664 SPInCR (SPI 2/3 Control Register) : C2H/C5H, n= 2, 3 SPInEN FLSBn SPInMS CPOLn CPHAn SPInDSCR SPInSCR1 SPInSCR0 Initial value : 00H SPInEN This bit controls the SPI 2/3 operation Disable SPI 2/3 operation Enable SPI 2/3 operation FLSBn...

  • Page 165: Uart2/3/4

    MC97F2664 11.10 UART2/3/4 11.10.1 Overview The universal asynchronous serial receiver and transmitter (UART2/3/4) is a highly flexible serial communication device. The main features are listed below. - Full Duplex Operation (Independent Serial Receive and Transmit Registers) - Baud Rate Generator...

  • Page 166: Figure 11.34 Uart Block Diagram(Where N = 2,3, And 4)

    MC97F2664 11.10.2 Block Diagram To interrupt block UARTnBD WAKEIEn RXCIEn SCLK Baud Rate Generator At Stop mode WAKEn Low level RXCn detector RXDn Clock Control Recovery Data Receive Shift Register Recovery (RXSR) LOOPSn DORn/PEn/FEn UARTnDR[0] Checker (Rx) UARTnDR[1] (Rx) Stop bit...

  • Page 167: Figure 11.35 Clock Generation Block Diagram (Where N = 2,3, And 4)

    MC97F2664 11.10.3 Clock Generation UARTnBD U2Xn SCLK (UARTnBD+1) Baud Rate SCLK Generator txclk rxclk Figure 11.35 Clock Generation Block Diagram (where n = 2,3, and 4) The clock generation logic generates the base clock for the transmitter and receiver. Following table shows equations for calculating the baud rate (in bps).

  • Page 168: Figure 11.36 Frame Format

    MC97F2664 11.10.4 Data format A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error detection. The UART2/3/4 supports all 30 combinations of the following as valid frame formats.
  • Page 169 MC97F2664 11.10.6 UART2/3/4 Transmitter The UART2/3/4 transmitter is enabled by setting the TXEn bit in UARTnCR2 register. When the Transmitter is enabled, the TXDn pin should be set to TXDn function for the serial output pin of UART2/3/4 by the P4FSR3/ P4FSR4/P2FSR3.
  • Page 170 MC97F2664 11.10.6.3 Parity Generator The parity generator calculates the parity bit for the serial frame data to be sent. When parity bit is enabled (UnPM[1]=1), the transmitter control logic inserts the parity bit between the MSB and the first stop bit of the frame to be sent.
  • Page 171 MC97F2664 11.10.7.2 Receiver Flag and Interrupt The UART2/3/4 receiver has one flag that indicates the receiver state. The receive complete (RXCn) flag indicates whether there are unread data in the receive buffer. This flag is set when there are unread data in the receive buffer and cleared when the receive buffer is empty. If the receiver is disabled (RXEn=0), the receiver buffer is flushed and the RXCn flag is cleared.

  • Page 172: Figure 11.37 Start Bit Sampling (Where N = 2,3, And 4)

    MC97F2664 11.10.7.5 Asynchronous Data Reception To receive asynchronous data frame, the UART includes a clock and data recovery unit. The clock recovery logic is used for synchronizing the internally generated baud-rate clock to the incoming asynchronous serial frame on the RXDn pin.

  • Page 173: Figure 11.39 Stop Bit Sampling And Next Start Bit Sampling (Where N = 2,3, And 4)

    MC97F2664 The process for detecting stop bit is like clock and data recovery process. That is, if 2 or more samples of 3 center values have high level, correct stop bit is detected, else a frame error (FEn) flag is set. After deciding whether the first stop bit is valid or not, the Receiver goes to idle state and monitors the RXD line to check a valid high to low transition is detected (start bit detection).
  • Page 174 MC97F2664 UARTnDR (UARTn Data Register) : 103DH/1045H/104DH (XSFR), Where n = 2, 3, and 4 UARTnDR7 UARTnDR6 UARTnDR5 UARTnDR4 UARTnDR3 UARTnDR2 UARTnDR1 UARTnDR0 Initial value : 00H UARTnDR [7:0] The UARTn Transmit Buffer and Receive Buffer share the same I/O address with this DATA register.
  • Page 175 MC97F2664 UARTnCR2 (UARTn Control Register 2) : 1039H/1041H/1049H (XSFR), Where n = 2, 3, and 4 UDRIEn TXCIEn RXCIEn WAKEIEn TXEn RXEn UARTnEN U2Xn Initial value : 00H UDRIEn Interrupt enable bit for UARTn Data Register Empty Interrupt from UDREn is inhibited (use polling)
  • Page 176 MC97F2664 UARTnCR3 (UARTn Control Register 3) : 103AH/1042H/104AH (XSFR), Where n = 2, 3, and 4 LOOPSn USBSn UnTX8 UnRX8 Initial value : 00H LOOPSn Controls the Loop Back Mode of UARTn, for test mode Normal operation Loop Back mode USBSn Selects the length of stop bit.
  • Page 177 MC97F2664 UARTnST (UARTn Status Register) : 103BH/1043H/104BH (XSFR), Where n = 2, 3, and 4 UDREn TXCn RXCn WAKEn SOFTRSTn DORn Initial value : 80H UDREn The UDREn flag indicates if the transmit buffer (UARTnDR) is ready to receive new data. If UDREn is ‘1’, the buffer is empty and ready to be written.

  • Page 178: Table 11-16 Examples Of Uartnbd Settings For Commonly Used Oscillator Frequencies

    MC97F2664 11.10.11 Baud Rate setting (example) Table 11-16 Examples of UARTnBD Settings for Commonly Used Oscillator Frequencies fx=1.00MHz fx=1.8432MHz fx=2.00MHz Baud Rate UARTnBD ERROR UARTnBD ERROR UARTnBD ERROR 2400 0.2% 0.0% 0.2% 4800 0.2% 0.0% 0.2% 9600 -7.0% 0.0% 0.2% 14.4k...

  • Page 179: Usi0/1 (Uart + Spi + I2C)

    MC97F2664 11.11 USI0/1 (UART + SPI + I2C) 11.11.1 Overview The USI0/1 consists of USI0/1 control register1/2/3/4, USI0/1 status register 1/2, USI0/1 baud-rate generation register, USI0/1 data register, USI0/1 SDA hold time register, USI0/1 SCL high period register, USI0/1 SCL low period register, and USI0/1 slave address register (USInCR1, USInCR2, USInCR3, USInCR4, USInST1, USInST2, USInBD, USInDR, USInSDHR, USInSCHR, USInSCLR, USInSAR).
  • Page 180 MC97F2664 11.11.2 USI0/1 UART Mode The universal synchronous and asynchronous serial receiver and transmitter (UART) is a highly flexible serial communication device. The main features are listed below. - Full Duplex Operation (Independent Serial Receive and Transmit Registers) - Asynchronous or Synchronous Operation...

  • Page 181: Figure 11.40 Usi0/1 Uart Block Diagram (Where N = 0 And 1)

    MC97F2664 11.11.3 USI0/1 UART Block Diagram Master SCKn Control USInMS[1:0] SCLK USInBD (fx: System clock) To interrupt block Baud Rate Generator DBLSn WAKEIEn RXCIEn Clock Sync Logic At Stop mode WAKEn Low level RXCn detector RXDn Clock Recovery Control USInS[2:0]...

  • Page 182: Figure 11.41 Clock Generation Block Diagram (Usin, Where N = 0 And 1)

    MC97F2664 11.11.4 USI0/1 Clock Generation USInBD DBLSn SCLK (USInBD+1) Prescaling Up-Counter txclk SCLK MASTERn Edge Sync Register USInMS[1:0] Detector CPOLn SCKn rxclk Figure 11.41 Clock Generation Block Diagram (USIn, where n = 0 and 1) The clock generation logic generates the base clock for the transmitter and receiver. The USI0/1 supports four modes of clock operation and those are normal asynchronous, double speed asynchronous, master synchronous and slave synchronous mode.

  • Page 183: Figure 11.42 Synchronous Mode Sckn Timing (Usin , Where N = 0 And 1)

    MC97F2664 11.11.5 USI0/1 External Clock (SCKn) External clocking is used in the synchronous mode of operation. External clock input from the SCKn pin is sampled by a synchronization logic to remove meta-stability. The output from the synchronization logic must be passed through an edge detector before it is used by the transmitter and receiver.

  • Page 184: Figure 11.43 Frame Format (Usi0/1)

    MC97F2664 11.11.7 USI0/1 UART Data format A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error detection. The UART supports all 30 combinations of the following as valid frame formats.
  • Page 185 MC97F2664 11.11.9 USI0/1 UART Transmitter The UART transmitter is enabled by setting the TXEn bit in USInCR2 register. When the Transmitter is enabled, the TXDn pin should be set to TXDn function for the serial output pin of UART by the P6FSR2/P4FSR0. The baud-rate, operation mode and frame format must be setup once before doing any transmission.
  • Page 186 MC97F2664 11.11.9.3 USI0/1 UART Parity Generator The parity generator calculates the parity bit for the serial frame data to be sent. When parity bit is enabled (USInPM1=1), the transmitter control logic inserts the parity bit between the MSB and the first stop bit of the frame to be sent.
  • Page 187 MC97F2664 11.11.10.2 USI0/1 UART Receiver Flag and Interrupt The UART receiver has one flag that indicates the receiver state. The receive complete (RXCn) flag indicates whether there are unread data in the receive buffer. This flag is set when there are unread data in the receive buffer and cleared when the receive buffer is empty. If the receiver is disabled (RXEn=0), the receiver buffer is flushed and the RXCn flag is cleared.

  • Page 188: Figure 11.44 Asynchronous Start Bit Sampling (Usin, Where N = 0 And 1)

    MC97F2664 11.11.10.5 USI0/1 Asynchronous Data Reception To receive asynchronous data frame, the UART includes a clock and data recovery unit. The clock recovery logic is used for synchronizing the internally generated baud-rate clock to the incoming asynchronous serial frame on the RXDn pin.

  • Page 189: Figure 11.46 Stop Bit Sampling And Next Start Bit Sampling (Usin, Where N = 0 And 1)

    MC97F2664 The process for detecting stop bit is like clock and data recovery process. That is, if 2 or more samples of 3 center values have high level, correct stop bit is detected, else a frame error (FEn) flag is set. After deciding whether the first stop bit is valid or not, the Receiver goes to idle state and monitors the RXDn line to check a valid high to low transition is detected (start bit detection).

  • Page 190: Table 11-18 Cpoln Functionality (Where N = 0 And 1)

    MC97F2664 11.11.11 USI0/1 SPI Mode The USI0/1 can be set to operate in industrial standard SPI compliant mode. The SPI mode has the following features. - Full Duplex, Three-wire synchronous data transfer - Mater and Slave Operation - Supports all four SPI0 modes of operation (mode 0, 1, 2, and 3)

  • Page 191: Figure 11.47 Usi0/1 Spi Clock Formats When Cphan=0 (Where N = 0 And 1)

    MC97F2664 SCKn (CPOLn=0) SCKn (CPOLn=1) SAMPLE MOSIn MSB First … BIT7 BIT6 BIT2 BIT1 BIT0 LSB First … BIT0 BIT1 BIT5 BIT6 BIT7 MISOn /SSn OUT (MASTER) /SSn IN (SLAVE) Figure 11.47 USI0/1 SPI Clock Formats when CPHAn=0 (where n = 0 and 1) When CPHAn=0, the slave begins to drive its MISOn output with the first data bit value when SSn goes to active low.

  • Page 192: Figure 11.48 Usi0/1 Spi Clock Formats When Cphan=1 (Where N = 0 And 1)

    MC97F2664 SCKn (CPOLn=0) SCKn (CPOLn=1) SAMPLE MOSIn … MSB First BIT7 BIT6 BIT2 BIT1 BIT0 … LSB First BIT0 BIT1 BIT5 BIT6 BIT7 MISOn /SSn OUT (MASTER) /SSn IN (SLAVE) Figure 11.48 USI0/1 SPI Clock Formats when CPHAn=1 (where n = 0 and 1) When CPHAn=1, the slave begins to drive its MISOn output when SSn goes active low, but the data is not defined until the first SCKn edge.

  • Page 193: Figure 11.49 Usi0/1 Spi Block Diagram (Where N = 0 And 1)

    MC97F2664 11.11.13 USI0/1 SPI Block Diagram USInBD Control SCLK Baud Rate Generator (fx: System clock) MASTERn USInSSEN Edge Detector SCKn Control Controller FXCHn RXEn CPOLn CPHAn MISOn Data Receive Shift Register Rx Control Recovery (RXSR) RXCn RXCIEn DORn Checker USInDR[0], (Rx)

  • Page 194: Figure 11.50 Bit Transfer On The I2C-Bus (Usin, Where N = 0 And 1)

    MC97F2664 11.11.14 USI0/1 I2C Mode The USI0/1 can be set to operate in industrial standard serial communication protocols mode. The I2C mode uses 2 bus lines serial data line (SDAn) and serial clock line (SCLn) to exchange data. Because both SDAn and SCLn lines are open-drain output, each line needs pull-up resistor.

  • Page 195: Figure 11.51 Start And Stop Condition (Usin, Where N = 0 And 1)

    MC97F2664 11.11.16 USI0/1 I2C Start / Repeated Start / Stop One master can issue a START (S) condition to notice other devices connected to the SCLn, SDAn lines that it will use the bus. A STOP (P) condition is generated by the master to release the bus lines so that other devices can use it.

  • Page 196: Figure 11.53 Acknowledge On The I2C-Bus (Usin, Where N = 0 And 1)

    MC97F2664 11.11.18 USI0/1 I2C Acknowledge The acknowledge related clock pulse is generated by the master. The transmitter releases the SDAn line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDAn line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse. When a slave is addressed by a master (Address Packet), and if it is unable to receive or transmit because it’s performing some real time...

  • Page 197: Figure 11.54 Clock Synchronization During Arbitration Procedure (Usin, Where N = 0 And 1)

    MC97F2664 Wait High Start High Counting Counting Fast Device SCLOUT High Counter Reset Slow Device SCLOUT SCLn Figure 11.54 Clock Synchronization during Arbitration Procedure (USIn, where n = 0 and 1) Arbitration Process Device 1 loses Device1 outputs not adapted...
  • Page 198 MC97F2664 11.11.20.1 USI0/1 I2C Master Transmitter To operate I2C in master transmitter, follow the recommended steps below. Enable I2C by setting USInMS[1:0] bits in USInCR1 and USInEN bit in USInCR2. This provides main clock to the peripheral. Load SLAn+W into the USInDR where SLAn is address of slave device and W is transfer direction from the viewpoint of the master.

  • Page 199: Figure 11.56 Formats And States In The Master Transmitter Mode (Usin, Where N = 0 And 1)

    MC97F2664 The next figure depicts above process for master transmitter operation of I2C. Master S or Sr SLA+R Receiver SLA+W 0x86 0x22 STOP 0x0E 0x87 LOST DATA STOP LOST LOST& Slave Receiver (0x1D) 0x0F 0x1D 0x1F or Transmitter (0x1F) 0x46...
  • Page 200 MC97F2664 11.11.20.2 USI0/1 I2C Master Receiver To operate I2C in master receiver, follow the recommended steps below. Enable I2C by setting USInMS[1:0] bits in USInCR1 and USInEN bit in USInCR2. This provides main clock to the peripheral. Load SLAn+R into the USInDR where SLA is address of slave device and R is transfer direction from the viewpoint of the master.

  • Page 201: Figure 11.57 Formats And States In The Master Receiver Mode (Usin, Where N = 0 And 1)

    MC97F2664 This is the final step for master receiver function of I2C, handling STOP interrupt. The STOP bit indicates that data transfer between master and slave is over. To clear USInST2, write any value to USInST2. After this, I2C enters idle state.
  • Page 202 MC97F2664 11.11.20.3 USI0/1 I2C Slave Transmitter To operate I2C in slave transmitter, follow the recommended steps below. If the main operating clock (SCLK) of the system is slower than that of SCLn, load value 0x00 into USInSDHR to make SDAn change within one system clock period from the falling edge of SCLn. Note that the hold time of SDAn is calculated by SDAH x period of SCLK where SDAH is multiple of number of SCLK coming from USInSDHR.

  • Page 203: Figure 11.58 Formats And States In The Slave Transmitter Mode (Usin, Where N = 0 And 1)

    MC97F2664 The next figure shows flow chart for handling slave transmitter function of I2C. IDLE S or Sr SLA+R GCALL 0x97 0x1F LOST& 0x17 DATA 0x22 STOP 0x47 0x46 IDLE From master to slave / Interrupt, SCLn line is held low...
  • Page 204 MC97F2664 11.11.20.4 USI0/1 I2C Slave Receiver To operate I2C in slave receiver, follow the recommended steps below. 1. If the main operating clock (SCLK) of the system is slower than that of SCLn, load value 0x00 into USInSDHR to make SDAn change within one system clock period from the falling edge of SCLn. Note that the hold time of SDAn is calculated by SDAH x period of SCLK where SDAH is multiple of number of SCLK coming from USInSDHR.

  • Page 205: Figure 11.59 Formats And States In The Slave Receiver Mode (Usin, Where N = 0 And 1)

    MC97F2664 The process can be depicted as following figure when I2C operates in slave receiver mode. IDLE S or Sr SLA+W GCALL 0x95 0x1D LOST& 0x15 DATA 0x20 STOP 0x44 0x45 IDLE From master to slave / Interrupt, SCLn line is held low...

  • Page 206: Figure 11.60 Usi0/1 I2C Block Diagram (Where N = 0 And 1)

    MC97F2664 11.11.21 USI0/1 I2C Block Diagram IICnIFR To interrupt block Slave Address Register USInSAR RXACKn, GCALLn, Interrupt IICnIE TENDn, STOPDn, Generator SSELn, MLOSTn, General Call And USInGCE BUSYn, TMODEn Address Detector Receive Shift Register SDAn USInDR, (Rx) (RXSR) SDA In/Out...

  • Page 207: Table 11-19 Usi0/1 Register Map (Where N = 0 And 1)

    MC97F2664 11.11.22 Register Map Table 11-19 USI0/1 Register Map (where n = 0 and 1) Name Address Default Description USInBD 1022H/1032H (XSFR) USIn Baud Rate Generation Register USInDR 1024H/1034H (XSFR) USIn Data Register USInSDHR 1023H/1033H (XSFR) USIn SDA Hold Time Register...
  • Page 208 MC97F2664 USInDR (USI0/1 Data Register: For UART, SPI, and I2C mode) : 1024H/1034H (XSFR), n = 0, 1 USInDR7 USInDR 6 USInDR 5 USInDR 4 USInDR 3 USInDR 2 USInDR 1 USInDR 0 Initial value : 00H USInDR[7:0] The USIn transmit buffer and receive buffer share the same I/O address with this DATA register.
  • Page 209 MC97F2664 USInSCLR (USI0/1 SCL Low Period Register: For I2C mode) : 1025H/1035H (XSFR), n = 0, 1 USInSCLR7 USInSCLR6 USInSCLR5 USInSCLR 4 USInSCLR 3 USInSCLR 2 USInSCLR 1 USInSCLR 0 Initial value : 3FH USInSCLR[7:0] This register defines the high period of SCL when it operates in I2C master mode.
  • Page 210 MC97F2664 USInCR1 (USI0/1 Control Register 1: For UART, SPI, and I2C mode) : 1018H/1028H (XSFR), n = 0, 1 USInS1 USInS0 USInMS1 USInMS0 USInPM1 USInPM0 USInS2 CPOLn ORDn CPHAn Initial value : 00H USInMS[1:0] Selects operation mode of USIn USInMS1...
  • Page 211 MC97F2664 USInCR2 (USI0/1 Control Register 2: For UART, SPI, and I2C mode) : 1019H/1029H (XSFR), n = 0, 1 DRIEn TXCIEn RXCIEn WAKEIEn TXEn RXEn USInEN DBLSn Initial value : 00H DRIEn Interrupt enable bit for data register empty (only UART and SPI mode).
  • Page 212 MC97F2664 USInCR3 (USI0/1 Control Register 3: For UART, SPI, and I2C mode) : 101AH/102AH (ESFR), n = 0, 1 MASTERn LOOPSn DISSCKn USInSSEN FXCHn USInSB USInTX8 USInRX8 Initial value : 00H MASTERn Selects master or slave in SPI and synchronous mode operation and controls the direction of SCKn pin Slave mode operation (External clock for SCK).
  • Page 213 MC97F2664 USInCR4 (USI0/1 Control Register 4: For I2C mode) : 101BH/102BH (XSFR), n = 0, 1 – IICnIFR TXDLYENBn IICnIE ACKnEN IMASTERn STOPCn STARTCn – Initial value : 00H IICnIFR This is an interrupt flag bit for I2C mode. When an interrupt occurs, this bit becomes ‘1’.
  • Page 214 MC97F2664 USInST1 (USI0/1 Status Register 1: For UART and SPI mode) : 1020H/1030H (XSFR), n = 0, 1 DREn TXCn RXCn WAKEn USInRST DORn Initial value : 80H DREn The DREn flag indicates if the transmit buffer (USInDR) is ready to receive new data.
  • Page 215 MC97F2664 USInST2 (USI0/1 Status Register 2: For I2C mode) : 1021H/1031H (XSFR), n = 0, 1 GCALLn TENDn STOPDn SSELn MLOSTn BUSYn TMODEn RXACKn Initial value : 00H (NOTE) GCALLn This bit has different meaning depending on whether I2C is master or slave.

  • Page 216: Baud Rate Setting (Example)

    MC97F2664 11.12 Baud Rate setting (example) Table 11-20 Examples of USI0BD and USI1BD Settings for Commonly Used Oscillator Frequencies fx=1.00MHz fx=1.8432MHz fx=2.00MHz Baud Rate USI0BD/USI1BD ERROR USI0BD/USI1BD ERROR USI0BD/USI1BD ERROR 2400 0.2% 0.0% 0.2% 4800 0.2% 0.0% 0.2% 9600 -7.0% 0.0%...

  • Page 217: 12-Bit A/D Converter

    MC97F2664 11.13 12-Bit A/D Converter 11.13.1 Overview The analog-to-digital converter (A/D) allows conversion of an analog input signal to corresponding 12-bit digital value. The A/D module has fifteen analog inputs. The output of the multiplexer is the input into the converter which generates the result through successive approximation.

  • Page 218: Figure 11.61 12-Bit Adc Block Diagram

    MC97F2664 11.13.3 Block Diagram TRIG[2:0] ADST T4 match signal T5 match signal Start T6 match signal T7 match signal ADSEL[3:0] CKSEL[1:0] T8 match signal (Select one input pin T9 match signal of the assigned pins) fx/1 fx/2 Clear fx/4 fx/8...

  • Page 219: Figure 11.64 Adc Operation For Align Bit

    MC97F2664 11.13.4 ADC Operation Align bit set “0” ADCO11 ADCO10 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0 ADCDRH7 ADCDRH6 ADCDRH5 ADCDRH4 ADCDRH3 ADCDRH2 ADCDRH1 ADCDRH0 ADCDRL7 ADCDRL6 ADCDRL5 ADCDRL4 ADCDRH[7:0] ADCDRL[7:4] ADCDRL[3:0] bits are “0” Align bit set “1”...

  • Page 220: Figure 11.65 A/D Converter Operation Flow

    MC97F2664 SET ADCCRH Select ADC Clock and Data Align Bit. SET ADCCRL ADC enable & Select AN Input Channel. Converting START Start ADC Conversion. If Conversion is completed, AFLAG is set “1” and ADC AFLAG = 1? interrupt is occurred.
  • Page 221 MC97F2664 11.13.7 Register Description for ADC ADCDRH (A/D Converter Data High Register) : 1053H (XSFR) ADDM11 ADDM10 ADDM9 ADDM8 ADDM7 ADDM6 ADDM5 ADDM4 ADDL11 ADDL10 ADDL9 ADDL8 Initial value : xxH ADDM[11:4] MSB align, A/D Converter High Data (8-bit) ADDL[11:8]...
  • Page 222 MC97F2664 ADCCRH (A/D Converter High Register) : 1051H (XSFR) – ADCIFR TRIG2 TRIG1 TRIG0 ALIGN CKSEL1 CKSEL0 – Initial value : 00H When ADC interrupt occurs, this bit becomes ‘1’. For clearing bit, ADCIFR write ‘0’ to this bit or auto clear by INT_ACK signal. Writing “1” has no effect.
  • Page 223 MC97F2664 ADCCRL (A/D Converter Counter Low Register) : 1050H (XSFR) STBY ADST REFSEL AFLAG ADSEL3 ADSEL2 ADSEL1 ADSEL0 Initial value : 00H STBY Control Operation of A/D (The ADC module is automatically disabled at stop mode) ADC module disable ADC module enable ADST Control A/D Conversion start.

  • Page 224: Power Down Operation

    12. Power Down Operation 12.1 Overview The MC97F2664 has two power-down modes to minimize the power consumption of the device. In power down mode, power consumption is reduced considerably. The device provides three kinds of power saving functions, Main-IDLE, Sub-IDLE and STOP mode. In three modes, program is stopped.

  • Page 225: Idle Mode

    MC97F2664 12.3 IDLE Mode The power control register is set to ‘01h’ to enter the IDLE Mode. In this mode, the internal oscillation circuits remain active. Oscillation continues and peripherals are operated normally but CPU stops. It is released by reset or interrupt.

  • Page 226: Stop Mode

    MC97F2664 12.4 STOP Mode The power control register is set to ‘03H’ to enter the STOP Mode. In the stop mode, the selected oscillator, system clock and peripheral clock is stopped, but watch timer can be continued to operate with sub clock. With the clock frozen, all functions are stopped, but the on-chip RAM and control registers are held.

  • Page 227: Release Operation Of Stop Mode

    MC97F2664 12.5 Release Operation of STOP Mode After STOP mode is released, the operation begins according to content of related interrupt register just before STOP mode start (Figure 12.3). If the global interrupt Enable Flag (IE.EA) is set to `1`, the STOP mode is released by the interrupt which each interrupt enable flag = `1` and the CPU jumps to the relevant interrupt service routine.

  • Page 228: Table 12-2 Power Down Operation Register Map

    MC97F2664 12.5.1 Register Map Table 12-2 Power Down Operation Register Map Name Address Default Description PCON Power Control Register 12.5.2 Power Down Operation Register Description The power down operation register consists of the power control register (PCON). 12.5.3 Register Description for Power Down Operation PCON (Power Control Register) : 87H –...

  • Page 229: Reset

    Control Register Refer to the Peripheral Registers 13.2 Reset Source The MC97F2664 has five types of reset sources. The following is the reset sources. - External RESETB - Power ON RESET (POR) - WDT Overflow Reset (In the case of WDTEN = `1`)

  • Page 230: Reset Noise Canceller

    MC97F2664 13.4 RESET Noise Canceller The Figure 13.2 is the noise canceller diagram for noise cancellation of RESET. It has the noise cancellation value of about 2us (@V =5V) to the low input of system reset. t < T t < T t >...

  • Page 231: Figure 13.5 Configuration Timing When Power-On

    MC97F2664 Counting for config read start after POR is released Internal nPOR PAD RESETB “H” LVR_RESETB .. 27 28 BIT (for Config) 00 01 02 03 BIT (for Reset) 1us X 256 X 28h = about 10ms Config Read 1us X 4096 X 4h = about 16ms...

  • Page 232: Table 13-2 Boot Process Description

    MC97F2664 Table 13-2 Boot Process Description Process Description Remarks ① -No Operation ② -1st POR level Detection -about 1.4V - (INT-OSC 16MHz/16)x256x28h Delay section (=10ms) ③ -Slew Rate 0.15V/ms -VDD input voltage must rise over than flash operating voltage for Config read -about 1.5V ~ 1.6V...

  • Page 233: External Resetb Input

    MC97F2664 13.6 External RESETB Input The External RESETB is the input to a Schmitt trigger. If RESETB pin is held with low for at least 10us over within the operating voltage range and stable oscillation, it is applied and the internal state is initialized. After reset state becomes ‘1’, it needs the stabilization time with 16ms and after the stable state, the internal RESET...

  • Page 234: Brown Out Detector Processor

    13.7 Brown Out Detector Processor The MC97F2664 has an On-chip brown-out detection circuit (BOD) for monitoring the VDD level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by LVRVS[3:0] bit to be 1.60V/ 2.00V/ 2.10V/ 2.20V/2.32V/ 2.44V/ 2.59V/ 2.75V/ 2.93V/ 3.14V/ 3.38V/ 3.67V/ 4.00V/ 4.40V.

  • Page 235: Lvi Block Diagram

    MC97F2664 “H” “H” Internal nPOR “H” PAD RESETB LVR_RESETB ..27 28 BIT (for Config) 00 01 02 BIT (for Reset) 1us X 256 X 28h = about 10ms Config Read 1us X 4096 X 4h = about 16ms...

  • Page 236: Table 13-3 Reset Operation Register Map

    MC97F2664 13.8.1 Register Map Table 13-3 Reset Operation Register Map Name Address Default Description RSTFR Reset Flag Register LVRCR Low Voltage Reset Control Register LVICR Low Voltage Indicator Control Register 13.8.2 Reset Operation Register Description The reset control register consists of the reset flag register (RSTFR), low voltage reset control register (LVRCR), and low voltage indicator control register (LVICR).
  • Page 237 MC97F2664 LVRCR (Low Voltage Reset Control Register) : D8H – – LVRST LVRVS3 LVRVS2 LVRVS1 LVRVS0 LVREN – – Initial value : 00H LVRST LVR Enable when Stop Release Not effect at stop release LVR enable at stop release NOTES) When this bit is ‘1’, the LVREN bit is cleared to ‘0’...
  • Page 238 MC97F2664 LVICR (Low Voltage Indicator Control Register) : 86H – – LVIF LVIEN LVILS3 LVILS2 LVILS1 LVILS0 – – Initial value : 00H LVIF Low Voltage Indicator Flag Bit No detection Detection LVIEN LVI Enable/Disable Disable Enable LVILS[3:0] LVI Level Select...

  • Page 239: On-Chip Debug System

    14.1 Overview 14.1.1 Description On-chip debug system (OCD2) of MC97F2664 can be used for programming the non-volatile memories and on- chip debugging. Detail descriptions for programming via the OCD2 interface can be found in the following chapter. Figure 14.1 shows a block diagram of the OCD2 interface and the On-chip Debug system.

  • Page 240: Two-Pin External Interface

    MC97F2664 14.2 Two-Pin External Interface 14.2.1 Basic Transmission Packet • 10-bit packet transmission using two-pin interface. • 1-packet consists of 8-bit data, 1-bit parity and 1-bit acknowledge. • Parity is even of ‘1’ for 8-bit data in transmitter. • Receiver generates acknowledge bit as ‘0’ when transmission for 8-bit data and its parity has no error.

  • Page 241: Figure 14.3 Data Transfer On The Twin Bus

    MC97F2664 14.2.2 Packet Transmission Timing 14.2.2.1 Data Transfer DSDA acknowledgement acknowledgement signal from receiver signal from receiver DSCL START STOP Figure 14.3 Data Transfer on the Twin Bus 14.2.2.2 Bit Transfer DSDA DSCL data line change stable: of data data valid...

  • Page 242: Figure 14.5 Start And Stop Condition

    MC97F2664 14.2.2.3 Start and Stop Condition DSDA DSDA DSCL DSCL START condition STOP condition Figure 14.5 Start and Stop Condition 14.2.2.4 Acknowledge Bit Data output by transmitter no acknowledge Data output By receiver acknowledge DSCL from master clock pulse for acknowledgement Figure 14.6 Acknowledge on the Serial Bus...

  • Page 243: Figure 14.7 Clock Synchronization During Wait Procedure

    MC97F2664 Acknowledge bit Acknowledge bit transmission transmission Minimum wait HIGH start HIGH 500ns Host PC DSCL OUT Start wait Target Device DSCL OUT minimum 1 T SCLK for next byte Maximum 5 T SCLK transmission DSCL Internal Operation Figure 14.7 Clock Synchronization during Wait Procedure...

  • Page 244: Figure 14.8 Connection Of Transmission

    MC97F2664 14.2.3 Connection of Transmission Two-pin interface connection uses open-drain (wire-AND bidirectional I/O). pull resistors DSDA(Debugger Serial Data Line) DSCL(Debugger Serial Clock Line) RUNFLAG RUNFLAG DSCL DSDA RUNFLAG DSCL DSDA DSDA DSDA RUNFLAG DSCL RUNFLAG DSCL Target Device(Slave) Host Machine(Master) Current source for DSCL to fast 0 to 1 transition in high speed mode Figure 14.8 Connection of Transmission...

  • Page 245: Flash Memory

    15.1 Overview 15.1.1 Description MC97F2664 incorporates flash memory to which a program can be written, erased, and overwritten while mounted on the board. The flash memory can be read by ‘MOVC’ instruction and it can be programmed in OCD2, serial ISP mode or user program mode.

  • Page 246: Figure 15.1 Flash Program Rom Structure

    MC97F2664 15.1.2 Flash Program ROM Structure 0FFFFH Sector 1023 0FFC0H 0FFC0H 0FFBFH Sector 1022 0FF80H 0FF80H 0FF7FH Sector 1021 0FF40H 0FF40H 0FF3FH Sector 1020 Flash Sector Address Address Sector 2 00080H 00080H 0007FH Sector 1 00040H 00040H 0003FH Sector 0...

  • Page 247: Table 15-1 Flash Memory Register Map

    MC97F2664 15.1.3 Register Map Table 15-1 Flash Memory Register Map Name Address Default Description FSADRH Flash Sector Address High Register FSADRM Flash Sector Address Middle Register FSADRL Flash Sector Address Low Register FIDR Flash Identification Register FMCR Flash Mode Control Register 15.1.4 Register Description for Flash Memory Control and Status...
  • Page 248 MC97F2664 15.1.5 Register Description for Flash FSADRH (Flash Sector Address High Register) : FAH – – – – FSADRH3 FSADRH 2 FSADRH1 FSADRH0 – – – – Initial value : 00H FSADRH[3:0] Flash Sector Address High FSADRM (Flash Sector Address Middle Register) : FBH...
  • Page 249 MC97F2664 FMCR (Flash Mode Control Register) : FEH – – – – FMBUSY FMCR2 FMCR1 FMCR0 – – – – Initial value : 00H FMBUSY Flash Mode Busy Bit. This bit will be used for only debugger. No effect when “1” is written...
  • Page 250 15.1.7 Protection Area (User program mode) MC97F2664 can program its own flash memory (protection area). The protection area can not be erased or programmed. The protection areas are available only when the PAEN bit is cleared to ‘0’, that is, enable protection area at the configure option 2 if it is needed.
  • Page 251 MC97F2664 15.1.8 Erase Mode The sector erase program procedure in user program mode 1. Page buffer clear (FMCR=0x01) 2. Write ‘0’ to page buffer 3. Set flash sector address register (FSADRH/FSADRM/FSADRL). 4. Set flash identification register (FIDR). 5. Set flash mode control register (FMCR).
  • Page 252 MC97F2664 The Byte erase program procedure in user program mode 1. Page buffer clear (FMCR=0x01) 2. Write ‘0’ to page buffer 3. Set flash sector address register (FSADRH/FSADRM/FSADRL). 4. Set flash identification register (FIDR). 5. Set flash mode control register (FMCR).
  • Page 253 MC97F2664 15.1.9 Write Mode The sector Write program procedure in user program mode 1. Page buffer clear (FMCR=0x01) 2. Write data to page buffer 3. Set flash sector address register (FSADRH/FSADRM/FSADRL). 4. Set flash identification register (FIDR). 5. Set flash mode control register (FMCR).
  • Page 254 MC97F2664 The Byte Write program procedure in user program mode 1. Page buffer clear (FMCR=0x01) 2. Write data to page buffer 3. Set flash sector address register (FSADRH/FSADRM/FSADRL). 4. Set flash identification register (FIDR). 5. Set flash mode control register (FMCR).
  • Page 255 MC97F2664 15.1.10 Read Mode The Reading program procedure in user program mode 1. Load receive data from flash memory on MOVC instruction by indirectly addressing mode. Program Tip – reading A,#0 DPH,#0x7F DPL,#0x40 ;flash memory address MOVC A,@A+DPTR ;read data from flash memory 15.1.11 Hard Lock Mode...

  • Page 256: Configure Option

    MC97F2664 16. Configure Option 16.1 Configure Option Control The data for configure option should be written in the configure option area (003EH – 003FH) by programmer (Writer tools). CONFIGURE OPTION 1 : ROM Address 003FH – – – – VAPEN...

  • Page 257: Appendix

    MC97F2664 17. APPENDIX A. Instruction Table Instructions are either 1, 2 or 3 bytes long as listed in the ‘Bytes’ column below. Each instruction takes either 1, 2 or 4 machine cycles to execute as listed in the following table. 1 machine cycle comprises 2 system clock cycles.
  • Page 258 MC97F2664 XRL A, @Ri Exclusive-OR indirect memory to A 66-67 XRL A,#data Exclusive-OR immediate to A XRL dir,A Exclusive-OR A to direct byte XRL dir,#data Exclusive-OR immediate to direct byte CLR A Clear A CPL A Complement A SWAP A...
  • Page 259 MC97F2664 ANL C,bit AND direct bit to carry ANL C,/bit AND direct bit inverse to carry ORL C,bit OR direct bit to carry ORL C,/bit OR direct bit inverse to carry MOV C,bit Move direct bit to carry MOV bit,C...

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