Brk Interrupt; Multi Interrupt - Abov MC80F0304 User Manual

MC80F0304/08/16
Example: Register save using push and pop instructions
POP POP X Y ;RESTORE Y REG. ;RESTORE X REG.
INTxx: CLR1 INTxxIF ;CLEAR REQUEST. POP A ;RESTORE ACC.
PUSH PUSH X A ;SAVE X REG. ;SAVE ACC. RETI ;RETURN
PUSH Y ;SAVE Y REG. General-purpose register save/restore using push and pop instruc-
interrupt processing tions;

18.2 BRK Interrupt

the lowest priority order. Software interrupt can be invoked by BRK instruction, which has
TCALL 0 (Refer to Program Memory Section). When BRK inter- Interrupt vector address of BRK is shared with the vector of
rupt is generated, B-flag of PSW is set to distinguish BRK from B-FLAG =0
TCALL 0. BRK or =1
Each processing step is determined by B-flag as shown in Figure TCALL0 INTERRUPT BRK TCALL0 ROUTINE
18-5 . ROUTINE
RETI RET
Figure 18-5 Execution of BRK/TCALL0

18.3 Multi Interrupt

If two requests of different priority levels are received simulta- neously, the request of higher priority level is serviced. If re- ware which request is serviced. However, multiple processing through software for special features is possible. Generally when
quests of the interrupt are received at the same time an interrupt is accepted, the I-flag is cleared to disable any further
simultaneously, an internal polling sequence determines by hard- interrupt. But as user sets I-flag in interrupt routine, some further
98 November 4, 2011 Ver 2.12