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CMOS single-chip 8-bit MCU with 12-bit A/D converter and LCD driver MC96F6432S Main features User’s manual 8-bit Microcontroller With High Speed 8051 CPU Basic MCU Function V 1.9 – 32Kbytes Flash Code Memory – 1024bytes SRAM Built-in Analog Function ...
The information, diagrams and other data in this manual are correct and reliable; however, ABOV Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
MC96F6432S ABOV Semiconductor Co., Ltd. Overview 1.1. Description The MC96F6432S is an advanced CMOS 8-bit microcontroller with 32Kbytes of FLASH. This is powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. This offers the following features: 32Kbytes of FLASH, 256bytes of IRAM, 768bytes of XRAM, general purpose I/O, basic...
1.3.1 Compiler ABOV Semiconductor does not provide compiler. It is recommended that you consult a compier provider. The MC96F6432S core is Mentor 8051, and the ROM size is smaller than 64Kbytes.Therefore, developer can use the standard 8051 compiler from other providers.
MC96F6432S ABOV Semiconductor Co., Ltd. 1.3.3 Programmer Single programmer: E-PGM+ : It programs MCU device directly. Figure 1.2 E-PGM+(Single writer)
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MC96F6432S ABOV Semiconductor Co., Ltd. Gang programmer: E-GANG4 and E-GANG6 It can run PC controlled mode. It can run standalone without PC control too. USB interface is supported. Easy to connect to the handler. Figure 1.3 E-GANG4 and E-GANG6 (for Mass Production)
MC96F6432S ABOV Semiconductor Co., Ltd. MTP programming 1.4.1 Overview The program memory of MC96F6432S is MTP Type. This flash is accessed by serial data format. There are four pins(DSCL, DSDA, VDD, and VSS) for programming/reading the flash. During programming Main chip...
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MC96F6432S ABOV Semiconductor Co., Ltd. E-PGM+, E-GANG4/E-GANG6 R1 (2kΩ ~ 5kΩ) DSCL(I) To application circuit R2 (2kΩ ~ 5kΩ) DSDA(I/O) To application circuit NOTE) In on-board programming mode, very high-speed signal will be provided to pin DSCL and DSDA. And it will cause some damages to the application circuits connected to DSCL or DSDA port if the application circuit is designed as high speed response such as relay control circuit.
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MC96F6432S ABOV Semiconductor Co., Ltd. P53/SXIN/T0O/PWM0O P03/SEG26/AN1/EINT1/PWM4AB P54/SXOUT/EINT10 P04/SEG25/AN2/EINT2/PWM4BA P55/RESETB P05/SEG24/AN3/EINT3/PWM4BB P40/VLC3/RXD0/SCL0/MISO0 P06/SEG23/AN4/EINT4/PWM4CA MC96F6332L P41/VLC2/TXD0/SDA0/MOSI0 P07/SEG22/AN5/EINT5/PWM4CB (32-LQFP) P42/VLC1/SCK0 P13/SEG17/AN10/EC1/BUZO P33/COM4/SEG2 P12/SEG16/AN11/EINT11/T1O/PWM1O P32/COM5/SEG3 P11/SEG15/AN12/EINT12/T2O/PWM2O NOTE) The programmer (E-PGM+, E-Gang4/E-Gang6) uses P0[1:0] pin as DSCL, DSDA. The P14-P17, P23-P25, P34-P37 and P43 pins should be selected as a push-pull output or an input with pull-up resistor by software control when the 32-pin package is used.
MC96F6432S ABOV Semiconductor Co., Ltd. Pin Description Function @RESET Shared with Name Port 0 is a bit-programmable I/O port which can be EC3/DSDA configured as a Schmitt-trigger input, a push-pull T3O/DSCL output, or an open-drain output. A pull-up resistor can be specified in 1-bit unit.
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MC96F6432S ABOV Semiconductor Co., Ltd. Function @RESET Shared with Name Port 5 is a bit-programmable I/O port which can be XOUT configured as a Schmitt-trigger input or a push-pull output. A pull-up resistor can be specified in 1-bit unit. EINT8/EC0/BLNK...
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MC96F6432S ABOV Semiconductor Co., Ltd. Function @RESET Shared with Name BUZO Buzzer signal output Input P13/SEG17/AN10/EC1 SCK0 Serial 0 clock input/output Input P42/VLC1 SCK1 Serial 1 clock input/output Input P21/SEG12/AN15 SCK2 Serial 2 clock input/output Input P16/SEG20/AN7/EINT7 MOSI0 SPI 0 master output, slave input...
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MC96F6432S ABOV Semiconductor Co., Ltd. PIN Name Function @RESET Shared with VLC0 P43/SS0 VLC1 P42/SCK0 LCD bias voltage pins Input VLC2 P41/TXD0/SDA0/MOSI0 VLC3 P40/RXD0/SCL0/MISO0 COM0 P37–P36 COM1 COM2– LCD common signal outputs Input P35–P34/SEG0–SEG1 COM3 COM4– P33–P30/SEG2–SEG5 COM7 SEG0– P35–P34/COM2–COM3 SEG1 SEG2–...
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MC96F6432S ABOV Semiconductor Co., Ltd. Function @RESET Shared with Name System reset pin with a pull-up resistor when it is RESETB Input selected as the RESETB by CONFIGURE OPTION DSDA In-system programming data input/output Input P00/EC3 DSCL In-system programming clock input...
MC96F6432S ABOV Semiconductor Co., Ltd. Port Structures General Purpose I/O Port Level Shift (1.8V to ExtVDD) Level Shift (ExtVDD to 1.8V) PULL-UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE SUB-FUNC DIRECTION DIRECTION REGISTER CMOS or Schmitt Level...
MC96F6432S ABOV Semiconductor Co., Ltd. External Interrupt I/O Port Level Shift (1.8V to ExtVDD) Level Shift (ExtVDD to 1.8V) PULL-UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE SUB-FUNC DIRECTION DIRECTION REGISTER EXTERNAL INTERRUPT POLARITY REG. INTERRUPT...
MC96F6432S ABOV Semiconductor Co., Ltd. Electrical Characteristics Absolute Maximum Ratings Parameter Symbol Rating Unit Note – Supply Voltage -0.3~+6.5 -0.3~VDD+0.3 Voltage on any pin with respect to VSS -0.3~VDD+0.3 Maximum current output sourced by (I per I/O pin) Normal Voltage Pin ∑...
MC96F6432S ABOV Semiconductor Co., Ltd. DC Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V, f = 12MHz) Parameter Symbol Conditions Unit – P0, P1,P5, RESETB 0.8VDD Input High Voltage – All input pins except V 0.7VDD –...
MC96F6432S ABOV Semiconductor Co., Ltd. 7.12 UART0/1 Characteristics =-40°C ~ +85°C, VDD=1.8V ~ 5.5V, f =11.1MHz) Parameter Symbol Unit Serial port clock cycle time 1250 x 16 1650 – Output data setup to clock rising edge x 13 – –...
MC96F6432S ABOV Semiconductor Co., Ltd. 7.14 Data Retention Voltage in Stop Mode =-40°C ~ +85°C, VDD=1.8V ~ 5.5V) Parameter Symbol Conditions Unit – – Data retention supply voltage DDDR VDDR= 1.8V, – – Data retention supply current = 25°C), DDDR...
MC96F6432S ABOV Semiconductor Co., Ltd. 7.21 Operating Voltage Range =0.4 to 12MHz) =32 to 38kHz) 12.0MHz 32.768kHz 10.0MHz 4.2MHz 0.4MHz Supply voltage (V) Supply voltage (V) Figure 7.14 Operating Voltage Range...
MC96F6432S ABOV Semiconductor Co., Ltd. 7.22 Recommended Circuit and Layout This 0.1uF capacitor should be within 1cm from the VDD pin of MCU on the PCB layout. DC Power 0.1uF 0.1uF The MCU power line (VDD and VSS) should be separated from the high-...
MC96F6432S ABOV Semiconductor Co., Ltd. 7.23 Recommended Circuit and Layout with SMPS Power SMPS Side MCU Side SMPS 1. The C1 capacitor is to flatten out the voltage of the SMPS power, VCC. √ Recommended C1: 470uF/25V more. 2. The R1 and C2 are the RC filter for VDD and suppress the ripple of VCC.
MC96F6432S ABOV Semiconductor Co., Ltd. 7.24 Typical Characteristics These graphs and tables provided in this section are only for design guidance and are not tested or guaranteed. In graphs or tables some data are out of specified operating range (e.g. out of specified VDD range). This is only for information and devices are guaranteed to operate properly only within the specified range.
MC96F6432S ABOV Semiconductor Co., Ltd. Memory The MC96F6432S addresses two separate address memory stores:Program memory and Data memory. The logical separation of Program and Data memory allows Data memory to be accessed by 8-bit addresses, which makes the 8- bit CPU access the data memory more rapidly. Nevertheless, 16-bit Data memory addresses can also be generated through the DPTR register.
MC96F6432S ABOV Semiconductor Co., Ltd. Data Memory Upper 128bytes Special Function Registers Internal RAM 128bytes (Indirect Addressing) (Direct Addressing) Lower 128bytes Internal RAM (Direct or Indirect Addressing) Figure 8.2 Data Memory Map The internal data memory space is divided into three blocks, which are generally referred to as the lower 128bytes, upper 128bytes, and SFR space.
MC96F6432S ABOV Semiconductor Co., Ltd. External Data Memory MC96F6432S has 768bytes XRAM and XSFR. This area has no relation with RAM/FLASH. It can be read and written to through SFR with 8-bit unit. 107FH Extended Special Function Registers 128bytes (Indirect Addressing)
MC96F6432S ABOV Semiconductor Co., Ltd. 8.4.2 SFR Map @Reset Address Function Symbol P0 Data Register Stack Pointer Data Pointer Register Low Data Pointer Register High Data Pointer Register Low 1 DPL1 Data Pointer Register High 1 DPH1 – – Low Voltage Indicator Control Register LVICR –...
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MC96F6432S ABOV Semiconductor Co., Ltd. @Reset Address Function Symbol External Interrupt Flag 0 Register EIFLAG0 P3 Direction Register P3IO – – Timer 2 Control Low Register T2CRL – – – – Timer 2 Control High Register T2CRH Timer 2 A Data Low Register...
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MC96F6432S ABOV Semiconductor Co., Ltd. @Reset Address Function Symbol Accumulator Register – USI0 Status Register 1 USI0ST1 USI0 Status Register 2 USI0ST2 USI0 Baud Rate Generation Register USI0BD USI0 SDA Hold Time Register USI0SHDR USI0 Data Register USI0DR USI0 SCL Low Period Register...
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MC96F6432S ABOV Semiconductor Co., Ltd. @Reset Address Function Symbol – 1000H Timer 3 Control Register T3CR Timer 3 Counter Register T3CNT 1001H Timer 3 Data Register T3DR Timer 3 Capture Data Register T3CAPR 1002H Timer 4 Control Register T4CR 1003H...
MC96F6432S ABOV Semiconductor Co., Ltd. I/O Ports I/O Ports The MC96F6432S has tengroups of I/O ports (P0 ~ P5). Each port can be easily configured by software as I/O pin, internal pull up and open-drain pin to meet various system configurations and design requirements. Also P0 includes function that can generate interrupt according to change of state of the pin.
MC96F6432S ABOV Semiconductor Co., Ltd. 9.2.6 Port Function Selection Register (PxFSR) These registers define alternative functions of ports. Please remember that these registers should be set properly for alternative port function. A reset clears the PxFSR register to ‘00H’, which makes all pins to normal I/O ports.
MC96F6432S ABOV Semiconductor Co., Ltd. P1 Port 9.4.1 P1 Port Description P1 is 8-bit I/O port. P1 control registers consist of P1 data register (P1), P1 direction register (P1IO), debounce enable register (P15DB), P1 pull-up resistor selection register (P1PU), andP1 open-drain selection register (P1OD) . Refer to the port function selection registers for the P1 function selection.
MC96F6432S ABOV Semiconductor Co., Ltd. P2 Port 9.5.1 P2 Port Description P2 is 8-bit I/O port. P2 control registers consist of P2 data register (P2), P2 direction register (P2IO), P2 pull-up resistor selection register (P2PU) andP2 open-drain selection register (P2OD).Refer to the port function selection registers for the P2 function selection.
MC96F6432S ABOV Semiconductor Co., Ltd. P3 Port 9.6.1 P3 Port Description P3 is 8-bit I/O port. P3 control registers consist of P3 data register (P3), P3 direction register (P3IO) and P3 pull-up resistor selection register (P3PU). Refer to the port function selection registers for the P3 function selection.
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MC96F6432S ABOV Semiconductor Co., Ltd. P3FSR (Port 3 Function Selection Register): EEH P3FSR7 P3FSR6 P3FSR5 P3FSR4 P3FSR3 P3FSR2 P3FSR1 P3FSR0 Initial value: 00H P3FSR7 P37 Function select I/O Port COM0 Function P3FSR6 P36 Function Select I/O Port COM1 Function P3FSR5...
MC96F6432S ABOV Semiconductor Co., Ltd. P4 Port 9.7.1 P4 Port Description P4 is 4-bit I/O port. P4 control registers consist of P4 data register (P4), P4 direction register (P4IO), P4 pull-up resistor selection register (P4PU) andP4 open-drain selection register (P4OD).Refer to the port function selection registers for the P4 function selection.
MC96F6432S ABOV Semiconductor Co., Ltd. P5 Port 9.8.1 P5 Port Description P5 is 6-bit I/O port. P5 control registers consist of P5 data register (P5), P5 direction register (P5IO) andP5 pull-up resistor selection register (P5PU) . Refer to the port function selection registers for the P5 function selection.
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MC96F6432S ABOV Semiconductor Co., Ltd. P5FSR (Port 5 Function Selection Register): FFH – – P5FSR5 P5FSR4 P5FSR3 P5FSR2 P5FSR1 P5FSR0 – – Initial value: 00H P5FSR5 P54 Function Select I/O Port(EINT10 function possible when input) SXOUT Function P5FSR[4:3] P53 Function Select...
MC96F6432S ABOV Semiconductor Co., Ltd. Interrupt Controller 10.1 Overview The MC96F6432S supports up to 23 interrupt sources. The interrupts have separate enable register bits associated with them, allowing software control. They can also have four levels of priority assigned to them. The non-maskable interrupt source is always enabled with a higher priority than any other interrupt source, and is not controllable by software.
MC96F6432S ABOV Semiconductor Co., Ltd. 10.4 Interrupt Vector Table The interrupt controller supports 24 interrupt sources as shown in the Table 10-2. When interrupt is served, long call instruction (LCALL) is executed and program counter jumps to the vector address. All interrupt requests have their own priority order.
MC96F6432S ABOV Semiconductor Co., Ltd. 10.5 Interrupt Sequence An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to ‘0’ by a reset or an instruction. Interrupt acceptance always generates at last cycle of the instruction. So instead of fetching the current instruction, CPU executes internally LCALL instruction and saves the PC at stack.
MC96F6432S ABOV Semiconductor Co., Ltd. 10.6 Effective Timing after Controlling Interrupt Bit Case a) Control Interrupt Enable Register (IE, IE1, IE2, IE3) Interrupt Enable Register command After executing IE set/clear, enable register is effective. Next Instruction Next Instruction Figure 10.4...
MC96F6432S ABOV Semiconductor Co., Ltd. 10.7 Multi Interrupt If two requests of different priority levels are received simultaneously, the request of higher priority level is served first. If more than one interrupt request are received, the interrupt polling sequence determines which request is served first by hardware.
MC96F6432S ABOV Semiconductor Co., Ltd. 10.12.3 External Interrupt Flag Register (EIFLAG0, EIFLAG1) The external interrupt flag 0 register (EIFLAG0) and external interrupt flag 1 register (EIFLAG1) areset to ‘1’ when the external interrupt generating condition is satisfied. The flag is cleared when the interrupt service routine is executed.
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MC96F6432S ABOV Semiconductor Co., Ltd. EIFLAG0 (External Interrupt Flag0 Register): C0H FLAG7 FLAG6 FLAG5 FLAG4 FLAG3 FLAG2 FLAG1 FLAG0 Initial value :00H When an External Interrupt 0-7 is occurred, the flag becomes ‘1’.The flag is cleared EIFLAG0[7:0] only by writing ‘0’ to the bit. So, the flag should be cleared by software.
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MC96F6432S ABOV Semiconductor Co., Ltd. EIFLAG1 (External Interrupt Flag 1 Register): A6H – T0OVIFR T0IFR T3IFR FLAG12 FLAG11 FLAG10 FLAG8 – Initial value :00H When T0 overflow interrupt occurs, this bit becomes ‘1’. For clearing bit, write‘0’ to T0OVIFR this bit or automatically clear by INT_ACK signal. Writing “1” has no effect.
MC96F6432S ABOV Semiconductor Co., Ltd. Peripheral Hardware 11.1 Clock Generator 11.1.1 Overview As shown in Figure 11.1, the clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and the peripheral hardware. It contains main/sub-frequency clock oscillator. The main/sub clock operation can be easily obtained by attaching a crystal between the XIN/SXIN and XOUT/SXOUT pin, respectively.
MC96F6432S ABOV Semiconductor Co., Ltd. 11.1.3 Register Map Name Address Direction Default Description SCCR System and Clock Control Register OSCCR Oscillator Control Register Clock Generator Register Map Table 11.1 11.1.4 Clock Generator Register Description The clock generatorregister uses clock control for system operation. The clock generation consists of System and clock control register and oscillator control register.
MC96F6432S ABOV Semiconductor Co., Ltd. 11.2 Basic Interval Timer 11.2.1 Overview The MC96F6432S has one 8-bit basic interval timer that is free-run and can’t stop. Block diagram is shown in Figure 11.2. In addition, the basic interval timer generates the time base for watchdog timer counting. It also provides a basic interval timer interrupt (BITIFR).
MC96F6432S ABOV Semiconductor Co., Ltd. 11.2.4 Basic Interval Timer Register Description The basicinterval timer register consists of basic interval timer counter register (BITCNT) and basic interval timer control register (BITCR). If BCLR bit is set to ‘1’, BITCNT becomes ‘0’ and then counts up. After 1 machine cycle, BCLR bit is cleared to ‘0’...
MC96F6432S ABOV Semiconductor Co., Ltd. 11.3 Watch Dog Timer 11.3.1 Overview The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or something like that, and resumes the CPU to the normal state. The watchdog timer signal for malfunction detection can be used as either a CPUreset or an interrupt request.
MC96F6432S ABOV Semiconductor Co., Ltd. 11.4 Watch Timer 11.4.1 Overview The watch timer has the function for RTC (Real Time Clock) operation.It is generally used for RTC design.The internal structure of the watch timer consists of the clock source select circuit, timer counter circuit, output select circuit, and watch timer control register.
MC96F6432S ABOV Semiconductor Co., Ltd. 11.4.3 Register Map Name Address Direction Default Description WTCNT Watch Timer Counter Register WTDR Watch Timer Data Register WTCR Watch Timer Control Register Watch Timer Register Map Table 11.4 11.4.4 Watch Timer Register Description The watch timer register consists of watch timer counter register (WTCNT), watch timer data register (WTDR), and watch timer controlregister (WTCR).
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MC96F6432S ABOV Semiconductor Co., Ltd. WTCR (Watch Timer Control Register): 96H – – WTEN WTIFR WTIN1 WTIN0 WTCK1 WTCK0 – – Initial value: 00H WTEN Control Watch Timer Disable Enable When WT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or WTIFR automatically clear by INT_ACK signal.
MC96F6432S ABOV Semiconductor Co., Ltd. 11.5 Timer 0 11.5.1 Overview The 8-bit timer 0 consists of multiplexer, timer 0 counter register, timer 0 data register, timer 0 capture data register and timer 0 control register (T0CNT, T0DR, T0CDR, T0CR). It has three operating modes: −...
MC96F6432S ABOV Semiconductor Co., Ltd. 11.5.2 8-bit Timer/Counter Mode The 8-bit timer/counter mode is selected by control register as shown in Figure 11.6. The 8-bit timer have counter and data register. The counter register is increased by internal or external clock input.
MC96F6432S ABOV Semiconductor Co., Ltd. 11.5.3 8-bit PWM Mode The timer 0 has a high speed PWM (Pulse Width Modulation) function. In PWM mode, T0O/PWM0O pin outputs up to 8-bit resolution PWM output. This pin should be configured as a PWM output by setting the T0O/PWM0O function by P5FSR[4:3] bits.
MC96F6432S ABOV Semiconductor Co., Ltd. 11.5.4 8-bit Capture Mode The timer 0 capture mode is set by T0MS[1:0] as ‘1x’. The clock source can use the internal/external clock. Basically, it has the same function as the 8-bit timer/counter mode and the interrupt occurs when T0CNT is equal to T0DR.
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MC96F6432S ABOV Semiconductor Co., Ltd. T0CDR Load T0CNT Value Count Pulse Period Up-count TIME Ext. EINT10 PIN Interrupt Request (FLAG10) Interrupt Interval Period Figure 11.11 Input Capture Mode Operation for Timer 0 T0CNT Interrupt Request (T0IFR) Ext. EINT10 PIN Interrupt...
MC96F6432S ABOV Semiconductor Co., Ltd. 11.6 Timer 1 11.6.1 Overview The 16-bit timer 1 consists of multiplexer, timer 1 A data register high/low, timer 1 B data register high/low and timer 1 control registerhigh/low (T1ADRH, T1ADRL, T1BDRH, T1BDRL, T1CRH, T1CRL).
MC96F6432S ABOV Semiconductor Co., Ltd. 11.6.3 16-bit Capture Mode The 16-bit timer 1 capture mode is set by T1MS[1:0] as ‘01’. The clock source can use the internal/external clock. Basically, it has the same function as the 16-bit timer/counter mode and the interrupt occurs when T1CNTH/T1CNTL is equal to T1ADRH/T1ADRL.
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MC96F6432S ABOV Semiconductor Co., Ltd. T1BDRH/L Load T1CNTH/L Value Count Pulse Period Up-count TIME Ext. EINT11 PIN Interrupt Request (FLAG11) Interrupt Interval Period Figure 11.17 Input Capture Mode Operation for Timer 1 FFFF FFFF T1CNTH/L Interrupt Request (T1IFR) Ext. EINT11 PIN...
MC96F6432S ABOV Semiconductor Co., Ltd. 11.6.4 16-bit PPG Mode The timer 1 has a PPG (Programmable Pulse Generation) function. In PPG mode, T1O/PWM1O pin outputs up to 16-bit resolution PWM output. This pin should be configured as a PWM output by settingP1FSRL[5:4] to ‘11’. The period of the PWM output is determined by the T1ADRH/T1ADRL.
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MC96F6432S ABOV Semiconductor Co., Ltd. Repeat Mode(T1MS = 11b) and "Start High"(T1POL = 0b). Clear and Start Set T1EN Timer 1 clock Counter T1ADRH/L T1 Interrupt 1. T1BDRH/L(5) < T1ADRH/L PWM1O B Match A Match 2. T1BDRH/L >= T1ADRH/L PWM1O A Match 3.
MC96F6432S ABOV Semiconductor Co., Ltd. 11.6.5 Block Diagram 16-bit A Data Register T1ADRH/T1ADRL A Match Reload T1CC T1EN To Timer 2 T1CK[2:0] block T1ECE INT_ACK Buffer Register A Clear Edge A Match Detector To interrupt T1IFR block T1EN fx/1 Comparator...
MC96F6432S ABOV Semiconductor Co., Ltd. 11.7 Timer 2 11.7.1 Overview The 16-bit timer 2 consists of multiplexer, timer 2 A data high/low register, timer 2 B data high/low register and timer 2 control high/low register (T2ADRH, T2ADRL, T2BDRH, T2BDRL, T2CRH, and T2CRL).
MC96F6432S ABOV Semiconductor Co., Ltd. 11.7.2 16-bit Timer/Counter Mode The 16-bit timer/counter mode is selected by control register as shown in Figure 11.22. The 16-bit timer have counter and data register. The counter register is increased by internal or timer 1 A match clock input.
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MC96F6432S ABOV Semiconductor Co., Ltd. Match with T2ADRH/L T2CNTH/L Value Count Pulse Period Up-count TIME Interrupt Period x (n+1) Timer 2 (T2IFR) Interrupt Occur Occur Occur Interrupt Interrupt Interrupt Figure 11.23 16-bit Timer/Counter 2 Example...
MC96F6432S ABOV Semiconductor Co., Ltd. 11.7.3 16-bit Capture Mode The timer 2 capture mode is set by T2MS[1:0] as ‘01’. The clock source can use the internal clock. Basically, it has the same function as the 16-bit timer/counter mode and the interrupt occurs when T2CNTH/T2CNTLis equal to T2ADRH/T2ADRL.
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MC96F6432S ABOV Semiconductor Co., Ltd. T2BDRH/L Load T2CNTH/L Value Count Pulse Period Up-count TIME Ext. EINT12 PIN Interrupt Request (FLAG12) Interrupt Interval Period Figure 11.25 Input Capture Mode Operation for Timer 2 FFFF FFFF T2CNTH/L Interrupt Request (T2IFR) Ext. EINT12 PIN...
MC96F6432S ABOV Semiconductor Co., Ltd. 11.7.4 16-bit PPG Mode The timer 2 has a PPG (Programmable Pulse Generation) function. In PPG mode, the T2O/PWM2O pin outputs up to 16-bit resolution PWM output. This pin should be configured as a PWM output by set P1FSRL[3:2] to ‘11’. The period of the PWM output is determined by the T2ADRH/T2ADRL.
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MC96F6432S ABOV Semiconductor Co., Ltd. Repeat Mode(T2MS = 11b) and "Start High"(T2POL = 0b). Clear and Start Set T2EN Timer 2 clock Counter T2ADRH/L T2 Interrupt 1. T2BDRH/L(5) < T2ADRH/L PWM2O B Match A Match 2. T2BDRH/L >= T2ADRH/L PWM2O A Match 3.
MC96F6432S ABOV Semiconductor Co., Ltd. 11.7.5 Block Diagram 16-bit A Data Register T2ADRH/T2ADRL A Match Reload T2CC T2CK[2:0] T2EN INT_ACK Buffer Register A Clear T1 A Match A Match To interrupt T2IFR block T2EN fx/1 Comparator fx/2 A Match Clear...
MC96F6432S ABOV Semiconductor Co., Ltd. 11.7.7 Timer/Counter 2 Register Description The timer/counter 2 register consists of timer 2 A data high register (T2ADRH), timer 2 A data low register (T2ADRL), timer 2 B data high register (T2BDRH), timer 2 B data low register (T2BDRL), timer 2 control high register (T2CRH) and timer 2 control low register (T2CRL).
MC96F6432S ABOV Semiconductor Co., Ltd. 11.8 Timer 3, 4 11.8.1 Overview Timer 3 and timer 4 can be used either two 8-bit timer/counter or one 16-bit timer/counter with combine them.Each 8- bit timer/event counter module has multiplexer, comparator, 8-bit timer data register, 8-bit counter register, control register and capture data register(T3CNT, T3DR, T3CAPR, T3CR, T4CNT, T4DR, T4CAPR, and T4CR).
MC96F6432S ABOV Semiconductor Co., Ltd. 11.8.2 8-bit Timer/Counter 3, 4 Mode The 8-bit timer/counter mode is selected by control register as shown in Figure 11.30. The two 8-bit timers have each counter and data register. The counter register is increased by internal or external clock input.Timer 3 can use the input clock with one of 2, 4, 8, 32, 128, 512, 2048 and EC3prescaler division rates...
MC96F6432S ABOV Semiconductor Co., Ltd. 11.8.3 16-bit Timer/Counter 3 Mode The 16-bit timer/counter mode is selected by control register as shown in Figure 11.31. The 16-bit timer have counter and data register. The counter register is increased by internal or external clock input.
MC96F6432S ABOV Semiconductor Co., Ltd. 11.8.4 8-bit Timer 3, 4 Capture Mode The 8-bit Capture 3 and 4 mode is selected by control register as shown in Figure 11.32. The timer 3, 4 capture mode is set by T3MS, T4MS as ‘1’. The clock source can use the internal/external clock.
MC96F6432S ABOV Semiconductor Co., Ltd. 11.8.5 16-bit Timer 3 Capture Mode The 16-bit Capture mode is selected by control register as shown in Figure 11.33. The 16-bit capture mode is the same operation as 8-bit capture mode, except that the timer register uses 16 bits. The 16-bit timer 3 capture mode is set by T3MS, T4MS as ‘1’.
MC96F6432S ABOV Semiconductor Co., Ltd. 11.8.6 10-bit Timer 4 PWM Mode The timer 4 has a high speed PWM (Pulse Width Modulation) function. In PWM mode, the 6-channel pins output up to 10-bit resolution PWM output. This pin should be configured as a PWM output by set PWM4E to ‘1’. When the value of 2-bit +T4CNT and T4PPRH/L are identical in timer 4, a period match signal is generated and the interrupt of timer 4 occurs.
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MC96F6432S ABOV Semiconductor Co., Ltd. Phase correction & Frequency correction On operating PWM, it is possible that it is changed the phase and the frequency by using BMOD bit (back-to-back mode) in T4PCR1 register. (Figure 1.38, Figure 11.39, Figure 11.40 referred) In the back-to-back mode, the counter of PWM repeats up/down count.
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MC96F6432S ABOV Semiconductor Co., Ltd. Duty, Period Update T4CNT Back-to-Back mode Duty1 Duty2 Duty3 Output Period1 Period2 Period3 Interrupt Timing Overflow INT. Overflow INT. Bottom INT. Overflow INT. Figure 11.40 Example of Phase Correction and Frequency correction of PWM External Sync If using ESYNC bit of T4PCR1 register, it is possible to synchronize the output of PWM from external signal.
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MC96F6432S ABOV Semiconductor Co., Ltd. FORCE Drive ALL Channel with A-ch mode If FORCA bit sets to ‘1’, it is possible to enable or disable all PWM output pins through PWM outputs which occur from A-ch duty counter. It is noted that the inversion outputs of A, B, C channel have the same A-ch output waveform.
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MC96F6432S ABOV Semiconductor Co., Ltd. FORCE 6-Ch Drive If FORCA bit sets to ‘0’, it is possible to enable or disable PWM output pin and inversion output pin generated through the duty counter of each channel. The inversion output is the reverse phase of the PWM output. A AA/AB output of the A-channel duty register, a BA/BB output of the B-channel duty register, a CA/CB output of the C-channel duty register are controlled respectively.
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MC96F6432S ABOV Semiconductor Co., Ltd. PWM output Delay If using the T4DLYA, T4DLYB, and T4DLYC register, it can delay PWM output based on the rising edge. At that time, it does not change the falling edge, so the duty is reduced as the time delay. In POLAA/BA/CA setting to ‘0’, the delay is applied to the falling edge.
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MC96F6432S ABOV Semiconductor Co., Ltd. T4PCR1 (Timer 4PWM Control Register 1): 1003H (ESFR) PWM4E ESYNC BMOD PHLT UPDT UALL NOPS1 NOPS0 Initial value: 00H PWM4E Control Timer 4 Mode Select timer/counter or capture mode of Timer 4 Select 10-bit PWM mode of Timer 4...
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MC96F6432S ABOV Semiconductor Co., Ltd. T4PCR2 (Timer 4PWM Control Register 2): 1004H (ESFR) – FORCA PAAOE PABOE PBAOE PBBOE PCAOE PCBOE – Initial value: 00H FORCA Control The PWM outputs Mode 6-channel mode (The PWM4xA/PWM4xB pins are output according to the T4xDR registers, respectively.
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MC96F6432S ABOV Semiconductor Co., Ltd. T4PCR3 (Timer 4PWM Control Register 3): 1005H (ESFR) HZCLR POLBO POLAA POLAB POLBA POLBB POLCA POLCB Initial value: 00H HZCLR High-Impedance Output Clear Bit No effect Clear high-impedance output (The PWM4xA/PWM4xB pins are back to output and this bit is automatically cleared to logic ‘0’.
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MC96F6432S ABOV Semiconductor Co., Ltd. T4ISR (Timer 4 Interrupt Status Register): 1006H (ESFR) – – – IOVR IBTM ICMA ICMB ICMC – – – Initial value: 00H IOVR Timer 4 Compare Match or Timer 4 Overflow Interrupt Status, Write '0' to this bit for...
MC96F6432S ABOV Semiconductor Co., Ltd. 11.9 Buzzer Driver 11.9.1 Overview The Buzzer consists of 8bit counter,buzzer data register (BUZDR), and buzzer control register (BUZCR). The Square Wave (61.035Hz~125.0kHz @8MHz)is outputted through P13/SEG17/AN10/EC1/BUZO pin. The buzzer dataregister (BUZDR) controls the buzzer frequency (lookat the following expression). In buzzer control register(BUZCR), BUCK[1:0] selects source clock divided by prescaler.
MC96F6432S ABOV Semiconductor Co., Ltd. 11.10 SPI 2 11.10.1 Overview There is serial peripheral interface (SPI 2) one channel in MC96F6432S. The SPI 2 allows synchronous serial data transfer between the external serial devices. It can do Full-duplex communication by 4-wire (MOSI2, MISO2, SCK2, SS2), support master/slave mode, can select serial clock (SCK2) polarity, phase and whether LSB first data transfer or MSB first data transfer.
MC96F6432S ABOV Semiconductor Co., Ltd. 11.10.3 Data Transmit / Receive Operation User can use SPI 2 for serial data communication by following step 1. Select SPI 2 operation mode(master/slave, polarity, phase) by control register SPICR. 2. When the SPI 2 is configured as a Master, it selects a Slave by SS2 signal (active low).
MC96F6432S ABOV Semiconductor Co., Ltd. 11.10.6 Register Map Name Address Direction Default Description SPISR SPI 2 Status Register SPIDR SPI 2 Data Register SPICR SPI 2 Control Register SPI 2Register Map Table 11.17 11.10.7 SPI 2 Register Description The SPI 2 register consists of SPI 2 control register (SPICR), SPI 2 status register (SPISR) and SPI 2 data register (SPIDR) 11.10.8 Register Description for SPI 2...
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MC96F6432S ABOV Semiconductor Co., Ltd. SPISR (SPI 2 Status Register): B7H – – – SPIIFR WCOL SS_HIGH FXCH SSENA – – – Initial value: 00H When SPI 2 Interrupt occurs, this bit becomes ‘1’. IF SPI 2 interrupt is enable, this bit is SPIIFR auto cleared by INT_ACK signal.
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MC96F6432S ABOV Semiconductor Co., Ltd. SPICR (SPI 2Control Register): B5H SPIEN FLSB CPOL CPHA DSCR SCR1 SCR0 Initial value: 00H SPIEN This bit controls the SPI 2 operation Disable SPI 2 operation Enable SPI 2 operation FLSB This bit selects the data transmission sequence...
MC96F6432S ABOV Semiconductor Co., Ltd. 11.11 12-bit A/D Converter 11.11.1 Overview The analog-to-digital converter (A/D) allows conversion of an analog input signal to corresponding 12-bit digital value. The A/D module has eight analog inputs.The output of the multiplexeris the input into the converter which generates the result through successive approximation.
MC96F6432S ABOV Semiconductor Co., Ltd. 11.11.3 Block Diagram TRIG[2:0] ADST T1 A match signal T4 overflow event signal T4 A match event signal ADSEL[3:0] Start T4 B match event signal (Select one input pin T4 C match event signal of the assigned pins)
MC96F6432S ABOV Semiconductor Co., Ltd. SET ADCCRH Select ADC Clock and Data Align Bit. SET ADCCRL ADC enable & Select AN Input Channel. Converting START Start ADC Conversion. If Conversion is completed, AFLAG is set “1” and ADC AFLAG = 1? interrupt is occurred.
MC96F6432S ABOV Semiconductor Co., Ltd. 11.12 USI (USART + SPI + I2C) 11.12.1 Overview The USI is an acronym of USART, SPI and I2C, MC96F6432S has two USI function blocks, USI0 and USI1 are absolutely same functionally. Each USI consists of USI control register1/2/3/4, USI status register 1/2, USI baud-rate...
MC96F6432S ABOV Semiconductor Co., Ltd. 11.12.2 USIn UART Mode The universal synchronous and asynchronous serial receiver and transmitter (USART) is a highly flexible serial communication device. The main features are listed below. − Full Duplex Operation (Independent Serial Receive and Transmit Registers) −...
MC96F6432S ABOV Semiconductor Co., Ltd. 11.12.5 USIn External Clock (SCKn) External clocking is used in the synchronous mode of operation. External clock input from the SCKn pin is sampled by a synchronization logic to remove meta-stability. The output from the synchronization logic must be passed through an edge detector before it is used by the transmitter and receiver.
MC96F6432S ABOV Semiconductor Co., Ltd. 11.12.7 USIn UART Data format A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error detection. The USARTsupports all 30 combinations of the following as valid frame formats.
MC96F6432S ABOV Semiconductor Co., Ltd. 11.12.8 USIn UART Parity bit The parity bit is calculated by doing an exclusive-OR of all the data bits. If odd parity is used, the result of the exclusive-OR is inverted. The parity bit is located between the MSB and first stop bit of a serial frame.
MC96F6432S ABOV Semiconductor Co., Ltd. USIn UART Parity Generator 11.12.9.3 The parity generator calculates the parity bit for the serial frame data to be sent. When parity bit is enabled (USInPM1=1), the transmitter control logic inserts the parity bit between the MSB and the first stop bit of the frame to be sent.
MC96F6432S ABOV Semiconductor Co., Ltd. USIn UART Receiver Flag and Interrupt 11.12.10.2 The UARTreceiver has one flag that indicates the receiver state. The receive complete (RXCn)flag indicates whether there are unread data in the receive buffer. This flag is set when there is unread data in the receive buffer and cleared when the receive buffer is empty.If the receiver is disabled...
MC96F6432S ABOV Semiconductor Co., Ltd. USIn Asynchronous Data Reception 11.12.10.5 To receive asynchronous data frame, the UART includes a clock and data recovery unit. Theclock recovery logic is used for synchronizing the internally generated baud-rate clock to the incoming asynchronous serial frame on the RXDn pin.
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MC96F6432S ABOV Semiconductor Co., Ltd. When the receiver is enabled (RXEn=1), the clock recovery logic tries to find a high-to-low transition on the RXDn line, the start bit condition. After detecting high to low transition on RXDn line, the clock recovery logic uses samples 8, 9 and 10 for normal mode to decide if a valid start bit is received.
MC96F6432S ABOV Semiconductor Co., Ltd. 11.12.11 USIn SPI Mode The USIn can be set to operate in industrial standard SPI compliant mode. The SPI mode has the following features. − Full Duplex, Three-wire synchronous data transfer − Mater and Slave Operation −...
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MC96F6432S ABOV Semiconductor Co., Ltd. SCKn (CPOLn=0) SCKn (CPOLn=1) SAMPLE MOSIn MSB First … BIT7 BIT6 BIT2 BIT1 BIT0 LSB First … BIT0 BIT1 BIT5 BIT6 BIT7 MISOn /SSn OUT (MASTER) /SSn IN (SLAVE) Figure 11.64 USIn SPI Clock Formats when CPHAn=0 When CPHAn=0, the slave begins to drive its MISOn output with the first data bit value when SSn goes to active low.
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MC96F6432S ABOV Semiconductor Co., Ltd. SCKn (CPOLn=0) SCKn (CPOLn=1) SAMPLE MOSIn … MSB First BIT7 BIT6 BIT2 BIT1 BIT0 … LSB First BIT0 BIT1 BIT5 BIT6 BIT7 MISOn /SSn OUT (MASTER) /SSn IN (SLAVE) Figure 11.65 USIn SPI Clock Formats when CPHAn=1 When CPHAn=1, the slave begins to drive its MISOn output when SSn goes active low, but the data is not defined until the first SCKn edge.
MC96F6432S ABOV Semiconductor Co., Ltd. 11.12.14 USIn I2C Mode The USIn can be set to operate in industrial standard serial communication protocols mode. The I2C mode uses 2 bus lines serial data line (SDAn) and serial clock line (SCLn) to exchange data. Because both SDAn and SCLn lines are open-drain output, each line needs pull-up resistor.
MC96F6432S ABOV Semiconductor Co., Ltd. 11.12.16 USIn I2C Start / Repeated Start / Stop One master can issue a START (S) condition to notice other devices connected to the SCLn, SDAn lines that it will use the bus. A STOP (P) condition is generated by the master to release the bus lines so that other devices can use it.
MC96F6432S ABOV Semiconductor Co., Ltd. 11.12.18 USIn I2C Acknowledge The acknowledge related clock pulse is generated by the master. The transmitter releases the SDAn line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDAn line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse.
MC96F6432S ABOV Semiconductor Co., Ltd. USIn I2C Master Transmitter 11.12.20.1 To operate I2C in master transmitter, follow the recommended steps below. Enable I2C by setting USInMS[1:0]bits in USInCR1 and USInEN bit in USInCR2. This provides main clock to the peripheral.
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MC96F6432S ABOV Semiconductor Co., Ltd. This is ACK signal processing stage for data packet transmitted by master. I2C holds the SCLn LOW. When I2C loses bus mastership while transmitting data arbitrating other masters, the MLOSTn bit in USInST2 is set.
MC96F6432S ABOV Semiconductor Co., Ltd. USIn I2C Master Receiver 11.12.20.2 To operate I2C in master receiver, follow the recommended steps below. Enable I2C by setting USInMS[1:0]bits in USInCR1and USInEN bit in USInCR2. This provides main clock to the peripheral. Load SLAn+R into the USInDR where SLA is address of slave device and R is transfer direction from the viewpoint of the master.
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MC96F6432S ABOV Semiconductor Co., Ltd. 1-Byte of data is being received. This is ACK signal processing stage for data packet transmitted by slave. I2C holds the SCLn LOW. When 1- Byte of data is received completely, I2C generates TENDn interrupt.
MC96F6432S ABOV Semiconductor Co., Ltd. USIn I2C Slave Transmitter 11.12.20.3 To operate I2C in slave transmitter, follow the recommended steps below. If the main operating clock (SCLK) of the system is slower than that of SCLn, load value 0x00 into USInSDHR to make SDAn change within one system clock period from the falling edge of SCLn.
MC96F6432S ABOV Semiconductor Co., Ltd. USIn I2C Slave Receiver 11.12.20.4 To operate I2C in slave receiver, follow the recommended steps below. If the main operating clock (SCLK) of the system is slower than that of SCLn, load value 0x00 into USInSDHR to make SDAn change within one system clock period from the falling edge of SCLn.
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MC96F6432S ABOV Semiconductor Co., Ltd. USInSDHR (USInSDA Hold Time Register: For I2C mode): E4H/F4H, n = 0, 1 USInSDHR7 USInSDHR6 USInSDHR5 USInSDHR 4 USInSDHR 3 USInSDHR 2 USInSDHR 1 USInSDHR 0 Initial value: 01H USInSDHR[7:0] The register is used to control SDAn output timing from the falling edge of SCI in I2C mode.
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MC96F6432S ABOV Semiconductor Co., Ltd. USInSCLR (USInSCL Low Period Register: For I2C mode): E6H/F6H, n = 0, 1 USInSCLR7 USInSCLR6 USInSCLR5 USInSCLR 4 USInSCLR 3 USInSCLR 2 USInSCLR 1 USInSCLR 0 Initial value: 3FH USInSCLR[7:0] This register defines the high period of SCLn when it operates in I2C master mode.
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MC96F6432S ABOV Semiconductor Co., Ltd. USInCR1 (USIn Control Register 1: For UART, SPI, and I2C mode): D9H/E9H, n = 0, 1 USInS1 USInS0 USInMS1 USInMS0 USInPM1 USInPM0 USInS2 CPOLn ORDn CPHAn Initial value: 00H USInMS[1:0] Selects operation mode of USIn...
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MC96F6432S ABOV Semiconductor Co., Ltd. USInCR2 (USIn Control Register 2: For UART, SPI, and I2C mode): DAH/EAH, n = 0, 1 DRIEn TXCIEn RXCIEn WAKEIEn TXEn RXEn USInEN DBLSn Initial value: 00H DRIEn Interrupt enable bit for data register empty (only UART and SPI mode).
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MC96F6432S ABOV Semiconductor Co., Ltd. USInCR3 (USIn Control Register 3: For UART, SPI, and I2C mode): DBH/EBH, n = 0, 1 MASTERn LOOPSn DISSCKn USInSSEN FXCHn USInSB USInTX8 USInRX8 Initial value: 00H MASTERn Selects master or slave in SPI and synchronous mode operation and controls the direction of SCKn pin Slave mode operation (External clock for SCKn).
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MC96F6432S ABOV Semiconductor Co., Ltd. USI0CR4 (USIn Control Register 4: For I2C mode): DCH/ECH, n = 0, 1 – IICnIFR TXDLYENBn IICnIE ACKnEN IMASTERn STOPCn STARTCn – Initial value: 00H This is an interrupt flag bit for I2C mode. When an interrupt occurs, this bit becomes ‘1’.
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MC96F6432S ABOV Semiconductor Co., Ltd. USInST1 (USIn Status Register 1: For UART and SPI mode): E1H/F1H, n = 0, 1 DREn TXCn RXCn WAKEn USInRST DORn Initial value: 80H DREn The DREn flag indicates if the transmit buffer (USInDR) is ready to receive new data. If DREn is ‘1’, the buffer is empty and ready to be written.
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MC96F6432S ABOV Semiconductor Co., Ltd. USInST2 (USIn Status Register 2: For I2C mode): E2H/F2H, n = 0, 1 GCALLn TENDn STOPDn SSELn MLOSTn BUSYn TMODEn RXACKn Initial value: 00H (NOTE) GCALLn This bit has different meaning depending on whether I2C is master or slave. When I2C is a master, this bit represents whether it received AACK (address ACK) from slave.
MC96F6432S ABOV Semiconductor Co., Ltd. 11.13 LCD Driver 11.13.1 Overview The LCD driver is controlled by the LCD Control Register (LCDCRH/L). The LCLK[1:0] determines the frequency of COM signal scanning of each segment output. A RESET clears the LCD control register LCDCRH and LCDCRL values to logic ‘0’.
MC96F6432S ABOV Semiconductor Co., Ltd. 11.13.2 LCD Display RAM Organization Display data are stored to the display data area in the external data memory. The display data which stored to the display external data area (address 0000H-001AH) are read automatically and sent to the LCD driver by the hardware.
MC96F6432S ABOV Semiconductor Co., Ltd. Power Down Operation 12.1 Overview The MC96F6432S has two power-down modes to minimize the power consumption of the device. In power down mode, power consumption is reduced considerably. The device provides three kinds of power saving functions, Main- IDLE, Sub-IDLE and STOP mode.
MC96F6432S ABOV Semiconductor Co., Ltd. 12.3 IDLE Mode The power control register is set to ‘01h’ to enter the IDLE Mode. In this mode, the internal oscillation circuits remain active. Oscillation continues and peripherals are operated normally but CPU stops. It is released by reset or interrupt.
MC96F6432S ABOV Semiconductor Co., Ltd. 12.4 STOP Mode The power control register is set to ‘03H’ to enter the STOP Mode. In the stop mode, the selected oscillator, system clock and peripheral clock is stopped, but watch timer can be continued to operate with sub clock. With the clock frozen, all functions are stopped, but the on-chip RAM and control registers are held.
MC96F6432S ABOV Semiconductor Co., Ltd. 12.5 Release Operation of STOP Mode After STOP mode is released, the operation begins according to content of related interrupt register just before STOP mode start (Figure 12.3).If the global interrupt Enable Flag (IE.EA)is set to `1`, the STOP mode isreleased by the interrupt which each interrupt enable flag = `1` and the CPU jumps to the relevant interrupt service routine.
MC96F6432S ABOV Semiconductor Co., Ltd. 12.6 Register Map Name Address Direction Default Description PCON Power Control Register Power Down Operation Register Map Table 12.2 12.7 Power Down Operation Register Description The power down operation register consists of the power control register (PCON).
MC96F6432S ABOV Semiconductor Co., Ltd. RESET 13.1 Overview The following is the hardware setting value. On Chip Hardware Initial Value Program Counter (PC) 0000h Accumulator Stack Pointer (SP) Peripheral Clock Control Register Refer to the Peripheral Registers Reset State Table 13.1 13.2...
MC96F6432S ABOV Semiconductor Co., Ltd. 13.4 RESET Noise Canceller The Figure 13.2 is the noise canceller diagram for noise cancellation of RESET. It has the noise cancellation value of about 2us(@V =5V) to the low input of system reset. t < T t <...
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MC96F6432S ABOV Semiconductor Co., Ltd. Counting for configure read start after POR is released Internal nPOR PAD RESETB “H” LVR_RESETB .. 27 28 BIT (for Configure) 00 01 02 03 BIT (for Reset) 1us X 256 X 28h = about 10ms...
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MC96F6432S ABOV Semiconductor Co., Ltd. Process Description Remarks ① - No Operation ② -1st POR level Detection -about 1.4V - (INT-OSC 8MHz/8)x256x28h Delay section (=10ms) ③ -Slew Rate >= 0.05V/ms -VDD input voltage must rise over than flash operating voltage for Configure option read -about 1.5V ~ 1.6V...
MC96F6432S ABOV Semiconductor Co., Ltd. 13.6 External RESETB Input The External RESETB is the input to a Schmitt trigger. If RESETB pin is held with low for at least 10us over within the operating voltage range and stable oscillation, it is applied and the internal state is initialized. After reset state becomes ‘1’, it needs the stabilization time with 16ms and after the stable state, the internal RESET becomes ‘1’.
MC96F6432S ABOV Semiconductor Co., Ltd. 13.7 Brown Out Detector Processor The MC96F6432S has an On-chip brown-out detection circuit (BOD) for monitoring the VDD level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by LVRVS[3:0] bit to be 1.60V, 2.00V, 2.10V, 2.20V,2.32V, 2.44V, 2.59V, 2.75V, 2.93V, 3.14V, 3.38V, 3.67V, 4.00V, 4.40V.
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MC96F6432S ABOV Semiconductor Co., Ltd. “H” “H” Internal nPOR “H” PAD RESETB LVR_RESETB ..27 28 BIT (for Config) 00 01 02 BIT (for Reset) 1us X 256 X 28h = about 10ms Config Read 1us X 4096 X 4h = about 16ms...
MC96F6432S ABOV Semiconductor Co., Ltd. 13.11 Register Description for Reset Operation RSTFR (Reset Flag Register): E8H – – – – PORF EXTRF WDTRF LVRF – – – – Initial value: 80H Power-On Reset flag bit. The bit is reset by writing ‘0’ to this bit.
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MC96F6432S ABOV Semiconductor Co., Ltd. LVRCR (Low Voltage Reset Control Register): D8H – – LVRST LVRVS3 LVRVS2 LVRVS1 LVRVS0 LVREN – – Initial value: 00H LVRST LVR Enable when Stop Release Not effect at stop release LVR enable at stop release NOTE) When this bit is ‘1’, the LVREN bit is cleared to ‘0’...
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MC96F6432S ABOV Semiconductor Co., Ltd. LVICR (Low Voltage Indicator Control Register): 86H – – LVIF LVIEN LVILS3 LVILS2 LVILS1 LVILS0 – – Initial value: 00H LVIF Low Voltage Indicator Flag Bit No detection Detection LVIEN LVI Enable/Disable Disable Enable LVILS[3:0]...
MC96F6432S ABOV Semiconductor Co., Ltd. On-chip Debug System(MC96F6432 ONLY) 14.1 Overview 14.1.1 Description MC96F6432S can not support On-chip debug(OCD). MC96F6432S isn’t equipped with on-chip debugger. We recommend to develop and debug program with MC96F6432. On-chip debug system of MC96F6432 can be used for programming the non-volatile memories and on-chip debugging.
MC96F6432S ABOV Semiconductor Co., Ltd. 14.1.2 Feature • Two-wire external interface: 1-wire serial clock input, 1-wire bi-directional serial data bus • Debugger Access to: − All Internal Peripheral Units − Internal data RAM − Program Counter − Flash and Data EEPROM Memories •...
MC96F6432S ABOV Semiconductor Co., Ltd. 14.2 Two-Pin External Interface 14.2.1 Basic Transmission Packet • 10-bit packet transmission using two-pin interface. • 1-packet consists of 8-bit data, 1-bit parity and 1-bit acknowledge. • Parity is even of ‘1’ for 8-bit data in transmitter.
MC96F6432S ABOV Semiconductor Co., Ltd. 14.2.2 Packet Transmission Timing Data Transfer 14.2.2.1 DSDA acknowledgement acknowledgement signal from receiver signal from receiver DSCL START STOP Figure 14.3 Data Transfer on the Twin Bus Bit Transfer 14.2.2.2 DSDA DSCL data line change...
MC96F6432S ABOV Semiconductor Co., Ltd. Start and Stop Condition 14.2.2.3 DSDA DSDA DSCL DSCL START condition STOP condition Figure 14.5 Start and Stop Condition Acknowledge Bit 14.2.2.4 Data output By transmitter no acknowledge Data output By receiver acknowledge DSCL from...
MC96F6432S ABOV Semiconductor Co., Ltd. 14.2.3 Connection of Transmission Two-pin interface connection uses open-drain(wire-AND bidirectional I/O). pull resistors DSDA(Debugger Serial Data Line) DSCL(Debugger Serial Clock Line) DSCL DSDA DSCL DSDA DSDA DSDA DSCL DSCL Target Device(Slave) Host Machine(Master) Current source for DSCL to fast 0 to 1 transition in high speed mode Figure 14.8...
MC96F6432S ABOV Semiconductor Co., Ltd. Flash Memory 15.1 Overview 15.1.1 Description MC96F6432S incorporates flash memory to which a program can be written, erased, and overwritten while mounted on the board. The flash memory can be read by ‘MOVC’ instruction and it can be programmed in serial ISP mode or user program mode.
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MC96F6432S ABOV Semiconductor Co., Ltd. FMCR (Flash Mode Control Register): FEH – – – – FMBUSY FMCR2 FMCR1 FMCR0 – – – – Initial value: 00H FMBUSY Flash Mode Busy Bit. This bit will be used for only debugger. No effect when “1” is written...
MC96F6432S ABOV Semiconductor Co., Ltd. 15.1.6 Serial In-System Program (ISP) Mode Serial in-system program uses the interface of debugger which uses two wires. Refer to chapter 14 in details about debugger 15.1.7 Protection Area (User program mode) MC96F6432S can program its own flash memory (protection area). The protection area can not be erased or programmed.
MC96F6432S ABOV Semiconductor Co., Ltd. 15.1.8 Erase Mode The sector erase program procedure in user program mode Page buffer clear (FMCR=0x01) Write ‘0’ to page buffer Set flash sector address register (FSADRH/FSADRM/FSADRL). Set flash identification register (FIDR). (Note) Check the UserID for to prevent the invalid work Set flash mode control register (FMCR).
MC96F6432S ABOV Semiconductor Co., Ltd. 15.1.9 Write Mode The sector Write program procedure in user program mode Page buffer clear (FMCR=0x01) Write data to page buffer Set flash sector address register (FSADRH/FSADRM/FSADRL). Set flash identification register (FIDR). (Note1) Check the UserID for to prevent the invalid work Set flash mode control register (FMCR).
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MC96F6432S ABOV Semiconductor Co., Ltd. The Byte Write program procedure in user program mode Page buffer clear (FMCR=0x01) Write data to page buffer Set flash sector address register (FSADRH/FSADRM/FSADRL). Set flash identification register (FIDR). (Note1) Check the UserID for to prevent the invalid work Set flash mode control register (FMCR).
MC96F6432S ABOV Semiconductor Co., Ltd. 15.1.10 Protection for Invalid Erase/Write It should be taken care to the flash erase/write programming in code. You must make preparations for invalid jump to the flash erase/write code by malfunction, noise, and power off.
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MC96F6432S ABOV Semiconductor Co., Ltd. The flash sector address (FSADRH/FSADRM/FSADRL) should always keep the address of the flash which is used for data area. For example, The FSADRH/FSADRM is always 0x00/0x7f” if 0x7f00 to 0x7fff is used for data. Overview of main...
MC96F6432S ABOV Semiconductor Co., Ltd. Flow of Protection for Invalid Erase/Write 15.1.10.1 Start Work1 Decide to write/erase Set Flags on flash Work2 Check the flag for Match Write UserID1/2/3 UserID Work3 Check the UserID for Match Write/Erase Flash write/erase flash...
MC96F6432S ABOV Semiconductor Co., Ltd. 15.1.11 Read Mode The Reading program procedure in user program mode Load receive data from flash memory on MOVC instruction by indirectly addressing mode. Program Tip – reading A,#0 DPH,#0x7F DPL,#0x40 ;flash memory address MOVC A,@A+DPTR ;read data from flash memory...
MC96F6432S ABOV Semiconductor Co., Ltd. Configure Option 16.1 Configure Option Control The data for configure option should be written in the configure option area (003EH – 003FH) by programmer (Writer tools). CONFIGURE OPTION 1 : ROM Address 003FH – –...
MC96F6432S ABOV Semiconductor Co., Ltd. APPENDIX 17.1 Instruction Table Instructions are either1, 2 or 3bytes long as listed in the ‘Bytes’ column below. Each instruction takes either 1, 2 or 4 machine cycles to execute as listed in the following table. 1 machine cycle comprises 2 system clock cycles.
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MC96F6432S ABOV Semiconductor Co., Ltd. LOGICAL Mnemonic Description Bytes Cycles Hex code ANL A,Rn AND register to A 58-5F ANL A,dir AND direct byte to A ANL A,@Ri AND indirect memory to A 56-57 ANL A,#data AND immediate to A...
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MC96F6432S ABOV Semiconductor Co., Ltd. DATA TRANSFER Mnemonic Description Bytes Cycles Hex code MOV A,Rn Move register to A E8-EF MOV A,dir Move direct byte to A MOV A,@Ri Move indirect memory to A E6-E7 MOV A,#data Move immediate to A...
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MC96F6432S ABOV Semiconductor Co., Ltd. BRANCHING Mnemonic Description Bytes Cycles Hex code ACALL addr 11 Absolute jump to subroutine 11→F1 LCALL addr 16 Long jump to subroutine Return from subroutine RETI Return from interrupt AJMP addr 11 Absolute jump unconditional 01→E1...
MC96F6432S ABOV Semiconductor Co., Ltd. 17.2 Instructions on how to use the input port. • Error occur status − Using compare jump instructions with input port, it could cause error due to the timing conflict inside the MCU. − Compare jump Instructions which cause potential error used with input port condition: bit, rel ;...
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MC96F6432S ABOV Semiconductor Co., Ltd. − If you use input bit port for compare jump instruction, you have to copy the input port as internal parameter or carry bit and then use compare jump instruction. bit tt; zzz: MOV C,080.0 ;...
MC96F6432S ABOV Semiconductor Co., Ltd. 17.3 ESD Test Method ESD Test Description ESD Testing was perform on Zapmaster system using the Human-Body-Model (H.B.M) and Machine-Model (M.M) according JESD22-A114F and EIA/JESD22-A115-A respectively. Human-Body-Model stresses devices by sudden application of a high voltage supplied by a 100pF capacitor through 1.5k Ohms resistance. Machine-Model stresses devices by sudden application of a high voltage supplied by a 200pF capacitor through very low (0 Ohm) resistance.
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MC96F6432S ABOV Semiconductor Co., Ltd. ESD Test Method : I/O (Pin-to-Pin) Mode I/O pins are zapped, pin by pin. I/O pins which are not zapped are grounded. All power pins (VDD and VSS) are floated. ESD Class HBM (Human-Body-Model) : 3A...
MC96F6432S ABOV Semiconductor Co., Ltd. 17.4 Flash Protection for Invalid Erase/Write Overview This is example to prevent changing code or data in flash by abnormal operation(noise, unstable power, malfunction, etc…). How to protect the flash • Divide into decision and execution to Erase/Write in flash.
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MC96F6432S ABOV Semiconductor Co., Ltd. Flowchart Start Initial ① Set LVR/LVI more than 2.0V Start Main Loop Working ③ Write Flash? Set User_ID1 ② Working ③ Check User_ID1? Set User_ID2 Working Check User_ID2? Set User_ID3 ③ Working Write Flash Set FSADDRH/M/L ④...
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Initialize User_ID1/2/3 Set Flash Sector Address to Dummy Address • Sample Source Refer to the ABOV homepage. It is created based on the MC97F2664. Each product should be modified according to the Page Buffer Size and Flash Size Etc •...
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MC96F6432S ABOV Semiconductor Co., Ltd. 17.1 Instruction Table .............................. 267 17.2 Instructions on how to use the input port......................271 17.3 ESD Test Method ............................273 17.4 Flash Protection for Invalid Erase/Write ......................275 Table of contents ................................. 278...
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