Abov MC96F6432S Series User Manual

Abov MC96F6432S Series User Manual

Cmos single-chip 8-bit mcu with 12-bit a/d converter and lcd driver
Table of Contents

Advertisement

CMOS single-chip 8-bit MCU
with 12-bit A/D converter and
LCD driver
Main features
8-bit Microcontroller With High Speed 8051 CPU
Basic MCU Function
– 32Kbytes Flash Code Memory
– 1024bytes SRAM
Built-in Analog Function
– Power-On Reset and Low Voltage Detect Reset
– Internal 16MHz RC Oscillator (±1.5%, T
– Watchdog Timer RC Oscillator (5kHz)
Peripheral Features
– 12-bit Analog to Digital Converter (16inputs)
– USI (USART + SPI + I2C) 2sets
– LCD Driver (21segments x 8commons)
I/O and Packages
– Up to 42 programmable I/O lines with 44 MQFP-1010
– 32 LQFP
– 32/28 SOP, 28 TSSOP
Operating Conditions
– 1.8V to 5.5V Wide Voltage Range
– -40°C to 85°C Temperature Range
Application
– Small Home Appliance
– BLDC Motor Controller
= 0 ~ +50°C)
A
MC96F6432S
User's manual
V 1.9
Revised 22 June, 2018

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the MC96F6432S Series and is the answer not in the manual?

Questions and answers

Summary of Contents for Abov MC96F6432S Series

  • Page 1 CMOS single-chip 8-bit MCU with 12-bit A/D converter and LCD driver MC96F6432S Main features User’s manual 8-bit Microcontroller With High Speed 8051 CPU  Basic MCU Function  V 1.9 – 32Kbytes Flash Code Memory – 1024bytes SRAM Built-in Analog Function ...
  • Page 2: Revision History

    The information, diagrams and other data in this manual are correct and reliable; however, ABOV Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
  • Page 3: Overview

    MC96F6432S ABOV Semiconductor Co., Ltd. Overview 1.1. Description The MC96F6432S is an advanced CMOS 8-bit microcontroller with 32Kbytes of FLASH. This is powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. This offers the following features: 32Kbytes of FLASH, 256bytes of IRAM, 768bytes of XRAM, general purpose I/O, basic...
  • Page 4: Features

    MC96F6432S ABOV Semiconductor Co., Ltd. Features   Low Voltage Reset – 8-bit CISC core (M8051, 2 clocks per cycle) – 14 levels detect  ROM (FLASH) Capacity (1.60/ 2.00/ 2.10/ 2.20/ 2.32/ 2.44/ 2.59/ 2.75/ 2.93/ 3.14/ 3.38/ 3.67/ 4.00/ 4.40V) –...
  • Page 5: Development Tools

    1.3.1 Compiler ABOV Semiconductor does not provide compiler. It is recommended that you consult a compier provider. The MC96F6432S core is Mentor 8051, and the ROM size is smaller than 64Kbytes.Therefore, developer can use the standard 8051 compiler from other providers.
  • Page 6: Programmer

    MC96F6432S ABOV Semiconductor Co., Ltd. 1.3.3 Programmer Single programmer: E-PGM+ : It programs MCU device directly. Figure 1.2 E-PGM+(Single writer)
  • Page 7 MC96F6432S ABOV Semiconductor Co., Ltd. Gang programmer: E-GANG4 and E-GANG6 It can run PC controlled mode. It can run standalone without PC control too. USB interface is supported. Easy to connect to the handler. Figure 1.3 E-GANG4 and E-GANG6 (for Mass Production)
  • Page 8: Mtp Programming

    MC96F6432S ABOV Semiconductor Co., Ltd. MTP programming 1.4.1 Overview The program memory of MC96F6432S is MTP Type. This flash is accessed by serial data format. There are four pins(DSCL, DSDA, VDD, and VSS) for programming/reading the flash. During programming Main chip...
  • Page 9 MC96F6432S ABOV Semiconductor Co., Ltd. E-PGM+, E-GANG4/E-GANG6 R1 (2kΩ ~ 5kΩ) DSCL(I) To application circuit R2 (2kΩ ~ 5kΩ) DSDA(I/O) To application circuit NOTE) In on-board programming mode, very high-speed signal will be provided to pin DSCL and DSDA. And it will cause some damages to the application circuits connected to DSCL or DSDA port if the application circuit is designed as high speed response such as relay control circuit.
  • Page 10: Block Diagram

    MC96F6432S ABOV Semiconductor Co., Ltd. Block diagram Flash 32KB CORE XRAM M8051 768B IRAM 256B General purpose I/O In-system programming 9 ports normal I/O 33 ports LCD shared I/O Power control Power on reset Low voltage reset Watchdog timer Low voltage indicator...
  • Page 11: Pin Assignment

    MC96F6432S ABOV Semiconductor Co., Ltd. Pin assignment P55/RESETB P04/SEG25/AN2/EINT2/PWM4BA P40/VLC3/RXD0/SCL0/MISO0 P05/SEG24/AN3/EINT3/PWM4BB P41/VLC2/TXD0/SDA0/MOSI0 P06/SEG23/AN4/EINT4/PWM4CA P42/VLC1/SCK0 P07/SEG22/AN5/EINT5/PWM4CB P43/VLC0/SS0 MC96F6432SQ P17/SEG21/AN6/EINT6/SS2 P37/COM0 P16/SEG20/AN7/EINT7/SCK2 (44MQFP-1010) P36/COM1 P15/SEG19/AN8/MISO2 P35/COM2/SEG0 P14/SEG18/AN9/MOSI2 P34/COM3/SEG1 P13/SEG17/AN10/EC1/BUZO P33/COM4/SEG2 P12/SEG16/AN11/EINT11/T1O/PWM1O P32/COM5/SEG3 P11/SEG15/AN12/EINT12/T2O/PWM2O NOTE) The programmer (E-PGM+, E-Gang4/E-Gang6) uses P0[1:0] pin as DSCL, DSDA.
  • Page 12 MC96F6432S ABOV Semiconductor Co., Ltd. P53/SXIN/T0O/PWM0O P03/SEG26/AN1/EINT1/PWM4AB P54/SXOUT/EINT10 P04/SEG25/AN2/EINT2/PWM4BA P55/RESETB P05/SEG24/AN3/EINT3/PWM4BB P40/VLC3/RXD0/SCL0/MISO0 P06/SEG23/AN4/EINT4/PWM4CA MC96F6332L P41/VLC2/TXD0/SDA0/MOSI0 P07/SEG22/AN5/EINT5/PWM4CB (32-LQFP) P42/VLC1/SCK0 P13/SEG17/AN10/EC1/BUZO P33/COM4/SEG2 P12/SEG16/AN11/EINT11/T1O/PWM1O P32/COM5/SEG3 P11/SEG15/AN12/EINT12/T2O/PWM2O NOTE) The programmer (E-PGM+, E-Gang4/E-Gang6) uses P0[1:0] pin as DSCL, DSDA. The P14-P17, P23-P25, P34-P37 and P43 pins should be selected as a push-pull output or an input with pull-up resistor by software control when the 32-pin package is used.
  • Page 13 MC96F6432S ABOV Semiconductor Co., Ltd. P50/XOUT P00/EC3/DSDA P51/XIN P01/T3O/DSCL P52/EINT8/EC0/BLNK P02/AN0/AVREF/EINT0/T4O/PWM4AA P53/SXIN/T0O/PWM0O P03/SEG26/AN1/EINT1/PWM4AB P54/SXOUT/EINT10 P04/SEG25/AN2/EINT2/PWM4BA P55/RESETB P05/SEG24/AN3/EINT3/PWM4BB MC96F6332SD P40/VLC3/RXD0/SCL0/MISO0 P06/SEG23/AN4/EINT4/PWM4CA (32-SOP) P41/VLC2/TXD0/SDA0/MOSI0 P07/SEG22/AN5/EINT5/PWM4CB P42/VLC1/SCK0 P13/SEG17/AN10/EC1/BUZO P33/COM4/SEG2 P12/SEG16/AN11/EINT11/T1O/PWM1O P32/COM5/SEG3 P11/SEG15/AN12/EINT12/T2O/PWM2O P31/COM6/SEG4 P10/SEG14/AN13/RXD1/SCL1/MISO1 P30/COM7/SEG5 P20/SEG13/AN14/TXD1/SDA1/MOSI1 P27/SEG6 P21/SEG12/AN15/SCK1 P26/SEG7 P22/SEG11/SS1 NOTE) The programmer (E-PGM+, E-Gang4/E-Gang6) uses P0[1:0] pin as DSCL, DSDA.
  • Page 14 MC96F6432S ABOV Semiconductor Co., Ltd. P50/XOUT P00/EC3/DSDA P51/XIN P01/T3O/DSCL P52/EINT8/EC0/BLNK P02/AN0/AVREF/EINT0/T4O/PWM4AA P53/SXIN/T0O/PWM0O P03/SEG26/AN1/EINT1/PWM4AB P54/SXOUT/EINT10 P04/SEG25/AN2/EINT2/PWM4BA P55/RESETB P05/SEG24/AN3/EINT3/PWM4BB MC96F6332SR P40/VLC3/RXD0/SCL0/MISO0 P06/SEG23/AN4/EINT4/PWM4CA (28-TSSOP) P41/VLC2/TXD0/SDA0/MOSI0 P07/SEG22/AN5/EINT5/PWM4CB P42/VLC1/SCK0 P12/SEG16/AN11/EINT11/T1O/PWM1O P33/COM4/SEG2 P11/SEG15/AN12/EINT12/T2O/PWM2O P32/COM5/SEG3 P10/SEG14/AN13/RXD1/SCL1/MISO1 P31/COM6/SEG4 P20/SEG13/AN14/TXD1/SDA1/MOSI1 P30/COM7/SEG5 P21/SEG12/AN15/SCK1 NOTE) The programmer (E-PGM+, E-Gang4/E-Gang6) uses P0[1:0] pin as DSCL, DSDA.
  • Page 15: Package Diagram

    MC96F6432S ABOV Semiconductor Co., Ltd. Package Diagram Figure 4.1 44-Pin MQFP Package...
  • Page 16 MC96F6432S ABOV Semiconductor Co., Ltd. Figure 4.2 32-Pin LQFP Package...
  • Page 17 MC96F6432S ABOV Semiconductor Co., Ltd. Figure 4.3 32-Pin SOP Package...
  • Page 18 MC96F6432S ABOV Semiconductor Co., Ltd. Figure 4.4 28-Pin SOP Package...
  • Page 19 MC96F6432S ABOV Semiconductor Co., Ltd. Figure 4.5 28-Pin TSSOP Package...
  • Page 20: Pin Description

    MC96F6432S ABOV Semiconductor Co., Ltd. Pin Description Function @RESET Shared with Name Port 0 is a bit-programmable I/O port which can be EC3/DSDA configured as a Schmitt-trigger input, a push-pull T3O/DSCL output, or an open-drain output. A pull-up resistor can be specified in 1-bit unit.
  • Page 21 MC96F6432S ABOV Semiconductor Co., Ltd. Function @RESET Shared with Name Port 5 is a bit-programmable I/O port which can be XOUT configured as a Schmitt-trigger input or a push-pull output. A pull-up resistor can be specified in 1-bit unit. EINT8/EC0/BLNK...
  • Page 22 MC96F6432S ABOV Semiconductor Co., Ltd. Function @RESET Shared with Name BUZO Buzzer signal output Input P13/SEG17/AN10/EC1 SCK0 Serial 0 clock input/output Input P42/VLC1 SCK1 Serial 1 clock input/output Input P21/SEG12/AN15 SCK2 Serial 2 clock input/output Input P16/SEG20/AN7/EINT7 MOSI0 SPI 0 master output, slave input...
  • Page 23 MC96F6432S ABOV Semiconductor Co., Ltd. PIN Name Function @RESET Shared with VLC0 P43/SS0 VLC1 P42/SCK0 LCD bias voltage pins Input VLC2 P41/TXD0/SDA0/MOSI0 VLC3 P40/RXD0/SCL0/MISO0 COM0 P37–P36 COM1 COM2– LCD common signal outputs Input P35–P34/SEG0–SEG1 COM3 COM4– P33–P30/SEG2–SEG5 COM7 SEG0– P35–P34/COM2–COM3 SEG1 SEG2–...
  • Page 24 MC96F6432S ABOV Semiconductor Co., Ltd. Function @RESET Shared with Name System reset pin with a pull-up resistor when it is RESETB Input selected as the RESETB by CONFIGURE OPTION DSDA In-system programming data input/output Input P00/EC3 DSCL In-system programming clock input...
  • Page 25: Port Structures

    MC96F6432S ABOV Semiconductor Co., Ltd. Port Structures General Purpose I/O Port Level Shift (1.8V to ExtVDD) Level Shift (ExtVDD to 1.8V) PULL-UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE SUB-FUNC DIRECTION DIRECTION REGISTER CMOS or Schmitt Level...
  • Page 26: External Interrupt I/O Port

    MC96F6432S ABOV Semiconductor Co., Ltd. External Interrupt I/O Port Level Shift (1.8V to ExtVDD) Level Shift (ExtVDD to 1.8V) PULL-UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE SUB-FUNC DIRECTION DIRECTION REGISTER EXTERNAL INTERRUPT POLARITY REG. INTERRUPT...
  • Page 27: Electrical Characteristics

    MC96F6432S ABOV Semiconductor Co., Ltd. Electrical Characteristics Absolute Maximum Ratings Parameter Symbol Rating Unit Note – Supply Voltage -0.3~+6.5 -0.3~VDD+0.3 Voltage on any pin with respect to VSS -0.3~VDD+0.3 Maximum current output sourced by (I per I/O pin) Normal Voltage Pin ∑...
  • Page 28: A/D Converter Characteristics

    MC96F6432S ABOV Semiconductor Co., Ltd. A/D Converter Characteristics =-40°C ~ +85°C, VDD=1.8V ~ 5.5V, VSS=0V) Parameter Symbol Conditions Unit – – –- – Resolution – – Integral Linear Error ±6 – – Differential Linearity Error ±1 AVREF= 2.7V – 5.5V fx= 8MHz –...
  • Page 29: Low Voltage Reset And Low Voltage Indicator Characteristics

    MC96F6432S ABOV Semiconductor Co., Ltd. Low Voltage Reset and Low Voltage Indicator Characteristics =-40°C ~ +85°C, VDD=1.8V ~ 5.5V, VSS=0V) Parameter Symbol Conditions Unit – 1.60 1.79 1.85 2.00 2.15 1.95 2.10 2.25 2.05 2.20 2.35 2.17 2.32 2.47 2.29 2.44...
  • Page 30: Internal Watch-Dog Timer Rc Oscillator Characteristics

    MC96F6432S ABOV Semiconductor Co., Ltd. Internal Watch-Dog Timer RC Oscillator Characteristics =-40°C ~ +85°C, VDD=1.8V ~ 5.5V, VSS=0V) Parameter Symbol Conditions Unit – Frequency WDTRC – – – Stabilization Time WDTS – – Enable WDTRC Current WDTRC – – Disable Internal WDTRC Oscillator Characteristics Table 7.7...
  • Page 31: Dc Characteristics

    MC96F6432S ABOV Semiconductor Co., Ltd. DC Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V, f = 12MHz) Parameter Symbol Conditions Unit – P0, P1,P5, RESETB 0.8VDD Input High Voltage – All input pins except V 0.7VDD –...
  • Page 32: Ac Characteristics

    MC96F6432S ABOV Semiconductor Co., Ltd. 7.10 AC Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) Parameter Symbol Conditions Unit – – RESETB input low width Input, VDD= 5V – – Interrupt input high, low width All interrupt, VDD= 5V...
  • Page 33: Spi0/1/2 Characteristics

    MC96F6432S ABOV Semiconductor Co., Ltd. 7.11 SPI0/1/2 Characteristics =-40°C– +85°C, VDD=1.8V – 5.5V) Parameter Symbol Conditions Unit – – Output Clock Pulse Period Internal SCK source – – Input Clock Pulse Period External SCK source – – Output Clock High, Low Pulse Width...
  • Page 34: Uart0/1 Characteristics

    MC96F6432S ABOV Semiconductor Co., Ltd. 7.12 UART0/1 Characteristics =-40°C ~ +85°C, VDD=1.8V ~ 5.5V, f =11.1MHz) Parameter Symbol Unit Serial port clock cycle time 1250 x 16 1650 – Output data setup to clock rising edge x 13 – –...
  • Page 35: I2C0/1 Characteristics

    MC96F6432S ABOV Semiconductor Co., Ltd. 7.13 I2C0/1 Characteristics =-40°C ~ +85°C, VDD=1.8V ~ 5.5V) Standard Mode High-Speed Mode Parameter Symbol Unit Clock frequency – – Clock High Pulse Width SCLH – – Clock Low Pulse Width SCLL – – Bus Free Time –...
  • Page 36: Data Retention Voltage In Stop Mode

    MC96F6432S ABOV Semiconductor Co., Ltd. 7.14 Data Retention Voltage in Stop Mode =-40°C ~ +85°C, VDD=1.8V ~ 5.5V) Parameter Symbol Conditions Unit – – Data retention supply voltage DDDR VDDR= 1.8V, – – Data retention supply current = 25°C), DDDR...
  • Page 37: Internal Flash Rom Characteristics

    MC96F6432S ABOV Semiconductor Co., Ltd. 7.15 Internal Flash Rom Characteristics =-40°C ~ +85°C, VDD=1.8V ~ 5.5V, VSS= 0V) Parameter Symbol Condition Unit – – Sector Write Time – – Sector Erase Time – – Code Write Protection Time – –...
  • Page 38: Main Clock Oscillator Characteristics

    MC96F6432S ABOV Semiconductor Co., Ltd. 7.17 Main Clock Oscillator Characteristics =-40°C ~ +85°C, VDD=1.8V ~ 5.5V) Oscillator Parameter Condition Unit 1.8V – 5.5V – 2.7V – 5.5V – Crystal Main oscillation frequency 10.0 3.0V – 5.5V – 12.0 1.8V – 5.5V –...
  • Page 39: Sub Clock Oscillator Characteristics

    MC96F6432S ABOV Semiconductor Co., Ltd. 7.18 Sub Clock Oscillator Characteristics =-40°C ~ +85°C, VDD=1.8V ~ 5.5V) Oscillator Parameter Condition Unit Crystal Sub oscillation frequency 32.768 1.8V – 5.5V – External Clock SXIN input frequency Sub Clock Oscillator Characteristics Table 7.19...
  • Page 40: Main Oscillation Stabilization Characteristics

    MC96F6432S ABOV Semiconductor Co., Ltd. 7.19 Main Oscillation Stabilization Characteristics =-40°C ~ +85°C, VDD=1.8V ~ 5.5V) Oscillator Parameter Unit fx > 4MHz, VDD = 2.7V ~ 5.5V, – – Crystal fx > 1MHz, VDD = 1.8V, T =-40°C – –...
  • Page 41: Operating Voltage Range

    MC96F6432S ABOV Semiconductor Co., Ltd. 7.21 Operating Voltage Range =0.4 to 12MHz) =32 to 38kHz) 12.0MHz 32.768kHz 10.0MHz 4.2MHz 0.4MHz Supply voltage (V) Supply voltage (V) Figure 7.14 Operating Voltage Range...
  • Page 42: Recommended Circuit And Layout

    MC96F6432S ABOV Semiconductor Co., Ltd. 7.22 Recommended Circuit and Layout This 0.1uF capacitor should be within 1cm from the VDD pin of MCU on the PCB layout. DC Power 0.1uF 0.1uF The MCU power line (VDD and VSS) should be separated from the high-...
  • Page 43: Recommended Circuit And Layout With Smps Power

    MC96F6432S ABOV Semiconductor Co., Ltd. 7.23 Recommended Circuit and Layout with SMPS Power SMPS Side MCU Side SMPS 1. The C1 capacitor is to flatten out the voltage of the SMPS power, VCC. √ Recommended C1: 470uF/25V more. 2. The R1 and C2 are the RC filter for VDD and suppress the ripple of VCC.
  • Page 44: Typical Characteristics

    MC96F6432S ABOV Semiconductor Co., Ltd. 7.24 Typical Characteristics These graphs and tables provided in this section are only for design guidance and are not tested or guaranteed. In graphs or tables some data are out of specified operating range (e.g. out of specified VDD range). This is only for information and devices are guaranteed to operate properly only within the specified range.
  • Page 45 MC96F6432S ABOV Semiconductor Co., Ltd. 160.0 140.0 120.0 100.0 -40℃ 80.0 +25℃ 60.0 +85℃ 40.0 20.0 2.7V 3.0V 3.3V 4.5V 5.0V 5.5V Figure 7.19 SUB RUN (IDD3) Current 30.00 25.00 20.00 -40℃ 15.00 +25℃ +85℃ 10.00 5.00 0.00 2.7V 3.0V 3.3V...
  • Page 46 MC96F6432S ABOV Semiconductor Co., Ltd. 5.00 4.50 4.00 3.50 3.00 -40℃ 2.50 +25℃ 2.00 +85℃ 1.50 1.00 0.50 0.00 2.7V 3.0V 3.3V 4.5V 5.0V 5.5V Figure 7.21 STOP (IDD5) Current...
  • Page 47: Memory

    MC96F6432S ABOV Semiconductor Co., Ltd. Memory The MC96F6432S addresses two separate address memory stores:Program memory and Data memory. The logical separation of Program and Data memory allows Data memory to be accessed by 8-bit addresses, which makes the 8- bit CPU access the data memory more rapidly. Nevertheless, 16-bit Data memory addresses can also be generated through the DPTR register.
  • Page 48 MC96F6432S ABOV Semiconductor Co., Ltd. FFFFH 7FFFH 32Kbytes 0000H Figure 8.1 Program Memory NOTE) 32Kbytes Including Interrupt Vector Region...
  • Page 49: Data Memory

    MC96F6432S ABOV Semiconductor Co., Ltd. Data Memory Upper 128bytes Special Function Registers Internal RAM 128bytes (Indirect Addressing) (Direct Addressing) Lower 128bytes Internal RAM (Direct or Indirect Addressing) Figure 8.2 Data Memory Map The internal data memory space is divided into three blocks, which are generally referred to as the lower 128bytes, upper 128bytes, and SFR space.
  • Page 50 MC96F6432S ABOV Semiconductor Co., Ltd. 7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70 6F 6E 6D 6C 6B 6A 69 68 67 66 65 64 63 62 61 60 5F 5E 5D 5C 5B 5A 59 58...
  • Page 51: External Data Memory

    MC96F6432S ABOV Semiconductor Co., Ltd. External Data Memory MC96F6432S has 768bytes XRAM and XSFR. This area has no relation with RAM/FLASH. It can be read and written to through SFR with 8-bit unit. 107FH Extended Special Function Registers 128bytes (Indirect Addressing)
  • Page 52: Sfr Map

    MC96F6432S ABOV Semiconductor Co., Ltd. SFR Map 8.4.1 SFR Map Summary Reserved M8051 compatible 00H/8H 01H/9H 02H/0AH 03H/0BH 04H/0CH 05H/0DH 06H/0EH 07H/0FH – 0F8H FSADRH FSADRM FSADRL FIDR FMCR P5FSR 0F0H USI1ST1 USI1ST2 USI1BD USI1SDHR USI1DR USI1SCLR USI1SCHR 0E8H RSTFR...
  • Page 53 MC96F6432S ABOV Semiconductor Co., Ltd. 00H/8H 01H/9H 02H/0AH 03H/0BH 04H/0CH 05H/0DH 06H/0EH 07H/0FH – – – – – – – – 1078H – – – – – – – – 1070H – – – – – – – – 1068H –...
  • Page 54: Sfr Map

    MC96F6432S ABOV Semiconductor Co., Ltd. 8.4.2 SFR Map @Reset Address Function Symbol P0 Data Register Stack Pointer Data Pointer Register Low Data Pointer Register High Data Pointer Register Low 1 DPL1 Data Pointer Register High 1 DPH1 – – Low Voltage Indicator Control Register LVICR –...
  • Page 55 MC96F6432S ABOV Semiconductor Co., Ltd. @Reset Address Function Symbol – – – – P4 Data Register P0 Direction Register P0IO – – – – Extended Operation Register – – – – P4 Pull-up Resistor Selection Register P4PU External Interrupt Polarity 0 Low Register...
  • Page 56 MC96F6432S ABOV Semiconductor Co., Ltd. @Reset Address Function Symbol External Interrupt Flag 0 Register EIFLAG0 P3 Direction Register P3IO – – Timer 2 Control Low Register T2CRL – – – – Timer 2 Control High Register T2CRH Timer 2 A Data Low Register...
  • Page 57 MC96F6432S ABOV Semiconductor Co., Ltd. @Reset Address Function Symbol Accumulator Register – USI0 Status Register 1 USI0ST1 USI0 Status Register 2 USI0ST2 USI0 Baud Rate Generation Register USI0BD USI0 SDA Hold Time Register USI0SHDR USI0 Data Register USI0DR USI0 SCL Low Period Register...
  • Page 58 MC96F6432S ABOV Semiconductor Co., Ltd. @Reset Address Function Symbol – 1000H Timer 3 Control Register T3CR Timer 3 Counter Register T3CNT 1001H Timer 3 Data Register T3DR Timer 3 Capture Data Register T3CAPR 1002H Timer 4 Control Register T4CR 1003H...
  • Page 59: Sfr Map

    MC96F6432S ABOV Semiconductor Co., Ltd. 8.4.3 SFR Map ACC (Accumulator Register): E0H Initial value: 00H Accumulator B (B Register): F0H Initial value: 00H B Register SP (Stack Pointer): 81H Initial value: 07H Stack Pointer DPL (Data Pointer Register Low): 82H...
  • Page 60 MC96F6432S ABOV Semiconductor Co., Ltd. DPL1 (Data Pointer Register Low 1): 84H DPL1 Initial value: 00H DPL1 Data Pointer Low 1 DPH1 (Data Pointer Register High 1): 85H DPH1 Initial value: 00H DPH1 Data Pointer High 1 PSW (Program Status Word Register): D0H...
  • Page 61: O Ports

    MC96F6432S ABOV Semiconductor Co., Ltd. I/O Ports I/O Ports The MC96F6432S has tengroups of I/O ports (P0 ~ P5). Each port can be easily configured by software as I/O pin, internal pull up and open-drain pin to meet various system configurations and design requirements. Also P0 includes function that can generate interrupt according to change of state of the pin.
  • Page 62: Port Function Selection Register (Pxfsr)

    MC96F6432S ABOV Semiconductor Co., Ltd. 9.2.6 Port Function Selection Register (PxFSR) These registers define alternative functions of ports. Please remember that these registers should be set properly for alternative port function. A reset clears the PxFSR register to ‘00H’, which makes all pins to normal I/O ports.
  • Page 63: P0 Port

    MC96F6432S ABOV Semiconductor Co., Ltd. P0 Port 9.3.1 P0 Port Description P0 is 8-bit I/O port. P0 control registers consist of P0 data register (P0), P0 direction register (P0IO), debounce enable register (P0DB), P0 pull-up resistor selection register (P0PU), and P0 open-drain selection register (P0OD).
  • Page 64 MC96F6432S ABOV Semiconductor Co., Ltd. P0OD (P0 Open-drain Selection Register): 91H P07OD P06OD P05OD P04OD P03OD P02OD P01OD P00OD Initial value: 00H P0OD[7:0] Configure Open-drain of P0 Port Push-pull output Open-drain output P0DB (P0 De-bounce Enable Register): DEH DBCLK1 DBCLK0...
  • Page 65 MC96F6432S ABOV Semiconductor Co., Ltd. P0FSRH (Port 0 Function Selection High Register): D3H – – P0FSRH5 P0FSRH4 P0FSRH3 P0FSRH2 P0FSRH1 P0FSRH0 – – Initial value: 00H P0FSRH[5:4] P07 Function Select P0FSRH5 P0FSRH4 Description I/O Port (EINT5 function possible when input)
  • Page 66 MC96F6432S ABOV Semiconductor Co., Ltd. P0FSRL (Port 0 Function Selection Low Register): D2H – P0FSRL6 P0FSRL5 P0FSRL4 P0FSRL3 P0FSRL2 P0FSRL1 P0FSRL0 – Initial value: 00H P0FSRL[6:5] P04 Function Select P0FSRL6 P0FSRL5 Description I/O Port(EINT2 function possible when input) SEG25 Function...
  • Page 67: P1 Port

    MC96F6432S ABOV Semiconductor Co., Ltd. P1 Port 9.4.1 P1 Port Description P1 is 8-bit I/O port. P1 control registers consist of P1 data register (P1), P1 direction register (P1IO), debounce enable register (P15DB), P1 pull-up resistor selection register (P1PU), andP1 open-drain selection register (P1OD) . Refer to the port function selection registers for the P1 function selection.
  • Page 68 MC96F6432S ABOV Semiconductor Co., Ltd. P1OD (P1 Open-drain Selection Register): 92H P17OD P16OD P15OD P14OD P13OD P12OD P11OD P10OD Initial value: 08H P1OD[7:0] Configure Open-drain of P1 Port Push-pull output Open-drain output P15DB (P1/P5 De-bounce Enable Register): DFH – –...
  • Page 69 MC96F6432S ABOV Semiconductor Co., Ltd. P1FSRH (Port 1 Function Selection High Register): D5H P1FSRH7 P1FSRH6 P1FSRH5 P1FSRH4 P1FSRH3 P1FSRH2 P1FSRH1 P1FSRH0 Initial value: 00H P1FSRH[7:6] P17 Function Select P1FSRH7 P1FSRH6 Description I/O Port(EINT6/SS2 function possible when input) SEG21 Function AN6 Function...
  • Page 70 MC96F6432S ABOV Semiconductor Co., Ltd. P1FSRL (Port 1 Function Selection Low Register): D4H P1FSRL7 P1FSRL6 P1FSRL5 P1FSRL4 P1FSRL3 P1FSRL2 P1FSRL1 P1FSRL0 Initial value: 00H P1FSRL[7:6] P13 Function Select P1FSRL7 P1FSRL6 Description I/O Port(EC1 function possible when input) SEG17 Function AN10 Function...
  • Page 71: P2 Port

    MC96F6432S ABOV Semiconductor Co., Ltd. P2 Port 9.5.1 P2 Port Description P2 is 8-bit I/O port. P2 control registers consist of P2 data register (P2), P2 direction register (P2IO), P2 pull-up resistor selection register (P2PU) andP2 open-drain selection register (P2OD).Refer to the port function selection registers for the P2 function selection.
  • Page 72 MC96F6432S ABOV Semiconductor Co., Ltd. P2PU (P2 Pull-up Resistor Selection Register): AEH P27PU P26PU P25PU P24PU P23PU P22PU P21PU P20PU Initial value: 00H P2PU[7:0] Configure Pull-up Resistor of P2 Port Disable Enable P2OD (P2 Open-drain Selection Register): 93H P27OD P26OD...
  • Page 73 MC96F6432S ABOV Semiconductor Co., Ltd. P2FSRH (Port 2 Function Selection High Register): D7H – – – – P2FSRH3 P2FSRH2 P2FSRH1 P2FSRH0 – – – – Initial value: 00H P2FSRH3 P27 Function select I/O Port SEG6 Function P2FSRH2 P26 Function Select...
  • Page 74: P3 Port

    MC96F6432S ABOV Semiconductor Co., Ltd. P3 Port 9.6.1 P3 Port Description P3 is 8-bit I/O port. P3 control registers consist of P3 data register (P3), P3 direction register (P3IO) and P3 pull-up resistor selection register (P3PU). Refer to the port function selection registers for the P3 function selection.
  • Page 75 MC96F6432S ABOV Semiconductor Co., Ltd. P3FSR (Port 3 Function Selection Register): EEH P3FSR7 P3FSR6 P3FSR5 P3FSR4 P3FSR3 P3FSR2 P3FSR1 P3FSR0 Initial value: 00H P3FSR7 P37 Function select I/O Port COM0 Function P3FSR6 P36 Function Select I/O Port COM1 Function P3FSR5...
  • Page 76: P4 Port

    MC96F6432S ABOV Semiconductor Co., Ltd. P4 Port 9.7.1 P4 Port Description P4 is 4-bit I/O port. P4 control registers consist of P4 data register (P4), P4 direction register (P4IO), P4 pull-up resistor selection register (P4PU) andP4 open-drain selection register (P4OD).Refer to the port function selection registers for the P4 function selection.
  • Page 77 MC96F6432S ABOV Semiconductor Co., Ltd. P4OD (P4 Open-drain Selection Register): 94H – – – – P43OD P42OD P41OD P40OD – – – – Initial value: 00H P4OD[3:0] Configure Open-drain of P4 Port Push-pull output Open-drain output P4FSR (Port 4 Function Selection Register): EFH –...
  • Page 78: P5 Port

    MC96F6432S ABOV Semiconductor Co., Ltd. P5 Port 9.8.1 P5 Port Description P5 is 6-bit I/O port. P5 control registers consist of P5 data register (P5), P5 direction register (P5IO) andP5 pull-up resistor selection register (P5PU) . Refer to the port function selection registers for the P5 function selection.
  • Page 79 MC96F6432S ABOV Semiconductor Co., Ltd. P5FSR (Port 5 Function Selection Register): FFH – – P5FSR5 P5FSR4 P5FSR3 P5FSR2 P5FSR1 P5FSR0 – – Initial value: 00H P5FSR5 P54 Function Select I/O Port(EINT10 function possible when input) SXOUT Function P5FSR[4:3] P53 Function Select...
  • Page 80: Interrupt Controller

    MC96F6432S ABOV Semiconductor Co., Ltd. Interrupt Controller 10.1 Overview The MC96F6432S supports up to 23 interrupt sources. The interrupts have separate enable register bits associated with them, allowing software control. They can also have four levels of priority assigned to them. The non-maskable interrupt source is always enabled with a higher priority than any other interrupt source, and is not controllable by software.
  • Page 81 MC96F6432S ABOV Semiconductor Co., Ltd. Interrupt Highest Lowest Group 0 (Bit0) Interrupt 0 Interrupt 6 Interrupt 12 Interrupt 18 Highest 1 (Bit1) Interrupt 1 Interrupt 7 Interrupt 13 Interrupt 19 2 (Bit2) Interrupt 2 Interrupt 8 Interrupt 14 Interrupt 20...
  • Page 82: External Interrupt

    MC96F6432S ABOV Semiconductor Co., Ltd. 10.2 External Interrupt The external interrupt on INT0, INT1, INT5, INT6 and INT11 pins receivevarious interrupt request depending on the external interrupt polarity 0 high/low register (EIPOL0H/L) and external interrupt polarity 1 register (EIPOL1) as shown in Figure 10.1.
  • Page 83: Block Diagram

    MC96F6432S ABOV Semiconductor Co., Ltd. 10.3 Block Diagram EIPOL1 EIFLAG1.1 EINT10 FLAG10 EIFLAG1.2 Priority High EINT11 FLAG11 USI1 I2C I2C1IFR USI1 Rx USI1 Tx EIPOL0H/L EIFLAG0.0 EINT0 FLAG0 EIFLAG0.1 EINT1 FLAG1 EIFLAG0.2 EINT2 FLAG2 EIFLAG0.3 EINT3 FLAG3 EIFLAG0.4 EINT4 FLAG4 EIFLAG0.5...
  • Page 84: Interrupt Vector Table

    MC96F6432S ABOV Semiconductor Co., Ltd. 10.4 Interrupt Vector Table The interrupt controller supports 24 interrupt sources as shown in the Table 10-2. When interrupt is served, long call instruction (LCALL) is executed and program counter jumps to the vector address. All interrupt requests have their own priority order.
  • Page 85: Interrupt Sequence

    MC96F6432S ABOV Semiconductor Co., Ltd. 10.5 Interrupt Sequence An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to ‘0’ by a reset or an instruction. Interrupt acceptance always generates at last cycle of the instruction. So instead of fetching the current instruction, CPU executes internally LCALL instruction and saves the PC at stack.
  • Page 86: Effective Timing After Controlling Interrupt Bit

    MC96F6432S ABOV Semiconductor Co., Ltd. 10.6 Effective Timing after Controlling Interrupt Bit Case a) Control Interrupt Enable Register (IE, IE1, IE2, IE3) Interrupt Enable Register command After executing IE set/clear, enable register is effective. Next Instruction Next Instruction Figure 10.4...
  • Page 87: Multi Interrupt

    MC96F6432S ABOV Semiconductor Co., Ltd. 10.7 Multi Interrupt If two requests of different priority levels are received simultaneously, the request of higher priority level is served first. If more than one interrupt request are received, the interrupt polling sequence determines which request is served first by hardware.
  • Page 88: Interrupt Enable Accept Timing

    MC96F6432S ABOV Semiconductor Co., Ltd. 10.8 Interrupt Enable Accept Timing Max. 4 Machine Cycle 4 Machine Cycle System Clock Interrupt goes Active Interrupt Interrupt Processing Latched Interrupt Routine : LCALL & LJMP Figure 10.7 Interrupt Response Timing Diagram 10.9 Interrupt Service Routine Address...
  • Page 89: Interrupt Timing

    MC96F6432S ABOV Semiconductor Co., Ltd. 10.11 Interrupt Timing Interrupt sampled here CLP2 CLP1 CLP2 C1P1 C1P2 C2P1 C2P2 SCLK INT_SRC INTR_ACK LAST_CYC INTR_LCALL 8-bit interrupt Vector INT_VEC {8’h00, INT_VEC} PROGA Figure 10.10 Timing Chart of Interrupt Acceptance and Interrupt Return Instruction Interrupt sources are sampled at the last cycle of a command.
  • Page 90: External Interrupt Flag Register (Eiflag0, Eiflag1)

    MC96F6432S ABOV Semiconductor Co., Ltd. 10.12.3 External Interrupt Flag Register (EIFLAG0, EIFLAG1) The external interrupt flag 0 register (EIFLAG0) and external interrupt flag 1 register (EIFLAG1) areset to ‘1’ when the external interrupt generating condition is satisfied. The flag is cleared when the interrupt service routine is executed.
  • Page 91: Register Description For Interrupt

    MC96F6432S ABOV Semiconductor Co., Ltd. 10.12.7 Register Description for Interrupt IE (Interrupt Enable Register): A8H – INT5E INT4E INT3E INT2E INT1E INT0E – Initial value: 00H Enable or Disable All Interrupt bits All Interrupt disable All Interrupt enable INT5E Enable or Disable External Interrupt 0 ~ 7 (EINT0 ~ EINT7)
  • Page 92 MC96F6432S ABOV Semiconductor Co., Ltd. IE1 (Interrupt Enable Register 1): A9H – – – INT11E INT10E INT9E INT8E INT6E – – – Initial value: 00H INT11E Enable or Disable External Interrupt 12 (EINT12) Disable Enable INT10E Enable or Disable USI0Tx Interrupt...
  • Page 93 MC96F6432S ABOV Semiconductor Co., Ltd. IE2 (Interrupt Enable Register 2): AAH –- – INT17E INT16E INT15E INT14E INT13E INT12E – – Initial value: 00H INT17E Enable or Disable Timer 4 Interrupt Disable Enable INT16E Enable or Disable Timer 3 Match Interrupt...
  • Page 94 MC96F6432S ABOV Semiconductor Co., Ltd. IP (Interrupt Priority Register): B8H – – – – Initial value :00H IP1 (Interrupt Priority Register 1): F8H – – IP15 IP14 IP13 IP12 IP11 IP10 – – Initial value :00H IP[5:0], Select Interrupt Group Priority...
  • Page 95 MC96F6432S ABOV Semiconductor Co., Ltd. EIFLAG0 (External Interrupt Flag0 Register): C0H FLAG7 FLAG6 FLAG5 FLAG4 FLAG3 FLAG2 FLAG1 FLAG0 Initial value :00H When an External Interrupt 0-7 is occurred, the flag becomes ‘1’.The flag is cleared EIFLAG0[7:0] only by writing ‘0’ to the bit. So, the flag should be cleared by software.
  • Page 96 MC96F6432S ABOV Semiconductor Co., Ltd. EIFLAG1 (External Interrupt Flag 1 Register): A6H – T0OVIFR T0IFR T3IFR FLAG12 FLAG11 FLAG10 FLAG8 – Initial value :00H When T0 overflow interrupt occurs, this bit becomes ‘1’. For clearing bit, write‘0’ to T0OVIFR this bit or automatically clear by INT_ACK signal. Writing “1” has no effect.
  • Page 97: Peripheral Hardware

    MC96F6432S ABOV Semiconductor Co., Ltd. Peripheral Hardware 11.1 Clock Generator 11.1.1 Overview As shown in Figure 11.1, the clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and the peripheral hardware. It contains main/sub-frequency clock oscillator. The main/sub clock operation can be easily obtained by attaching a crystal between the XIN/SXIN and XOUT/SXOUT pin, respectively.
  • Page 98: Block Diagram

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.1.2 Block Diagram Main OSC XOUT STOP Mode IRCS[2:0] XCLKE System SCLK Clock Gen. (Core, System, Clock Peripheral) Change Internal RC OSC (16MHz) 1/16 Stabilization Time 1/32 Generation BITCK[1:0] STOP Mode overflow IRCE WDT clock...
  • Page 99: Register Map

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.1.3 Register Map Name Address Direction Default Description SCCR System and Clock Control Register OSCCR Oscillator Control Register Clock Generator Register Map Table 11.1 11.1.4 Clock Generator Register Description The clock generatorregister uses clock control for system operation. The clock generation consists of System and clock control register and oscillator control register.
  • Page 100 MC96F6432S ABOV Semiconductor Co., Ltd. OSCCR (Oscillator Control Register): C8H – – IRCS2 IRCS1 IRCS0 IRCE XCLKE SCLKE – – Initial value: 08H IRCS[2:0] Internal RC Oscillator Post-divider Selection IRCS2 IRCS1 IRCS0 Description INT-RC/32 (0.5MHz) INT-RC/16 (1MHz) INT-RC/8 (2MHz) INT-RC/4 (4MHz)
  • Page 101: Basic Interval Timer

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.2 Basic Interval Timer 11.2.1 Overview The MC96F6432S has one 8-bit basic interval timer that is free-run and can’t stop. Block diagram is shown in Figure 11.2. In addition, the basic interval timer generates the time base for watchdog timer counting. It also provides a basic interval timer interrupt (BITIFR).
  • Page 102: Basic Interval Timer Register Description

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.2.4 Basic Interval Timer Register Description The basicinterval timer register consists of basic interval timer counter register (BITCNT) and basic interval timer control register (BITCR). If BCLR bit is set to ‘1’, BITCNT becomes ‘0’ and then counts up. After 1 machine cycle, BCLR bit is cleared to ‘0’...
  • Page 103: Watch Dog Timer

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.3 Watch Dog Timer 11.3.1 Overview The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or something like that, and resumes the CPU to the normal state. The watchdog timer signal for malfunction detection can be used as either a CPUreset or an interrupt request.
  • Page 104: Block Diagram

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.3.3 Block Diagram clear WDT Clock To RESET WDTCNT Circuit WDTEN To interrupt WDTIFR block clear WDTDR INT_ACK WDTCL WDTRSON WDTCR Figure 11.4 Watch Dog Timer Block Diagram 11.3.4 Register Map Name Address Direction Default...
  • Page 105: Register Description For Watch Dog Timer

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.3.6 Register Description for Watch Dog Timer WDTCNT (Watch Dog Timer Counter Register: Read Case): 8EH WDTCNT 7 WDTCNT 6 WDTCNT 5 WDTCNT 4 WDTCNT3 WDTCNT 2 WDTCNT 1 WDTCNT 0 Initial value: 00H WDTCNT[7:0]...
  • Page 106: Watch Timer

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.4 Watch Timer 11.4.1 Overview The watch timer has the function for RTC (Real Time Clock) operation.It is generally used for RTC design.The internal structure of the watch timer consists of the clock source select circuit, timer counter circuit, output select circuit, and watch timer control register.
  • Page 107: Register Map

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.4.3 Register Map Name Address Direction Default Description WTCNT Watch Timer Counter Register WTDR Watch Timer Data Register WTCR Watch Timer Control Register Watch Timer Register Map Table 11.4 11.4.4 Watch Timer Register Description The watch timer register consists of watch timer counter register (WTCNT), watch timer data register (WTDR), and watch timer controlregister (WTCR).
  • Page 108 MC96F6432S ABOV Semiconductor Co., Ltd. WTCR (Watch Timer Control Register): 96H – – WTEN WTIFR WTIN1 WTIN0 WTCK1 WTCK0 – – Initial value: 00H WTEN Control Watch Timer Disable Enable When WT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or WTIFR automatically clear by INT_ACK signal.
  • Page 109: Timer 0

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.5 Timer 0 11.5.1 Overview The 8-bit timer 0 consists of multiplexer, timer 0 counter register, timer 0 data register, timer 0 capture data register and timer 0 control register (T0CNT, T0DR, T0CDR, T0CR). It has three operating modes: −...
  • Page 110: 8-Bit Timer/Counter Mode

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.5.2 8-bit Timer/Counter Mode The 8-bit timer/counter mode is selected by control register as shown in Figure 11.6. The 8-bit timer have counter and data register. The counter register is increased by internal or external clock input.
  • Page 111: 8-Bit Pwm Mode

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.5.3 8-bit PWM Mode The timer 0 has a high speed PWM (Pulse Width Modulation) function. In PWM mode, T0O/PWM0O pin outputs up to 8-bit resolution PWM output. This pin should be configured as a PWM output by setting the T0O/PWM0O function by P5FSR[4:3] bits.
  • Page 112 MC96F6432S ABOV Semiconductor Co., Ltd. PWM Mode(T0MS = 01b) Set T0EN Timer 0 clock T0CNT T0DR T0 Overflow Interrupt 1. T0DR = 4AH T0PWM T0 Match Interrupt 2. T0DR = 00H T0PWM T0 Match Interrupt 3. T0DR = FFH T0PWM...
  • Page 113: 8-Bit Capture Mode

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.5.4 8-bit Capture Mode The timer 0 capture mode is set by T0MS[1:0] as ‘1x’. The clock source can use the internal/external clock. Basically, it has the same function as the 8-bit timer/counter mode and the interrupt occurs when T0CNT is equal to T0DR.
  • Page 114 MC96F6432S ABOV Semiconductor Co., Ltd. T0CDR Load T0CNT Value Count Pulse Period Up-count TIME Ext. EINT10 PIN Interrupt Request (FLAG10) Interrupt Interval Period Figure 11.11 Input Capture Mode Operation for Timer 0 T0CNT Interrupt Request (T0IFR) Ext. EINT10 PIN Interrupt...
  • Page 115: Block Diagram

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.5.5 Block Diagram INT_ACK Clear To interrupt T0OVIFR block fx/2 fx/4 8-bit Timer 0 Counter Match signal fx/8 Clear INT_ACK T0CNT (8Bit) fx/32 T0CC Clear fx/128 Clear fx/512 Match To interrupt T0EN T0IFR block fx/2048...
  • Page 116: Register Description For Timer/Counter 0

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.5.8 Register Description for Timer/Counter 0 T0CNT (Timer 0 Counter Register): B3H T0CNT7 T0CNT6 T0CNT5 T0CNT4 T0CNT3 T0CNT2 T0CNT1 T0CNT0 Initial value: 00H T0CNT[7:0] T0 Counter T0DR (Timer 0 Data Register): B4H T0DR7 T0DR6 T0DR5...
  • Page 117 MC96F6432S ABOV Semiconductor Co., Ltd. T0CR (Timer 0 Control Register): B2H – T0EN T0MS1 T0MS0 T0CK2 T0CK1 T0CK0 T0CC – Initial value: 00H T0EN Control Timer 0 Timer 0 disable Timer 0 enable T0MS[1:0] Control Timer 0 Operation Mode T0MS1...
  • Page 118: Timer 1

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.6 Timer 1 11.6.1 Overview The 16-bit timer 1 consists of multiplexer, timer 1 A data register high/low, timer 1 B data register high/low and timer 1 control registerhigh/low (T1ADRH, T1ADRL, T1BDRH, T1BDRL, T1CRH, T1CRL).
  • Page 119 MC96F6432S ABOV Semiconductor Co., Ltd. ADDRESS:BBH – – – – T1EN T1MS1 T1MS0 T1CC T1CRH INITIAL VALUE : 0000_0000B – – – – ADDRESS:BAH – T1CK2 T1CK1 T1CK0 T1IFR T1POL T1ECE T1CNTR T1CRL INITIAL VALUE : 0000_0000B – 16-bit A Data Register...
  • Page 120: 16-Bit Capture Mode

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.6.3 16-bit Capture Mode The 16-bit timer 1 capture mode is set by T1MS[1:0] as ‘01’. The clock source can use the internal/external clock. Basically, it has the same function as the 16-bit timer/counter mode and the interrupt occurs when T1CNTH/T1CNTL is equal to T1ADRH/T1ADRL.
  • Page 121 MC96F6432S ABOV Semiconductor Co., Ltd. T1BDRH/L Load T1CNTH/L Value Count Pulse Period Up-count TIME Ext. EINT11 PIN Interrupt Request (FLAG11) Interrupt Interval Period Figure 11.17 Input Capture Mode Operation for Timer 1 FFFF FFFF T1CNTH/L Interrupt Request (T1IFR) Ext. EINT11 PIN...
  • Page 122: 16-Bit Ppg Mode

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.6.4 16-bit PPG Mode The timer 1 has a PPG (Programmable Pulse Generation) function. In PPG mode, T1O/PWM1O pin outputs up to 16-bit resolution PWM output. This pin should be configured as a PWM output by settingP1FSRL[5:4] to ‘11’. The period of the PWM output is determined by the T1ADRH/T1ADRL.
  • Page 123 MC96F6432S ABOV Semiconductor Co., Ltd. Repeat Mode(T1MS = 11b) and "Start High"(T1POL = 0b). Clear and Start Set T1EN Timer 1 clock Counter T1ADRH/L T1 Interrupt 1. T1BDRH/L(5) < T1ADRH/L PWM1O B Match A Match 2. T1BDRH/L >= T1ADRH/L PWM1O A Match 3.
  • Page 124: Block Diagram

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.6.5 Block Diagram 16-bit A Data Register T1ADRH/T1ADRL A Match Reload T1CC T1EN To Timer 2 T1CK[2:0] block T1ECE INT_ACK Buffer Register A Clear Edge A Match Detector To interrupt T1IFR block T1EN fx/1 Comparator...
  • Page 125: Timer/Counter 1 Register Description

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.6.7 Timer/Counter 1 Register Description The timer/counter 1 register consists of timer 1 Adata high register (T1ADRH), timer 1 Adata low register (T1ADRL), timer 1 Bdata high register (T1BDRH), timer 1 Bdata low register (T1BDRL), timer 1controlHigh register (T1CRH) and timer 1controllow register (T1CRL).
  • Page 126 MC96F6432S ABOV Semiconductor Co., Ltd. T1CRH (Timer 1ControlHigh Register): BBH – – – – T1EN T1MS1 T1MS0 T1CC – – – – Initial value: 00H T1EN Control Timer 1 Timer 1 disable Timer 1 enable (Counter clear and start) T1MS[1:0]...
  • Page 127 MC96F6432S ABOV Semiconductor Co., Ltd. T1CRL (Timer 1ControlLow Register): BAH – T1CK2 T1CK1 T1CK0 T1IFR T1POL T1ECE T1CNTR – Initial value: 00H T1CK[2:0] Select Timer 1 clock source. fx is main system clock frequency T1CK2 T1CK1 T1CK0 Description fx/2048 fx/512...
  • Page 128: Timer 2

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.7 Timer 2 11.7.1 Overview The 16-bit timer 2 consists of multiplexer, timer 2 A data high/low register, timer 2 B data high/low register and timer 2 control high/low register (T2ADRH, T2ADRL, T2BDRH, T2BDRL, T2CRH, and T2CRL).
  • Page 129: 16-Bit Timer/Counter Mode

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.7.2 16-bit Timer/Counter Mode The 16-bit timer/counter mode is selected by control register as shown in Figure 11.22. The 16-bit timer have counter and data register. The counter register is increased by internal or timer 1 A match clock input.
  • Page 130 MC96F6432S ABOV Semiconductor Co., Ltd. Match with T2ADRH/L T2CNTH/L Value Count Pulse Period Up-count TIME Interrupt Period x (n+1) Timer 2 (T2IFR) Interrupt Occur Occur Occur Interrupt Interrupt Interrupt Figure 11.23 16-bit Timer/Counter 2 Example...
  • Page 131: 16-Bit Capture Mode

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.7.3 16-bit Capture Mode The timer 2 capture mode is set by T2MS[1:0] as ‘01’. The clock source can use the internal clock. Basically, it has the same function as the 16-bit timer/counter mode and the interrupt occurs when T2CNTH/T2CNTLis equal to T2ADRH/T2ADRL.
  • Page 132 MC96F6432S ABOV Semiconductor Co., Ltd. T2BDRH/L Load T2CNTH/L Value Count Pulse Period Up-count TIME Ext. EINT12 PIN Interrupt Request (FLAG12) Interrupt Interval Period Figure 11.25 Input Capture Mode Operation for Timer 2 FFFF FFFF T2CNTH/L Interrupt Request (T2IFR) Ext. EINT12 PIN...
  • Page 133: 16-Bit Ppg Mode

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.7.4 16-bit PPG Mode The timer 2 has a PPG (Programmable Pulse Generation) function. In PPG mode, the T2O/PWM2O pin outputs up to 16-bit resolution PWM output. This pin should be configured as a PWM output by set P1FSRL[3:2] to ‘11’. The period of the PWM output is determined by the T2ADRH/T2ADRL.
  • Page 134 MC96F6432S ABOV Semiconductor Co., Ltd. Repeat Mode(T2MS = 11b) and "Start High"(T2POL = 0b). Clear and Start Set T2EN Timer 2 clock Counter T2ADRH/L T2 Interrupt 1. T2BDRH/L(5) < T2ADRH/L PWM2O B Match A Match 2. T2BDRH/L >= T2ADRH/L PWM2O A Match 3.
  • Page 135: Block Diagram

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.7.5 Block Diagram 16-bit A Data Register T2ADRH/T2ADRL A Match Reload T2CC T2CK[2:0] T2EN INT_ACK Buffer Register A Clear T1 A Match A Match To interrupt T2IFR block T2EN fx/1 Comparator fx/2 A Match Clear...
  • Page 136: Timer/Counter 2 Register Description

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.7.7 Timer/Counter 2 Register Description The timer/counter 2 register consists of timer 2 A data high register (T2ADRH), timer 2 A data low register (T2ADRL), timer 2 B data high register (T2BDRH), timer 2 B data low register (T2BDRL), timer 2 control high register (T2CRH) and timer 2 control low register (T2CRL).
  • Page 137 MC96F6432S ABOV Semiconductor Co., Ltd. T2CRH (Timer 2ControlHigh Register): C3H – – – – T2EN T2MS1 T2MS0 T2CC – – – – Initial value: 00H T2EN Control Timer 2 Timer 2 disable Timer 2 enable (Counter clear and start) T2MS[1:0]...
  • Page 138 MC96F6432S ABOV Semiconductor Co., Ltd. T2CRL (Timer 2ControlLow Register): CAH – – T2CK2 T2CK1 T2CK0 T2IFR T2POL T2CNTR – – Initial value: 00H T2CK[2:0] Select Timer 2 clock source. fx is main system clock frequency T2CK2 T2CK1 T2CK0 Description fx/512...
  • Page 139: Timer 3, 4

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.8 Timer 3, 4 11.8.1 Overview Timer 3 and timer 4 can be used either two 8-bit timer/counter or one 16-bit timer/counter with combine them.Each 8- bit timer/event counter module has multiplexer, comparator, 8-bit timer data register, 8-bit counter register, control register and capture data register(T3CNT, T3DR, T3CAPR, T3CR, T4CNT, T4DR, T4CAPR, and T4CR).
  • Page 140: 8-Bit Timer/Counter 3, 4 Mode

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.8.2 8-bit Timer/Counter 3, 4 Mode The 8-bit timer/counter mode is selected by control register as shown in Figure 11.30. The two 8-bit timers have each counter and data register. The counter register is increased by internal or external clock input.Timer 3 can use the input clock with one of 2, 4, 8, 32, 128, 512, 2048 and EC3prescaler division rates...
  • Page 141: 16-Bit Timer/Counter 3 Mode

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.8.3 16-bit Timer/Counter 3 Mode The 16-bit timer/counter mode is selected by control register as shown in Figure 11.31. The 16-bit timer have counter and data register. The counter register is increased by internal or external clock input.
  • Page 142: 8-Bit Timer 3, 4 Capture Mode

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.8.4 8-bit Timer 3, 4 Capture Mode The 8-bit Capture 3 and 4 mode is selected by control register as shown in Figure 11.32. The timer 3, 4 capture mode is set by T3MS, T4MS as ‘1’. The clock source can use the internal/external clock.
  • Page 143 MC96F6432S ABOV Semiconductor Co., Ltd. ADDRESS:1000H (ESFR) – T3EN T3MS T3CK2 T3CK1 T3CK0 T3CN T3ST T3CR INITIAL VALUE : 0000_0000B – ADDRESS:1002H (ESFR) 16BIT T4MS T4CN T4ST T4CK3 T4CK2 T4CK1 T4CK0 T4CR INITIAL VALUE : 0000_0000B FLAG0 To interrupt (EIFLAG0.1)
  • Page 144: 16-Bit Timer 3 Capture Mode

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.8.5 16-bit Timer 3 Capture Mode The 16-bit Capture mode is selected by control register as shown in Figure 11.33. The 16-bit capture mode is the same operation as 8-bit capture mode, except that the timer register uses 16 bits. The 16-bit timer 3 capture mode is set by T3MS, T4MS as ‘1’.
  • Page 145: 10-Bit Timer 4 Pwm Mode

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.8.6 10-bit Timer 4 PWM Mode The timer 4 has a high speed PWM (Pulse Width Modulation) function. In PWM mode, the 6-channel pins output up to 10-bit resolution PWM output. This pin should be configured as a PWM output by set PWM4E to ‘1’. When the value of 2-bit +T4CNT and T4PPRH/L are identical in timer 4, a period match signal is generated and the interrupt of timer 4 occurs.
  • Page 146 MC96F6432S ABOV Semiconductor Co., Ltd. ADDRESS:1002H (ESFR) 16BIT T4MS T4CN T4ST T4CK3 T4CK2 T4CK1 T4CK0 T4CR INITIAL VALUE : 0000_0000B ADDRESS:1003H (ESFR) PWM4E ESYNC BMOD PHLT UPDT UALL NOPS1 NOPS0 T4PCR1 INITIAL VALUE : 0000_0000B ADDRESS:1004H (ESFR) – FORCA PAAOE PABOE PBAOE PBBOE PCAOE PCBOE...
  • Page 147 MC96F6432S ABOV Semiconductor Co., Ltd. ADDRESS:1002H (ESFR) 16BIT T4MS T4CN T4ST T4CK3 T4CK2 T4CK1 T4CK0 T4CR INITIAL VALUE : 0000_0000B ADDRESS:1003H (ESFR) PWM4E ESYNC BMOD PHLT UPDT UALL NOPS1 NOPS0 T4PCR1 INITIAL VALUE : 0000_0000B ADDRESS:1004H (ESFR) – FORCA PAAOE PABOE PBAOE PBBOE PCAOE PCBOE...
  • Page 148 MC96F6432S ABOV Semiconductor Co., Ltd. Source Clock T4CNT P02/PWM4AA POLAA = 1 P02/PWM4AA POLAA = 0 Duty Cycle(1+80 )X250ns = 32.25us )X250ns = 256us  3.9kHz Period Cycle(1+3FF T4PPRH(2-bit) T4PPRL(8-bit) T4CR = 00 T4PPRH = 03 T4PPRL = FF T4ADRH = 00...
  • Page 149 MC96F6432S ABOV Semiconductor Co., Ltd. Phase correction & Frequency correction On operating PWM, it is possible that it is changed the phase and the frequency by using BMOD bit (back-to-back mode) in T4PCR1 register. (Figure 1.38, Figure 11.39, Figure 11.40 referred) In the back-to-back mode, the counter of PWM repeats up/down count.
  • Page 150 MC96F6432S ABOV Semiconductor Co., Ltd. Duty, Period Update T4CNT Back-to-Back mode Duty1 Duty2 Duty3 Output Period1 Period2 Period3 Interrupt Timing Overflow INT. Overflow INT. Bottom INT. Overflow INT. Figure 11.40 Example of Phase Correction and Frequency correction of PWM External Sync If using ESYNC bit of T4PCR1 register, it is possible to synchronize the output of PWM from external signal.
  • Page 151 MC96F6432S ABOV Semiconductor Co., Ltd. FORCE Drive ALL Channel with A-ch mode If FORCA bit sets to ‘1’, it is possible to enable or disable all PWM output pins through PWM outputs which occur from A-ch duty counter. It is noted that the inversion outputs of A, B, C channel have the same A-ch output waveform.
  • Page 152 MC96F6432S ABOV Semiconductor Co., Ltd. FORCE 6-Ch Drive If FORCA bit sets to ‘0’, it is possible to enable or disable PWM output pin and inversion output pin generated through the duty counter of each channel. The inversion output is the reverse phase of the PWM output. A AA/AB output of the A-channel duty register, a BA/BB output of the B-channel duty register, a CA/CB output of the C-channel duty register are controlled respectively.
  • Page 153 MC96F6432S ABOV Semiconductor Co., Ltd. PWM output Delay If using the T4DLYA, T4DLYB, and T4DLYC register, it can delay PWM output based on the rising edge. At that time, it does not change the falling edge, so the duty is reduced as the time delay. In POLAA/BA/CA setting to ‘0’, the delay is applied to the falling edge.
  • Page 154 MC96F6432S ABOV Semiconductor Co., Ltd. ADDRESS :1004H (ESFR) T4PCR2 FORCA PAAOE PABOE PBAOE PBBOE PCAOE PCBOE INITIAL VALUE : 0-00_0000B ADDRESS : 1005H (ESFR) T4PCR3 HZCLR POLBO POLAA POLAB POLBA POLBB POLCA POLCB INITIAL VALUE : 0000_0000B ADDRESS : 1010H (ESFR)
  • Page 155: Block Diagram

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.8.7 Block Diagram FLAG0 To interrupt (EIFLAG0.1) block T4MS Clear 8-bit Timer 4 Capture Register INT_ACK EINT1 T4CAPR (8Bit) EIPOL0L[3:2] 8-bit Timer 4 Data Register T4CK[3:0] T4DR (8Bit) Comparator fx/1 To interrupt fx/2 T4CN block...
  • Page 156 MC96F6432S ABOV Semiconductor Co., Ltd. T3ST fx/2 fx/4 16-bit Timer 3 Counter fx/8 Clear T4CNT/T3CNT (16Bit) INT_ACK fx/32 Clear fx/128 Clear fx/512 Match To interrupt T3CN T3IFR block fx/2048 Comparator T4DR/T3DR (16Bit) T3CK[2:0] 16-bit Timer 3 Data Register EIPOL0L[1:0] T4CAPR/T3CAPR (16Bit)
  • Page 157: Register Map

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.8.8 Register Map Name Address Direction Default Description T3CNT 1001H (ESFR) Timer 3 Counter Register T3DR 1001H (ESFR) Timer 3 Data Register T3CAPR 1001H (ESFR) Timer 3 Capture Data Register T3CR 1000H (ESFR) Timer 3 Control Register...
  • Page 158: Timer/Counter 3 Register Description

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.8.9 Timer/Counter 3 Register Description The timer/counter 3 register consists of timer 3counterregister (T3CNT), timer 3data register (T3DR), timer 3 capture data register (T3CAPR) and timer 3controlregister (T3CR). 11.8.10 Register Description for Timer/Counter 3 T3CNT (Timer 3Counter Register: Read Case, Timer mode only): 1001H (ESFR)
  • Page 159 MC96F6432S ABOV Semiconductor Co., Ltd. T3CR (Timer 3Control Register): 1000H (ESFR) – T3EN T3MS T3CK2 T3CK1 T3CK0 T3CN T3ST – Initial value: 00H T3EN Control Timer 3 Timer 3 disable Timer 3 enable T3MS Control Timer 3 Operation Mode Timer/counter mode (T3O: toggle at match)
  • Page 160: Timer/Counter 4 Register Description

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.8.11 Timer/Counter 4 Register Description The timer/counter 4 register consists of timer 4 PWM period high/low register (T4PPRH/L), timer 4 PWM A duty high/low register (T4ADRH/L), timer 4 PWM B duty high/low register (T4BDRH/L), timer 4 PWM C duty high/low...
  • Page 161 MC96F6432S ABOV Semiconductor Co., Ltd. T4BDRH (Timer 4 PWM B Duty High Register: 6-ch PWM mode only): 100DH (ESFR) – – – – – – T4BDRH1 T4BDRH0 – – – – – – Initial value: 00H T4BDRH[1:0] T4 PWM B Duty Data High Byte...
  • Page 162 MC96F6432S ABOV Semiconductor Co., Ltd. T4DLYC (Timer 4 PWM C Delay Register: 6-ch PWM mode only): 1012H (ESFR) T4DLYCA3 T4DLYCA2 T4DLYCA1 T4DLYCA0 T4DLYCB3 T4DLYCB2 T4DLYCB1 T4DLYCB0 Initial value: 00H T4DLYCA[3:0] PWM4CA Delay Data (Rising edge only) T4DLYCB[3:0] PWM4CB Delay Data (Rising edge only)
  • Page 163 MC96F6432S ABOV Semiconductor Co., Ltd. T4CR (Timer 4Control Register): 1002H (ESFR) 16BIT T4MS T4CN T4ST T4CK3 T4CK2 T4CK1 T4CK0 Initial value: 00H 16BIT Select Two 8-bit or 16-bit Mode for Timer 3/4 Two 8-bit Timer 3/4 16-bit Timer 3 T4MS...
  • Page 164 MC96F6432S ABOV Semiconductor Co., Ltd. T4PCR1 (Timer 4PWM Control Register 1): 1003H (ESFR) PWM4E ESYNC BMOD PHLT UPDT UALL NOPS1 NOPS0 Initial value: 00H PWM4E Control Timer 4 Mode Select timer/counter or capture mode of Timer 4 Select 10-bit PWM mode of Timer 4...
  • Page 165 MC96F6432S ABOV Semiconductor Co., Ltd. T4PCR2 (Timer 4PWM Control Register 2): 1004H (ESFR) – FORCA PAAOE PABOE PBAOE PBBOE PCAOE PCBOE – Initial value: 00H FORCA Control The PWM outputs Mode 6-channel mode (The PWM4xA/PWM4xB pins are output according to the T4xDR registers, respectively.
  • Page 166 MC96F6432S ABOV Semiconductor Co., Ltd. T4PCR3 (Timer 4PWM Control Register 3): 1005H (ESFR) HZCLR POLBO POLAA POLAB POLBA POLBB POLCA POLCB Initial value: 00H HZCLR High-Impedance Output Clear Bit No effect Clear high-impedance output (The PWM4xA/PWM4xB pins are back to output and this bit is automatically cleared to logic ‘0’.
  • Page 167 MC96F6432S ABOV Semiconductor Co., Ltd. T4ISR (Timer 4 Interrupt Status Register): 1006H (ESFR) – – – IOVR IBTM ICMA ICMB ICMC – – – Initial value: 00H IOVR Timer 4 Compare Match or Timer 4 Overflow Interrupt Status, Write '0' to this bit for...
  • Page 168: Buzzer Driver

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.9 Buzzer Driver 11.9.1 Overview The Buzzer consists of 8bit counter,buzzer data register (BUZDR), and buzzer control register (BUZCR). The Square Wave (61.035Hz~125.0kHz @8MHz)is outputted through P13/SEG17/AN10/EC1/BUZO pin. The buzzer dataregister (BUZDR) controls the buzzer frequency (lookat the following expression). In buzzer control register(BUZCR), BUCK[1:0] selects source clock divided by prescaler.
  • Page 169: Register Map

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.9.3 Register Map Name Address Direction Default Description BUZDR Buzzer Data Register BUZCR Buzzer Control Register Buzzer Driver Register Map Table 11.16 11.9.4 Buzzer Driver Register Description Buzzer driver consists of buzzer dataregister (BUZDR) and buzzer control register (BUZCR).
  • Page 170: Spi 2

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.10 SPI 2 11.10.1 Overview There is serial peripheral interface (SPI 2) one channel in MC96F6432S. The SPI 2 allows synchronous serial data transfer between the external serial devices. It can do Full-duplex communication by 4-wire (MOSI2, MISO2, SCK2, SS2), support master/slave mode, can select serial clock (SCK2) polarity, phase and whether LSB first data transfer or MSB first data transfer.
  • Page 171: Data Transmit / Receive Operation

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.10.3 Data Transmit / Receive Operation User can use SPI 2 for serial data communication by following step 1. Select SPI 2 operation mode(master/slave, polarity, phase) by control register SPICR. 2. When the SPI 2 is configured as a Master, it selects a Slave by SS2 signal (active low).
  • Page 172: Spi 2 Timing Diagram

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.10.5 SPI 2 Timing Diagram SCK2 (CPOL = 0) SCK2 (CPOL = 1) MISO2/MOSI2 (Output) MOSI2/MISO2 (Input) SPIIFR Figure 11.50 SPI 2 Transmit/Receive Timing Diagram at CPHA = 0 SCK2 (CPOL = 0) SCK2 (CPOL = 1)
  • Page 173: Register Map

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.10.6 Register Map Name Address Direction Default Description SPISR SPI 2 Status Register SPIDR SPI 2 Data Register SPICR SPI 2 Control Register SPI 2Register Map Table 11.17 11.10.7 SPI 2 Register Description The SPI 2 register consists of SPI 2 control register (SPICR), SPI 2 status register (SPISR) and SPI 2 data register (SPIDR) 11.10.8 Register Description for SPI 2...
  • Page 174 MC96F6432S ABOV Semiconductor Co., Ltd. SPISR (SPI 2 Status Register): B7H – – – SPIIFR WCOL SS_HIGH FXCH SSENA – – – Initial value: 00H When SPI 2 Interrupt occurs, this bit becomes ‘1’. IF SPI 2 interrupt is enable, this bit is SPIIFR auto cleared by INT_ACK signal.
  • Page 175 MC96F6432S ABOV Semiconductor Co., Ltd. SPICR (SPI 2Control Register): B5H SPIEN FLSB CPOL CPHA DSCR SCR1 SCR0 Initial value: 00H SPIEN This bit controls the SPI 2 operation Disable SPI 2 operation Enable SPI 2 operation FLSB This bit selects the data transmission sequence...
  • Page 176: 12-Bit A/D Converter

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.11 12-bit A/D Converter 11.11.1 Overview The analog-to-digital converter (A/D) allows conversion of an analog input signal to corresponding 12-bit digital value. The A/D module has eight analog inputs.The output of the multiplexeris the input into the converter which generates the result through successive approximation.
  • Page 177: Block Diagram

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.11.3 Block Diagram TRIG[2:0] ADST T1 A match signal T4 overflow event signal T4 A match event signal ADSEL[3:0] Start T4 B match event signal (Select one input pin T4 C match event signal of the assigned pins)
  • Page 178: Adc Operation

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.11.4 ADC Operation Align bit set “0” ADCO11 ADCO10 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0 ADCDRH7 ADCDRH6 ADCDRH5 ADCDRH4 ADCDRH3 ADCDRH2 ADCDRH1 ADCDRH0 ADCDRL7 ADCDRL6 ADCDRL5 ADCDRL4 ADCDRH[7:0] ADCDRL[7:4] ADCDRL[3:0] bits are “0”...
  • Page 179: Register Map

    MC96F6432S ABOV Semiconductor Co., Ltd. SET ADCCRH Select ADC Clock and Data Align Bit. SET ADCCRL ADC enable & Select AN Input Channel. Converting START Start ADC Conversion. If Conversion is completed, AFLAG is set “1” and ADC AFLAG = 1? interrupt is occurred.
  • Page 180: Register Description For Adc

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.11.7 Register Description for ADC ADCDRH (A/D Converter Data High Register):9FH ADDM11 ADDM10 ADDM9 ADDM8 ADDM7 ADDM6 ADDM5 ADDM4 ADDL11 ADDL10 ADDL9 ADDL8 Initial value: xxH ADDM[11:4] MSB align, A/D Converter High Data (8-bit) ADDL[11:8]...
  • Page 181 MC96F6432S ABOV Semiconductor Co., Ltd. ADCCRL (A/D Converter Control Low Register): 9CH STBY ADST REFSEL AFLAG ADSEL3 ADSEL2 ADSEL1 ADSEL0 Initial value: 00H STBY Control Operation of A/D (The ADC module is automatically disabled at stop mode) ADC module disable...
  • Page 182: Usi (Usart + Spi + I2C)

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.12 USI (USART + SPI + I2C) 11.12.1 Overview The USI is an acronym of USART, SPI and I2C, MC96F6432S has two USI function blocks, USI0 and USI1 are absolutely same functionally. Each USI consists of USI control register1/2/3/4, USI status register 1/2, USI baud-rate...
  • Page 183: Usin Uart Mode

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.12.2 USIn UART Mode The universal synchronous and asynchronous serial receiver and transmitter (USART) is a highly flexible serial communication device. The main features are listed below. − Full Duplex Operation (Independent Serial Receive and Transmit Registers) −...
  • Page 184: Usin Uart Block Diagram

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.12.3 USIn UART Block Diagram Master SCKn Control USInMS[1:0] SCLK USInBD (fx: System clock) To interrupt block Baud Rate Generator DBLSn WAKEIEn RXCIEn Clock Sync Logic At Stop mode WAKEn Low level RXCn detector RXDn...
  • Page 185: Usin Clock Generation

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.12.4 USIn Clock Generation USInBD DBLSn SCLK (USInBD+1) Prescaling Up-Counter txclk SCLK MASTERn Edge Sync Register USInMS[1:0] Detector SCKn CPOLn rxclk Figure 11.58 Clock Generation Block Diagram (USIn) The clock generation logic generates the base clock for the transmitter and receiver. The USIn supports fourmodes of clock operationand those are normal asynchronous,double speed asynchronous, master synchronous and slave synchronous mode.
  • Page 186: Usin External Clock (Sckn)

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.12.5 USIn External Clock (SCKn) External clocking is used in the synchronous mode of operation. External clock input from the SCKn pin is sampled by a synchronization logic to remove meta-stability. The output from the synchronization logic must be passed through an edge detector before it is used by the transmitter and receiver.
  • Page 187: Usin Uart Data Format

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.12.7 USIn UART Data format A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error detection. The USARTsupports all 30 combinations of the following as valid frame formats.
  • Page 188: Usin Uart Parity Bit

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.12.8 USIn UART Parity bit The parity bit is calculated by doing an exclusive-OR of all the data bits. If odd parity is used, the result of the exclusive-OR is inverted. The parity bit is located between the MSB and first stop bit of a serial frame.
  • Page 189: Usin Uart Parity Generator

    MC96F6432S ABOV Semiconductor Co., Ltd. USIn UART Parity Generator 11.12.9.3 The parity generator calculates the parity bit for the serial frame data to be sent. When parity bit is enabled (USInPM1=1), the transmitter control logic inserts the parity bit between the MSB and the first stop bit of the frame to be sent.
  • Page 190: Usin Uart Receiver Flag And Interrupt

    MC96F6432S ABOV Semiconductor Co., Ltd. USIn UART Receiver Flag and Interrupt 11.12.10.2 The UARTreceiver has one flag that indicates the receiver state. The receive complete (RXCn)flag indicates whether there are unread data in the receive buffer. This flag is set when there is unread data in the receive buffer and cleared when the receive buffer is empty.If the receiver is disabled...
  • Page 191: Usin Asynchronous Data Reception

    MC96F6432S ABOV Semiconductor Co., Ltd. USIn Asynchronous Data Reception 11.12.10.5 To receive asynchronous data frame, the UART includes a clock and data recovery unit. Theclock recovery logic is used for synchronizing the internally generated baud-rate clock to the incoming asynchronous serial frame on the RXDn pin.
  • Page 192 MC96F6432S ABOV Semiconductor Co., Ltd. When the receiver is enabled (RXEn=1), the clock recovery logic tries to find a high-to-low transition on the RXDn line, the start bit condition. After detecting high to low transition on RXDn line, the clock recovery logic uses samples 8, 9 and 10 for normal mode to decide if a valid start bit is received.
  • Page 193: Usin Spi Mode

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.12.11 USIn SPI Mode The USIn can be set to operate in industrial standard SPI compliant mode. The SPI mode has the following features. − Full Duplex, Three-wire synchronous data transfer − Mater and Slave Operation −...
  • Page 194 MC96F6432S ABOV Semiconductor Co., Ltd. SCKn (CPOLn=0) SCKn (CPOLn=1) SAMPLE MOSIn MSB First … BIT7 BIT6 BIT2 BIT1 BIT0 LSB First … BIT0 BIT1 BIT5 BIT6 BIT7 MISOn /SSn OUT (MASTER) /SSn IN (SLAVE) Figure 11.64 USIn SPI Clock Formats when CPHAn=0 When CPHAn=0, the slave begins to drive its MISOn output with the first data bit value when SSn goes to active low.
  • Page 195 MC96F6432S ABOV Semiconductor Co., Ltd. SCKn (CPOLn=0) SCKn (CPOLn=1) SAMPLE MOSIn … MSB First BIT7 BIT6 BIT2 BIT1 BIT0 … LSB First BIT0 BIT1 BIT5 BIT6 BIT7 MISOn /SSn OUT (MASTER) /SSn IN (SLAVE) Figure 11.65 USIn SPI Clock Formats when CPHAn=1 When CPHAn=1, the slave begins to drive its MISOn output when SSn goes active low, but the data is not defined until the first SCKn edge.
  • Page 196: Usin Spi Block Diagram

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.12.13 USIn SPI Block Diagram USInBD Control SCLK Baud Rate Generator (fx: System clock) MASTERn USInSSEN Edge Detector SCKn Control Controller FXCHn RXEn CPOLn CPHAn MISOn Data Receive Shift Register Rx Control Recovery (RXSR) RXCn...
  • Page 197: Usin I2C Mode

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.12.14 USIn I2C Mode The USIn can be set to operate in industrial standard serial communication protocols mode. The I2C mode uses 2 bus lines serial data line (SDAn) and serial clock line (SCLn) to exchange data. Because both SDAn and SCLn lines are open-drain output, each line needs pull-up resistor.
  • Page 198: Usin I2C Start / Repeated Start / Stop

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.12.16 USIn I2C Start / Repeated Start / Stop One master can issue a START (S) condition to notice other devices connected to the SCLn, SDAn lines that it will use the bus. A STOP (P) condition is generated by the master to release the bus lines so that other devices can use it.
  • Page 199: Usin I2C Acknowledge

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.12.18 USIn I2C Acknowledge The acknowledge related clock pulse is generated by the master. The transmitter releases the SDAn line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDAn line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse.
  • Page 200: Usin I2C Operation

    MC96F6432S ABOV Semiconductor Co., Ltd. Wait High Start High Counting Counting Fast Device SCLOUT High Counter Reset Slow Device SCLOUT SCLn Figure 11.71 Clock Synchronization during Arbitration Procedure (USIn) Arbitration Process Device 1 loses Device1 outputs not adapted Arbitration High...
  • Page 201: Usin I2C Master Transmitter

    MC96F6432S ABOV Semiconductor Co., Ltd. USIn I2C Master Transmitter 11.12.20.1 To operate I2C in master transmitter, follow the recommended steps below. Enable I2C by setting USInMS[1:0]bits in USInCR1 and USInEN bit in USInCR2. This provides main clock to the peripheral.
  • Page 202 MC96F6432S ABOV Semiconductor Co., Ltd. This is ACK signal processing stage for data packet transmitted by master. I2C holds the SCLn LOW. When I2C loses bus mastership while transmitting data arbitrating other masters, the MLOSTn bit in USInST2 is set.
  • Page 203: Usin I2C Master Receiver

    MC96F6432S ABOV Semiconductor Co., Ltd. USIn I2C Master Receiver 11.12.20.2 To operate I2C in master receiver, follow the recommended steps below. Enable I2C by setting USInMS[1:0]bits in USInCR1and USInEN bit in USInCR2. This provides main clock to the peripheral. Load SLAn+R into the USInDR where SLA is address of slave device and R is transfer direction from the viewpoint of the master.
  • Page 204 MC96F6432S ABOV Semiconductor Co., Ltd. 1-Byte of data is being received. This is ACK signal processing stage for data packet transmitted by slave. I2C holds the SCLn LOW. When 1- Byte of data is received completely, I2C generates TENDn interrupt.
  • Page 205: Usin I2C Slave Transmitter

    MC96F6432S ABOV Semiconductor Co., Ltd. USIn I2C Slave Transmitter 11.12.20.3 To operate I2C in slave transmitter, follow the recommended steps below. If the main operating clock (SCLK) of the system is slower than that of SCLn, load value 0x00 into USInSDHR to make SDAn change within one system clock period from the falling edge of SCLn.
  • Page 206: Usin I2C Slave Receiver

    MC96F6432S ABOV Semiconductor Co., Ltd. USIn I2C Slave Receiver 11.12.20.4 To operate I2C in slave receiver, follow the recommended steps below. If the main operating clock (SCLK) of the system is slower than that of SCLn, load value 0x00 into USInSDHR to make SDAn change within one system clock period from the falling edge of SCLn.
  • Page 207: Usin I2C Block Diagram

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.12.21 USIn I2C Block Diagram IICnIFR To interrupt block Slave Address Register USInSAR RXACKn, GCALLn, Interrupt IICnIE TENDn, STOPDn, Generator SSELn, MLOSTn, General Call And USInGCE BUSYn, TMODEn Address Detector Receive Shift Register SDAn USInDR, (Rx)
  • Page 208: Register Map

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.12.22 Register Map Name Address Direction Default Description USI0BD USI0 Baud Rate Generation Register USI0DR USI0 Data Register USI0SDHR USI0 SDA Hold Time Register USI0SCHR USI0 SCL High Period Register USI0SCLR USI0 SCL Low Period Register...
  • Page 209: Register Description For Usin

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.12.24 Register Description for USIn USInBD (USIn Baud- Rate Generation Register: For UART and SPI mode): E3H/F3H, n = 0, 1 USInBD7 USInBD 6 USInBD 5 USInBD 4 USInBD 3 USInBD 2 USInBD 1 USInBD 0...
  • Page 210 MC96F6432S ABOV Semiconductor Co., Ltd. USInSDHR (USInSDA Hold Time Register: For I2C mode): E4H/F4H, n = 0, 1 USInSDHR7 USInSDHR6 USInSDHR5 USInSDHR 4 USInSDHR 3 USInSDHR 2 USInSDHR 1 USInSDHR 0 Initial value: 01H USInSDHR[7:0] The register is used to control SDAn output timing from the falling edge of SCI in I2C mode.
  • Page 211 MC96F6432S ABOV Semiconductor Co., Ltd. USInSCLR (USInSCL Low Period Register: For I2C mode): E6H/F6H, n = 0, 1 USInSCLR7 USInSCLR6 USInSCLR5 USInSCLR 4 USInSCLR 3 USInSCLR 2 USInSCLR 1 USInSCLR 0 Initial value: 3FH USInSCLR[7:0] This register defines the high period of SCLn when it operates in I2C master mode.
  • Page 212 MC96F6432S ABOV Semiconductor Co., Ltd. USInCR1 (USIn Control Register 1: For UART, SPI, and I2C mode): D9H/E9H, n = 0, 1 USInS1 USInS0 USInMS1 USInMS0 USInPM1 USInPM0 USInS2 CPOLn ORDn CPHAn Initial value: 00H USInMS[1:0] Selects operation mode of USIn...
  • Page 213 MC96F6432S ABOV Semiconductor Co., Ltd. USInCR2 (USIn Control Register 2: For UART, SPI, and I2C mode): DAH/EAH, n = 0, 1 DRIEn TXCIEn RXCIEn WAKEIEn TXEn RXEn USInEN DBLSn Initial value: 00H DRIEn Interrupt enable bit for data register empty (only UART and SPI mode).
  • Page 214 MC96F6432S ABOV Semiconductor Co., Ltd. USInCR3 (USIn Control Register 3: For UART, SPI, and I2C mode): DBH/EBH, n = 0, 1 MASTERn LOOPSn DISSCKn USInSSEN FXCHn USInSB USInTX8 USInRX8 Initial value: 00H MASTERn Selects master or slave in SPI and synchronous mode operation and controls the direction of SCKn pin Slave mode operation (External clock for SCKn).
  • Page 215 MC96F6432S ABOV Semiconductor Co., Ltd. USI0CR4 (USIn Control Register 4: For I2C mode): DCH/ECH, n = 0, 1 – IICnIFR TXDLYENBn IICnIE ACKnEN IMASTERn STOPCn STARTCn – Initial value: 00H This is an interrupt flag bit for I2C mode. When an interrupt occurs, this bit becomes ‘1’.
  • Page 216 MC96F6432S ABOV Semiconductor Co., Ltd. USInST1 (USIn Status Register 1: For UART and SPI mode): E1H/F1H, n = 0, 1 DREn TXCn RXCn WAKEn USInRST DORn Initial value: 80H DREn The DREn flag indicates if the transmit buffer (USInDR) is ready to receive new data. If DREn is ‘1’, the buffer is empty and ready to be written.
  • Page 217 MC96F6432S ABOV Semiconductor Co., Ltd. USInST2 (USIn Status Register 2: For I2C mode): E2H/F2H, n = 0, 1 GCALLn TENDn STOPDn SSELn MLOSTn BUSYn TMODEn RXACKn Initial value: 00H (NOTE) GCALLn This bit has different meaning depending on whether I2C is master or slave. When I2C is a master, this bit represents whether it received AACK (address ACK) from slave.
  • Page 218: Baud Rate Setting (Example)

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.12.25 Baud Rate setting (example) fx=1.00MHz fx=1.8432MHz fx=2.00MHz Baud Rate (bps) USI0BD/USI1BD ERROR USI0BD/USI1BD ERROR USI0BD/USI1BD ERROR 2400 0.2% 0.0% 0.2% 4800 0.2% 0.0% 0.2% 9600 -7.0% 0.0% 0.2% 14.4k 8.5% 0.0% -3.5% 19.2k 8.5% 0.0%...
  • Page 219: Lcd Driver

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.13 LCD Driver 11.13.1 Overview The LCD driver is controlled by the LCD Control Register (LCDCRH/L). The LCLK[1:0] determines the frequency of COM signal scanning of each segment output. A RESET clears the LCD control register LCDCRH and LCDCRL values to logic ‘0’.
  • Page 220: Lcd Display Ram Organization

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.13.2 LCD Display RAM Organization Display data are stored to the display data area in the external data memory. The display data which stored to the display external data area (address 0000H-001AH) are read automatically and sent to the LCD driver by the hardware.
  • Page 221: Lcd Signal Waveform

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.13.3 LCD Signal Waveform COM0 SEG0 1 Frame COM1 VLC0 COM0 VLC2(VLC1, VLC3) SEG3 SEG1 SEG2 VLC0 COM1 VLC2(VLC1, VLC3) VLC0 VLC2(VLC1, VLC3) SEG0 VLC0 SEG1 VLC2(VLC1, VLC3) +VLC0 +VLC2(VLC1, VLC3) COM0-SEG0 -VLC2(VLC1, VLC3) -VLC0 Figure 11.75...
  • Page 222 MC96F6432S ABOV Semiconductor Co., Ltd. SEG1 SEG3 SEG2 COM0 1 Frame VLC0 VLC1 COM1 COM0 VLC2(VLC3) COM2 VLC0 VLC1 COM1 VLC2(VLC3) VLC0 VLC1 COM2 VLC2(VLC3) VLC0 VLC1 SEG1 VLC2(VLC3) VLC0 VLC1 SEG2 VLC2(VLC3) +VLC0 +VLC1 +VLC2(VLC3) COM0-SEG1 -VLC2(VLC3) -VLC1 -VLC0 Figure 11.76...
  • Page 223 MC96F6432S ABOV Semiconductor Co., Ltd. SEG3 SEG2 COM0 1 Frame COM1 VLC0 VLC1 COM2 COM0 VLC2(VLC3) COM3 VLC0 VLC1 COM1 VLC2(VLC3) VLC0 VLC1 COM2 VLC2(VLC3) VLC0 VLC1 SEG2 VLC2(VLC3) VLC0 VLC1 SEG3 VLC2(VLC3) +VLC0 +VLC1 +VLC2(VLC3) COM0-SEG2 -VLC2(VLC3) -VLC1 -VLC0 Figure 11.77...
  • Page 224 MC96F6432S ABOV Semiconductor Co., Ltd. COM0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 COM1 COM2 COM3 COM4 1 Frame COM5 COM6 VLC0 COM7 VLC1 COM0 VLC2 VLC3 VLC0 VLC1 COM1 VLC2 VLC3...
  • Page 225: Lcd Voltage Dividing Resistor Connection

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.13.4 LCD Voltage Dividing Resistor Connection (1/ 2 Bias, 2xR (1/ 2 Bias, R VLCD VLCD VLC0 VLC1 VLC2 VLC3 VLC0 VLC1 VLC2 VLC3 DISP DISP LCTEN LCTEN VLC0 VLC1 VLC2 VLC3 VLC0 VLC1 VLC2...
  • Page 226 MC96F6432S ABOV Semiconductor Co., Ltd. (1/ 2 BIAS) VLCD DISP LCTEN VLC0 VLC1 VLC2 VLC3 R’ R’ (1/ 3 BIAS) (1/ 4 BIAS) VLCD VLCD DISP DISP LCTEN LCTEN VLC0 VLC1 VLC2 VLC3 VLC0 VLC1 VLC2 VLC3 R’ R’ R’...
  • Page 227: Block Diagram

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.13.5 Block Diagram Port Latch SEG/Port Driver Display COM/Port Driver fLCD Timing LCDCRL Controller LCDCRH VLC0 LCD Bias VLC1 Voltage VLC2 Generator Contrast LCDCCR Controller VLC3 Figure 11.81 LCD Circuit Block Diagram 11.13.6 Register Map...
  • Page 228: Register Description For Lcd Driver

    MC96F6432S ABOV Semiconductor Co., Ltd. 11.13.8 Register Description for LCD Driver LCDCRH (LCD Driver Control High Register): 9AH – – – – – COMCHG LCDDR DISP – – – – – Initial value: 00H COMCHG Common Signal Output Port Change Control COM0 –...
  • Page 229 MC96F6432S ABOV Semiconductor Co., Ltd. LCDCRL (LCD Driver Control Low Register): 99H – IRSEL DBS3 DBS2 DBS1 DBS0 LCLK1 LCK0 – R./W Initial value: 00H IRSEL Internal LCD Bias Dividing Resistor Select = 60kΩ (R LCD1 = 120kΩ (R LCD2...
  • Page 230 MC96F6432S ABOV Semiconductor Co., Ltd. LCDCCR (LCD Driver Contrast Control Low Register): 9BH – – – LCTEN VLCD3 VLCD VLCD1 VLCD0 – – – Initial value: 00H LCTEN Control LCD Driver Contrast LCD Driver Contrast disable LCD Driver Contrast enable...
  • Page 231: Power Down Operation

    MC96F6432S ABOV Semiconductor Co., Ltd. Power Down Operation 12.1 Overview The MC96F6432S has two power-down modes to minimize the power consumption of the device. In power down mode, power consumption is reduced considerably. The device provides three kinds of power saving functions, Main- IDLE, Sub-IDLE and STOP mode.
  • Page 232: Idle Mode

    MC96F6432S ABOV Semiconductor Co., Ltd. 12.3 IDLE Mode The power control register is set to ‘01h’ to enter the IDLE Mode. In this mode, the internal oscillation circuits remain active. Oscillation continues and peripherals are operated normally but CPU stops. It is released by reset or interrupt.
  • Page 233: Stop Mode

    MC96F6432S ABOV Semiconductor Co., Ltd. 12.4 STOP Mode The power control register is set to ‘03H’ to enter the STOP Mode. In the stop mode, the selected oscillator, system clock and peripheral clock is stopped, but watch timer can be continued to operate with sub clock. With the clock frozen, all functions are stopped, but the on-chip RAM and control registers are held.
  • Page 234: Release Operation Of Stop Mode

    MC96F6432S ABOV Semiconductor Co., Ltd. 12.5 Release Operation of STOP Mode After STOP mode is released, the operation begins according to content of related interrupt register just before STOP mode start (Figure 12.3).If the global interrupt Enable Flag (IE.EA)is set to `1`, the STOP mode isreleased by the interrupt which each interrupt enable flag = `1` and the CPU jumps to the relevant interrupt service routine.
  • Page 235: Register Map

    MC96F6432S ABOV Semiconductor Co., Ltd. 12.6 Register Map Name Address Direction Default Description PCON Power Control Register Power Down Operation Register Map Table 12.2 12.7 Power Down Operation Register Description The power down operation register consists of the power control register (PCON).
  • Page 236: Reset

    MC96F6432S ABOV Semiconductor Co., Ltd. RESET 13.1 Overview The following is the hardware setting value. On Chip Hardware Initial Value Program Counter (PC) 0000h Accumulator Stack Pointer (SP) Peripheral Clock Control Register Refer to the Peripheral Registers Reset State Table 13.1 13.2...
  • Page 237: Reset Noise Canceller

    MC96F6432S ABOV Semiconductor Co., Ltd. 13.4 RESET Noise Canceller The Figure 13.2 is the noise canceller diagram for noise cancellation of RESET. It has the noise cancellation value of about 2us(@V =5V) to the low input of system reset. t < T t <...
  • Page 238 MC96F6432S ABOV Semiconductor Co., Ltd. Counting for configure read start after POR is released Internal nPOR PAD RESETB “H” LVR_RESETB .. 27 28 BIT (for Configure) 00 01 02 03 BIT (for Reset) 1us X 256 X 28h = about 10ms...
  • Page 239 MC96F6432S ABOV Semiconductor Co., Ltd. Process Description Remarks ① - No Operation ② -1st POR level Detection -about 1.4V - (INT-OSC 8MHz/8)x256x28h Delay section (=10ms) ③ -Slew Rate >= 0.05V/ms -VDD input voltage must rise over than flash operating voltage for Configure option read -about 1.5V ~ 1.6V...
  • Page 240: External Resetb Input

    MC96F6432S ABOV Semiconductor Co., Ltd. 13.6 External RESETB Input The External RESETB is the input to a Schmitt trigger. If RESETB pin is held with low for at least 10us over within the operating voltage range and stable oscillation, it is applied and the internal state is initialized. After reset state becomes ‘1’, it needs the stabilization time with 16ms and after the stable state, the internal RESET becomes ‘1’.
  • Page 241: Brown Out Detector Processor

    MC96F6432S ABOV Semiconductor Co., Ltd. 13.7 Brown Out Detector Processor The MC96F6432S has an On-chip brown-out detection circuit (BOD) for monitoring the VDD level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by LVRVS[3:0] bit to be 1.60V, 2.00V, 2.10V, 2.20V,2.32V, 2.44V, 2.59V, 2.75V, 2.93V, 3.14V, 3.38V, 3.67V, 4.00V, 4.40V.
  • Page 242 MC96F6432S ABOV Semiconductor Co., Ltd. “H” “H” Internal nPOR “H” PAD RESETB LVR_RESETB ..27 28 BIT (for Config) 00 01 02 BIT (for Reset) 1us X 256 X 28h = about 10ms Config Read 1us X 4096 X 4h = about 16ms...
  • Page 243: Lvi Block Diagram

    MC96F6432S ABOV Semiconductor Co., Ltd. 13.8 LVI Block Diagram 2.00V 2.10V 2.20V 2.32V 2.44V 2.59V Reference 2.75V Voltage LVI Circuit LVIF 2.93V Generator 3.14V 3.38V 3.67V 4.00V LVIEN 4.40V LVIREF LVILS[3:0] Figure 13.12 LVI Diagram 13.9 Register Map Name Address...
  • Page 244: Register Description For Reset Operation

    MC96F6432S ABOV Semiconductor Co., Ltd. 13.11 Register Description for Reset Operation RSTFR (Reset Flag Register): E8H – – – – PORF EXTRF WDTRF LVRF – – – – Initial value: 80H Power-On Reset flag bit. The bit is reset by writing ‘0’ to this bit.
  • Page 245 MC96F6432S ABOV Semiconductor Co., Ltd. LVRCR (Low Voltage Reset Control Register): D8H – – LVRST LVRVS3 LVRVS2 LVRVS1 LVRVS0 LVREN – – Initial value: 00H LVRST LVR Enable when Stop Release Not effect at stop release LVR enable at stop release NOTE) When this bit is ‘1’, the LVREN bit is cleared to ‘0’...
  • Page 246 MC96F6432S ABOV Semiconductor Co., Ltd. LVICR (Low Voltage Indicator Control Register): 86H – – LVIF LVIEN LVILS3 LVILS2 LVILS1 LVILS0 – – Initial value: 00H LVIF Low Voltage Indicator Flag Bit No detection Detection LVIEN LVI Enable/Disable Disable Enable LVILS[3:0]...
  • Page 247: On-Chip Debug System(Mc96F6432 Only)

    MC96F6432S ABOV Semiconductor Co., Ltd. On-chip Debug System(MC96F6432 ONLY) 14.1 Overview 14.1.1 Description MC96F6432S can not support On-chip debug(OCD). MC96F6432S isn’t equipped with on-chip debugger. We recommend to develop and debug program with MC96F6432. On-chip debug system of MC96F6432 can be used for programming the non-volatile memories and on-chip debugging.
  • Page 248: Feature

    MC96F6432S ABOV Semiconductor Co., Ltd. 14.1.2 Feature • Two-wire external interface: 1-wire serial clock input, 1-wire bi-directional serial data bus • Debugger Access to: − All Internal Peripheral Units − Internal data RAM − Program Counter − Flash and Data EEPROM Memories •...
  • Page 249: Two-Pin External Interface

    MC96F6432S ABOV Semiconductor Co., Ltd. 14.2 Two-Pin External Interface 14.2.1 Basic Transmission Packet • 10-bit packet transmission using two-pin interface. • 1-packet consists of 8-bit data, 1-bit parity and 1-bit acknowledge. • Parity is even of ‘1’ for 8-bit data in transmitter.
  • Page 250: Packet Transmission Timing

    MC96F6432S ABOV Semiconductor Co., Ltd. 14.2.2 Packet Transmission Timing Data Transfer 14.2.2.1 DSDA acknowledgement acknowledgement signal from receiver signal from receiver DSCL START STOP Figure 14.3 Data Transfer on the Twin Bus Bit Transfer 14.2.2.2 DSDA DSCL data line change...
  • Page 251: Start And Stop Condition

    MC96F6432S ABOV Semiconductor Co., Ltd. Start and Stop Condition 14.2.2.3 DSDA DSDA DSCL DSCL START condition STOP condition Figure 14.5 Start and Stop Condition Acknowledge Bit 14.2.2.4 Data output By transmitter no acknowledge Data output By receiver acknowledge DSCL from...
  • Page 252: Connection Of Transmission

    MC96F6432S ABOV Semiconductor Co., Ltd. 14.2.3 Connection of Transmission Two-pin interface connection uses open-drain(wire-AND bidirectional I/O). pull resistors DSDA(Debugger Serial Data Line) DSCL(Debugger Serial Clock Line) DSCL DSDA DSCL DSDA DSDA DSDA DSCL DSCL Target Device(Slave) Host Machine(Master) Current source for DSCL to fast 0 to 1 transition in high speed mode Figure 14.8...
  • Page 253: Flash Memory

    MC96F6432S ABOV Semiconductor Co., Ltd. Flash Memory 15.1 Overview 15.1.1 Description MC96F6432S incorporates flash memory to which a program can be written, erased, and overwritten while mounted on the board. The flash memory can be read by ‘MOVC’ instruction and it can be programmed in serial ISP mode or user program mode.
  • Page 254: Flash Program Rom Structure

    MC96F6432S ABOV Semiconductor Co., Ltd. 15.1.2 Flash Program ROM Structure 07FFFH Sector 511 07FC0H 07FC0H 07FBFH Sector 510 07F80H 07F80H 07F7FH Sector 509 07F40H 07F40H 07F3FH Sector 508 Flash Sector Address Address Sector 2 00080H 00080H 0007FH Sector 1 00040H...
  • Page 255: Register Map

    MC96F6432S ABOV Semiconductor Co., Ltd. 15.1.3 Register Map Name Address Direction Default Description FSADRH Flash Sector Address High Register FSADRM Flash Sector Address Middle Register FSADRL Flash Sector Address Low Register FIDR Flash Identification Register FMCR Flash Mode Control Register Flash Memory Register Map Table 15.1...
  • Page 256: Register Description For Flash

    MC96F6432S ABOV Semiconductor Co., Ltd. 15.1.5 Register Description for Flash FSADRH (Flash Sector Address High Register): FAH – – – – FSADRH3 FSADRH 2 FSADRH1 FSADRH0 – – – – Initial value: 00H FSADRH[3:0] Flash Sector Address High FSADRM (Flash Sector Address Middle Register): FBH...
  • Page 257 MC96F6432S ABOV Semiconductor Co., Ltd. FMCR (Flash Mode Control Register): FEH – – – – FMBUSY FMCR2 FMCR1 FMCR0 – – – – Initial value: 00H FMBUSY Flash Mode Busy Bit. This bit will be used for only debugger. No effect when “1” is written...
  • Page 258: Serial In-System Program (Isp) Mode

    MC96F6432S ABOV Semiconductor Co., Ltd. 15.1.6 Serial In-System Program (ISP) Mode Serial in-system program uses the interface of debugger which uses two wires. Refer to chapter 14 in details about debugger 15.1.7 Protection Area (User program mode) MC96F6432S can program its own flash memory (protection area). The protection area can not be erased or programmed.
  • Page 259: Erase Mode

    MC96F6432S ABOV Semiconductor Co., Ltd. 15.1.8 Erase Mode The sector erase program procedure in user program mode Page buffer clear (FMCR=0x01) Write ‘0’ to page buffer Set flash sector address register (FSADRH/FSADRM/FSADRL). Set flash identification register (FIDR). (Note) Check the UserID for to prevent the invalid work Set flash mode control register (FMCR).
  • Page 260: Write Mode

    MC96F6432S ABOV Semiconductor Co., Ltd. 15.1.9 Write Mode The sector Write program procedure in user program mode Page buffer clear (FMCR=0x01) Write data to page buffer Set flash sector address register (FSADRH/FSADRM/FSADRL). Set flash identification register (FIDR). (Note1) Check the UserID for to prevent the invalid work Set flash mode control register (FMCR).
  • Page 261 MC96F6432S ABOV Semiconductor Co., Ltd. The Byte Write program procedure in user program mode Page buffer clear (FMCR=0x01) Write data to page buffer Set flash sector address register (FSADRH/FSADRM/FSADRL). Set flash identification register (FIDR). (Note1) Check the UserID for to prevent the invalid work Set flash mode control register (FMCR).
  • Page 262: Protection For Invalid Erase/Write

    MC96F6432S ABOV Semiconductor Co., Ltd. 15.1.10 Protection for Invalid Erase/Write It should be taken care to the flash erase/write programming in code. You must make preparations for invalid jump to the flash erase/write code by malfunction, noise, and power off.
  • Page 263 MC96F6432S ABOV Semiconductor Co., Ltd. The flash sector address (FSADRH/FSADRM/FSADRL) should always keep the address of the flash which is used for data area. For example, The FSADRH/FSADRM is always 0x00/0x7f” if 0x7f00 to 0x7fff is used for data. Overview of main...
  • Page 264: Flow Of Protection For Invalid Erase/Write

    MC96F6432S ABOV Semiconductor Co., Ltd. Flow of Protection for Invalid Erase/Write 15.1.10.1 Start Work1 Decide to write/erase Set Flags on flash Work2 Check the flag for Match Write UserID1/2/3 UserID Work3 Check the UserID for Match Write/Erase Flash write/erase flash...
  • Page 265: Read Mode

    MC96F6432S ABOV Semiconductor Co., Ltd. 15.1.11 Read Mode The Reading program procedure in user program mode Load receive data from flash memory on MOVC instruction by indirectly addressing mode. Program Tip – reading A,#0 DPH,#0x7F DPL,#0x40 ;flash memory address MOVC A,@A+DPTR ;read data from flash memory...
  • Page 266: Configure Option

    MC96F6432S ABOV Semiconductor Co., Ltd. Configure Option 16.1 Configure Option Control The data for configure option should be written in the configure option area (003EH – 003FH) by programmer (Writer tools). CONFIGURE OPTION 1 : ROM Address 003FH – –...
  • Page 267: Appendix

    MC96F6432S ABOV Semiconductor Co., Ltd. APPENDIX 17.1 Instruction Table Instructions are either1, 2 or 3bytes long as listed in the ‘Bytes’ column below. Each instruction takes either 1, 2 or 4 machine cycles to execute as listed in the following table. 1 machine cycle comprises 2 system clock cycles.
  • Page 268 MC96F6432S ABOV Semiconductor Co., Ltd. LOGICAL Mnemonic Description Bytes Cycles Hex code ANL A,Rn AND register to A 58-5F ANL A,dir AND direct byte to A ANL A,@Ri AND indirect memory to A 56-57 ANL A,#data AND immediate to A...
  • Page 269 MC96F6432S ABOV Semiconductor Co., Ltd. DATA TRANSFER Mnemonic Description Bytes Cycles Hex code MOV A,Rn Move register to A E8-EF MOV A,dir Move direct byte to A MOV A,@Ri Move indirect memory to A E6-E7 MOV A,#data Move immediate to A...
  • Page 270 MC96F6432S ABOV Semiconductor Co., Ltd. BRANCHING Mnemonic Description Bytes Cycles Hex code ACALL addr 11 Absolute jump to subroutine 11→F1 LCALL addr 16 Long jump to subroutine Return from subroutine RETI Return from interrupt AJMP addr 11 Absolute jump unconditional 01→E1...
  • Page 271: Instructions On How To Use The Input Port

    MC96F6432S ABOV Semiconductor Co., Ltd. 17.2 Instructions on how to use the input port. • Error occur status − Using compare jump instructions with input port, it could cause error due to the timing conflict inside the MCU. − Compare jump Instructions which cause potential error used with input port condition: bit, rel ;...
  • Page 272 MC96F6432S ABOV Semiconductor Co., Ltd. − If you use input bit port for compare jump instruction, you have to copy the input port as internal parameter or carry bit and then use compare jump instruction. bit tt; zzz: MOV C,080.0 ;...
  • Page 273: Esd Test Method

    MC96F6432S ABOV Semiconductor Co., Ltd. 17.3 ESD Test Method ESD Test Description ESD Testing was perform on Zapmaster system using the Human-Body-Model (H.B.M) and Machine-Model (M.M) according JESD22-A114F and EIA/JESD22-A115-A respectively. Human-Body-Model stresses devices by sudden application of a high voltage supplied by a 100pF capacitor through 1.5k Ohms resistance. Machine-Model stresses devices by sudden application of a high voltage supplied by a 200pF capacitor through very low (0 Ohm) resistance.
  • Page 274 MC96F6432S ABOV Semiconductor Co., Ltd. ESD Test Method : I/O (Pin-to-Pin) Mode I/O pins are zapped, pin by pin. I/O pins which are not zapped are grounded. All power pins (VDD and VSS) are floated. ESD Class HBM (Human-Body-Model) : 3A...
  • Page 275: Flash Protection For Invalid Erase/Write

    MC96F6432S ABOV Semiconductor Co., Ltd. 17.4 Flash Protection for Invalid Erase/Write  Overview This is example to prevent changing code or data in flash by abnormal operation(noise, unstable power, malfunction, etc…).  How to protect the flash • Divide into decision and execution to Erase/Write in flash.
  • Page 276 MC96F6432S ABOV Semiconductor Co., Ltd.  Flowchart Start Initial ① Set LVR/LVI more than 2.0V Start Main Loop Working ③ Write Flash? Set User_ID1 ② Working ③ Check User_ID1? Set User_ID2 Working Check User_ID2? Set User_ID3 ③ Working Write Flash Set FSADDRH/M/L ④...
  • Page 277 Initialize User_ID1/2/3 Set Flash Sector Address to Dummy Address • Sample Source Refer to the ABOV homepage. It is created based on the MC97F2664. Each product should be modified according to the Page Buffer Size and Flash Size  Etc •...
  • Page 278: Table Of Contents

    MC96F6432S ABOV Semiconductor Co., Ltd. Table of contents Revision history ................................2 Overview ................................... 3 1.1. Description ................................3 Features ................................4 Development tools .............................. 5 1.3.1 Compiler ..............................5 1.3.2 OCD(On-chip debugger) emulator and debugger ..................5 1.3.3 Programmer ..............................6 MTP programming ..............................
  • Page 279 MC96F6432S ABOV Semiconductor Co., Ltd. I/O Ports .................................. 61 I/O Ports ................................61 Port Register ..............................61 9.2.1 Data Register (Px) ............................. 61 9.2.2 Direction Register (PxIO) .......................... 61 9.2.3 Pull-up Resistor Selection Register (PxPU) ....................61 9.2.4 Open-drain Selection Register (PxOD) ..................... 61 9.2.5...
  • Page 280 MC96F6432S ABOV Semiconductor Co., Ltd. 11.2.3 Register Map ............................101 11.2.4 Basic Interval Timer Register Description ....................102 11.2.5 Register Description for Basic Interval Timer ..................102 11.3 Watch Dog Timer ............................103 11.3.1 Overview ..............................103 11.3.2 WDT Interrupt Timing Waveform ......................103 11.3.3...
  • Page 281 MC96F6432S ABOV Semiconductor Co., Ltd. 11.9.5 Register Description for Buzzer Driver ....................169 11.10 SPI 2 ................................170 11.10.1 Overview .............................. 170 11.10.2 Block Diagram ............................170 11.10.3 Data Transmit / Receive Operation ...................... 171 11.10.4 SS2 pin function ........................... 171 11.10.5...
  • Page 282 MC96F6432S ABOV Semiconductor Co., Ltd. 11.13.5 Block Diagram ............................227 11.13.6 Register Map ............................227 11.13.7 LCD Driver Register Description ......................227 11.13.8 Register Description for LCD Driver ....................228 Power Down Operation ............................ 231 12.1 Overview ................................. 231 12.2 Peripheral Operation in IDLE/STOP Mode .....................
  • Page 283 MC96F6432S ABOV Semiconductor Co., Ltd. 17.1 Instruction Table .............................. 267 17.2 Instructions on how to use the input port......................271 17.3 ESD Test Method ............................273 17.4 Flash Protection for Invalid Erase/Write ......................275 Table of contents ................................. 278...

Table of Contents