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Abov MC96FR116C Series User Manual

8-bit microcontrollers
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MC96FR116C
ABOV SEMICONDUCTOR Co., Ltd.
8-BIT MICROCONTROLLERS
MC96FR116C
User's Manual (Rev.1.8)
November, 2018 Rev.1.8
1

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Summary of Contents for Abov MC96FR116C Series

  • Page 1 MC96FR116C ABOV SEMICONDUCTOR Co., Ltd. 8-BIT MICROCONTROLLERS MC96FR116C User’s Manual (Rev.1.8) November, 2018 Rev.1.8...

  • Page 2: Revision History

    MC96FR116C REVISION HISTORY REVISION 0.0 (August 6, 2013) Initial preliminary version REVISION 0.1 (November 15, 2013)  7. ELECTRICAL CHARACTERISTICS  12.5 BOD mode  The initial value of BODR register is changed from 81 to C9 REVISION 0.2 (December 3, 2013) ...
  • Page 3 MC96FR116C  Timing characteristics is added.  7.14 USART CHARACTERISTICS  max. values of tLEAD, tLAG, tSIM, tSIS, tSOM, tSOS are removed.  16.1 FUSE Control register  The Definition of FUSE_CONF is added. REVISION 1.0 (April 4, 2014) Initial version REVISION 1.1 (April 16, 2014) ...
  • Page 4 MC96FR116C REVISION 1.3 (July 10, 2014)  11.6.4 Register Description  The comment of RSEL(IRCC0[2:0] register) is updated.  7.9 Analog Comparator CHARACTERISTICS  Recommended condition is added. REVISION 1.4 (November 21, 2014)  1.3 Ordering Information  “7.3 POWER SEQUENCE CHARACTERISTICS” is added. ...

  • Page 5: Table Of Contents

    MC96FR116C Table of Contents REVISION HISTORY ............................2 Table of Contents ..............................5 List of Figures ............................... 8 MC96FR116C ..............................11 1. OVERVIEW ..............................11 1.1 Description ..............................11 1.2 Features ..............................11 1.3 Ordering Information ..........................12 1.4 Development Tools ............................ 14 2.
  • Page 6 MC96FR116C 9.2 Register Description........................... 49 10. Interrupt Controller ............................55 10.1 Overview ..............................55 10.2 External Interrupt ............................. 56 10.3 Block Diagram ............................57 10.4 Interrupt Vectors ............................58 10.5 Interrupt Sequence ........................... 58 10.6 Effective time of Interrupt Request ......................59 10.7 Multiple Interrupts ...........................
  • Page 7 MC96FR116C 15.1 Overview ..............................179 15.2 Boot Area ............................... 179 15.3 Register Map ............................180 15.4 Register Description..........................181 15.5 Memory map ............................187 15.6 Serial In-System Program Mode ......................188 15.7 Security ..............................192 16. FUSE ................................193 16.1 FUSE Control Register .......................... 193 17.

  • Page 8: List Of Figures

    MC96FR116C List of Figures Figure 1-1 Device Nomenclature ......................13 Figure 1-2 OCD Software and Connector..................... 14 Figure 1-3 OCD Mode Sequence ......................15 Figure 1-4 OCD Interface Circuit ......................16 Figure 1-5 E-PGM+ ..........................17 Figure 1-6 PGMPlusLC-II ........................18 Figure 1-7 Gang programmer .......................
  • Page 9 MC96FR116C Figure 11-8 Block Diagram of Timer 0, 1 in 16-bit Timer/ Counter mode .......... 81 Figure 11-9 Block Diagram of Timer 0, 1 in 8-bit Capture mode ............83 Figure 11-10 Timer 0,1 Operation in 8-bit Input Capture Mode ............84 Figure 11-11 Example of Capture Interval Calculation in 8-bit Input Capture Mode ......
  • Page 10 MC96FR116C Figure 11-53 Formats and States in the Slave Receiver Mode ............153 Figure 12-1 Wake-up from SLEEP mode by an interrupt ..............159 Figure 12-2 SLEEP mode release by an external reset ............... 159 Figure 12-3 Wake-up from STOP mode by an interrupt ..............160 Figure 12-4 STOP mode release by an external reset .................

  • Page 11: Mc96Fr116C

    MC96FR116C MC96FR116C CMOS 8-bit Flash Microcontroller : UR 1. OVERVIEW 1.1 Description The MC96FR116C is an advanced 8-bit microcontroller based on CMOS process with 16K Bytes of Flash. This is a powerful device which provides a highly flexible and cost effective solution to many embedded control applications.

  • Page 12: Ordering Information

    MC96FR116C Key scan: 1 12MHz ±2.0% @ -20 ~ +70℃(User Trim) Pin change(P0[5:0]):1 12MHz ±1.0% @ +15 ~ +45℃(User Trim) • Flash secure protection • Analog Comparator for IR learning • Operating Frequency • Power On Reset 1 ~ 12MHz (X-Tal oscillator) •...

  • Page 13: Figure 1-1 Device Nomenclature

    MC96FR116C 1.3.1 Device Nomenclature Device nomenclature MC96FR116Cx MC96FR116Cx Family Name Package type TSSOP WLCSP RoHS Halogen Free Packing Tape & Reel Figure 1-1 Device Nomenclature November, 2018 Rev.1.8...

  • Page 14: Development Tools

    MC96FR116C 1.4 Development Tools 1.4.1 Compiler ABOV semiconductor does not provide any compiler for MC96FR116C. As the CPU core of MC96FR116C is Mentor 8051, you can use all kinds of third party’s standard 8051 compiler. 1.4.2 OCD emulator and debugger OCD(On Chip Debugger) program is a debugging software for ABOV semiconductor’s 8051 MCU...

  • Page 15: Figure 1-3 Ocd Mode Sequence

    MC96FR116C 1.4.3 OCD Port Operation Internal nPOR LVI RESETB Test Mode or LVR RESETB Control Reset DSCL DSDA 12 ms (± 20%) @ Internal Ring OSC Configure Read 16 ms (± 20%) @ Internal Ring OSC Internal RESETb TEST_MODE (OCD Mode) Figure 1-3 OCD Mode Sequence The OCD port is used for flash program writing and device debugging.

  • Page 16: Figure 1-4 Ocd Interface Circuit

    Figure 1-4 OCD Interface Circuit 1.4.4 Programmer To program or download user code into the ROM of MC96FR116C, ABOV semiconductor provides several tools. As a single programmer which can program only one chip at a time, there are E-PGM+ and PGMPlusLC-II. On the other hand, you can program multi-chips at a time by using a gang programmer.

  • Page 17: Figure 1-5 E-Pgm

    MC96FR116C 1.4.4.1 E-PGM+ E-PGM+ is a single write tool for ABOV MCUs. Features :  Support ABOV / ADAM devices  2~5 times faster than S-PGM+  Main controller : 32 bit MCU @72MHz  Buffer memory : 1MB Enter Key Connector.

  • Page 18: Figure 1-6 Pgmpluslc-Ii

    MC96FR116C 2. VDD 4. GND 6. Serial Clock (DSCL) 8. Serial Data (DSDA) Figure 1-6 PGMPlusLC-II 1.4.4.3 E-GANG4(6) The gang programmer, E-GANG4/(6) can program maximum4(6) MCUs at a time. So it is mainly used in mass production line. As gang programmer is standalone type, it does not require host PC. Figure 1-7 Gang programmer November, 2018 Rev.1.8...

  • Page 19: Block Diagram

    MC96FR116C 2. BLOCK DIAGRAM P10/DSCL P11/DSDA P12/REM_PP_OUT CARRIER GENERATOR P05~P00 REM_OD_OUT PORT On-Chip Debug AMP / REM_OD_OUT IR Control /SENSOR P15~P10 M8051 PORT CORE P02/EC0 (2048B + 256B) P00/EC2 P04/EC3 TIMER P03/T0 & P03/T1/PWM1 FLASH (16KB) P01/T2 P03/SDA P05/PWM3 P02/SCL Power On Reset Brown Out...

  • Page 20: Pin Configurations

    MC96FR116C 3. PIN CONFIGURATIONS 16 WLCSP (MC96FR116C) 0.4 Typ. 16 WLCSP 1.6 Typ. 1.6 Typ. P11/DSDA VDD_IR P10/DSCL REMOUT_PP/P12 REMOUT_OD P13/XIN P05/INT5/TXD P03/INT3/SDA P14/XOUT P15/RESETB P04/INT4/RXD P02/INT2/SCL P01/INT1 P00/INT0 Figure 3-1 16 WLCSP Pin-out of MC96FR116CW November, 2018 Rev.1.8...

  • Page 21: Figure 1-5 E

    MC96FR116C 16 QFN (MC96FR116CU) P11/DSDA P13/XIN P10/DSCL MC96FR116CU (16QFN) P05/INT5/TXD/ P14/XOUT *EP : PWM3 OPEN P15/RESETB P04/INT4/RXD Figure 3-2 16 QFN Pin-out of MC96FR116CU November, 2018 Rev.1.8...

  • Page 22: Figure 3-3 20 Tssop Pin-Out Of Mc96Fr116Cr

    MC96FR116C 20 TSSOP (MC96FR116CR) VDD_IR REM_OD/SENSOR P12/REM_PP P11/DSDA P13/XIN P10/DSCL P14/XOUT MC96FR116CR 20 TSSOP P15/RESETB P05/INT5/TXD/PWM3 P04/INT4/RXD P00/INT0/SS P03/INT3/T0/PWM1 P01/INT1/XCK P02/INT2 Figure 3-3 20 TSSOP Pin-out of MC96FR116CR November, 2018 Rev.1.8...

  • Page 23: Package Dimension

    MC96FR116C 4. PACKAGE DIMENSION Figure 4-1 PKG DIMENSION (16 WLCSP) November, 2018 Rev.1.8...

  • Page 24: Figure 4-2 Pkg Dimension (16 Qfn)

    MC96FR116C Figure 4-2 PKG DIMENSION (16 QFN) November, 2018 Rev.1.8...

  • Page 25: Figure 4-3 Pkg Dimension (20 Tssop)

    MC96FR116C Figure 4-3 PKG DIMENSION (20 TSSOP) November, 2018 Rev.1.8...

  • Page 26: Pin Description

    MC96FR116C 5. PIN DESCRIPTION PIN Name Function @RESET Shared with NOTE1 - 6-bit I/O port, P0. Input INT0 - Can be set in input or output mode bitwise. NOTE1 INT1 - Internal pull-up resistor can be activated by setting PxnPU bit in PxPU register when this port is used as input port.

  • Page 27: Port Structures

    MC96FR116C 6. PORT STRUCTURES 6.1 General Purpose I/O Port LevelShift ( 1.8V to ExtVDD) LevelShift (ExtVDD to 1.8V) BODR PxBPC (pull-up control) PxPU (pull-up selection) PxOD (open-drain) (data) SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE SUB-FUNC DIRECTION PxIO (direction) R(400Ω) PORTx INPUT CMOS or Schmitt Level Input...

  • Page 28: External Interrupt I/O Port

    MC96FR116C 6.2 External Interrupt I/O Port LevelShift ( 1.8V to ExtVDD) LevelShift (ExtVDD to 1.8V) BODR PxBPC (pull-up control) PxPU (pull-up selection) PxOD (open-drain) (data) SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE SUB-FUNC DIRECTION PxIO (direction) R(400Ω) EXTERNAL INTERRUPT POLARITY INTERRUPT ENABLE EDGE FLAG CLEAR...

  • Page 29: Rem_Pp_Out Port

    MC96FR116C 6.3 REM_PP_OUT Port Figure 6-3 REM_PP_OUT port 6.4 REM_OD_OUT Port Figure 6-4 REM_OD_OUT port November, 2018 Rev.1.8...

  • Page 30: Electrical Characteristics

    MC96FR116C 7. ELECTRICAL CHARACTERISTICS Unless otherwise noted, VDD = V ~ 3.6V, TA=-20~+70℃. BODR 7.1 Absolute Maximum Ratings Parameter Symbol Rating Unit -0.3~+4.0 Supply Voltage VDD_IR -0.3~+5.0 -0.3~+0.3 -0.3~VDD+0.3 Normal Voltage Pin -0.3~VDD+0.3 ∑ Total Power Dissipation 2500 VDD_IR Storage Temperature TSTG -45~+125 ℃...

  • Page 31: Voltage Dropout Converter(1.8V Internal Regulator) Characteristics

    MC96FR116C 7.4 VOLTAGE DROPOUT CONVERTER(1.8V Internal regulator) CHARACTERISTICS Parameter Symbol Condition Unit Regulation Voltage 1.62 1.98 Table 7-4 Voltage Dropout Converter Characteristics 7.5 BROWN OUT DETECTOR(BOD) CHARACTERISTICS Parameter Symbol Condition Unit NOTE 1.49 1.52 1.55 BODR NOTE 1.60 1.63 1.66 BODI0 NOTE 1.70...

  • Page 32: Internal Rc Oscillator Characteristics

    MC96FR116C 32bytes Program/Erase Cycle 10,000 Cycles Data Retention Years Table 7-7 FLASH Characteristics NOTE The minimum voltage of FLASH write is 1.55V. If FLASH is written, must be checked with V BODI0 7.8 Internal RC Oscillator CHARACTERISTICS Parameter Symbol Condition Unit ℃...

  • Page 33: Power-On Reset Characteristics

    MC96FR116C VDD_IR=1.8V, Input overdrive = 200mV Table 7-11 Analog Comparator Characteristics NOTE The recommended V (the reference voltage of IR AMP) is VDD_IR*62/64(IRCC0[2:0]=0x6 for the sensitivity of IR learning and the immunity of noise. 7.11 POWER-ON RESET CHARACTERISTICS Parameter Symbol Condition Unit RESET Release Level...

  • Page 34: Ac Characteristics

    MC96FR116C 7.13 AC CHARACTERISTICS Parameter Symbol Unit Operating Frequency fMCP System Clock Cycle Time tSYS XIN, Oscillation Stabilization Time (8MHz) tMST1 XOUT External Clock “H” or “L” Pulse Width tCPW External Clock Transition Time tRCP,tFCP Interrupt Input Width INT0~INT5 RESETB Input Pulse “L” Width tRST RESETB Rising time of REM_OD_OUT...

  • Page 35: Figure 7-1 Ac Timing

    MC96FR116C 1/fMCP tCPW tCPW 0.9VDD 0.1VDD tRCP tFCP 0.8VDD INT0~INT5 0.2VDD tRST RESETB 0.2VDD tECW tECW 0.8VDD 0.2VDD tREC tFEC Figure 7-1 AC Timing November, 2018 Rev.1.8...

  • Page 36: I2C Characteristics

    MC96FR116C 7.14 I2C CHARACTERISTICS The following table and figure show the timing codition of SDA and SCL bus lines for I C bus devices. STANDARD MODE FAST MODE Parameter Symbol Unit SCL clock frequency Hold time after (repeated) START condition. After this period, the first clock HD;STA pulse is generated LOW period of the SCL clock...

  • Page 37: Rem_Pp_Out Port Characteristics

    MC96FR116C 7.15 REM_PP_OUT PORT CHARACTERISTICS The characteristics of REM_PP_OUT is related with VDD, not VDD_IR. IOL(mA) VDD=4V VDD=3V VDD=2V VOL(V) Figure 7-3 IOL vs VOL for REM_PP_OUT VOH(V) VDD=2V VDD=3V VDD=4V IOH(mA) Figure 7-4 IOH vs VOH for REM_PP_OUT November, 2018 Rev.1.8...

  • Page 38: Rem_Od_Out Port Characteristics

    MC96FR116C 7.16 REM_OD_OUT PORT CHARACTERISTICS The characteristics of REM_OD_OUT is related with VDD_IR, not VDD. Figure 7-5 Characteristics for REM_OD_OUT 7.17 TYPICAL CHARACTERISTICS These graphs and tables provided in this section are for design guidance only and are not tested or guaranteed.

  • Page 39: Memory

    MC96FR116C 8. MEMORY The MC96FR116C has separate address spaces for Program and Data Memory. The logical separation of Program and Data Memory allows the Data Memory to be accessed by 8-bit addresses, which can be more quickly stored and manipulated by an 8-bit CPU. Nevertheless, 16-bit Data Memory addresses can also be generated through the DPTR register.

  • Page 40: Iram

    MC96FR116C 8.2 IRAM Upper Special Function 128 Bytes Registers Internal RAM 128 Bytes (Indirect Addressing) (Direct Addressing) Lower 128 Bytes Internal RAM (Direct or Indirect Addressing) Figure 8-2 DATA MEMORY (IRAM) Internal Data Memory is mapped in Figure 8-2. The memory space is shown divided into three blocks, which are generally referred to as the Lower 128, the Upper 128, and SFR space.

  • Page 41: Figure 8-3 Lower 128 Byte Of Iram

    MC96FR116C General purpose 80 bytes register 16 bytes Bit addressable (128bits) Register bank 3 8 bytes (8 bytes) Register bank 2 8 bytes (8 bytes) Register bank 1 8 bytes (8 bytes) Register bank 0 8 bytes (8 bytes) Figure 8-3 Lower 128 Byte of IRAM 8.2.1 Indirect Address Area Note that in Figure 8.2 the SFRs and the indirect address RAM have the same addresses (80 Nevertheless, they are two separate areas and accessed in two different ways.
  • Page 42 MC96FR116C Register Bank 0~3 Locations 00 through 1F (32 bytes). ASM-51 and the device after reset default to register bank 0. To use the other register banks the user must select them in the software (refer to the MCS-51 Micro Assembler User’s Guide). Each register bank contains 8 one-byte registers, 0 through 7.

  • Page 43: Figure 8-4 Psw Register

    MC96FR116C Data Pointer Register (DPTR) The Data Pointer (DPTR) is a 16-bit register which is used to form 16- bit addresses for External Data Memory accesses (MOVX A, @DPTR and MOVX @DPTR, A), for program byte moves (MOVC A, @A+DPTR) and for indirect program jumps (JMP @A+DPTR). Two true 16-bit operations are allowed on the Data Pointer –...

  • Page 44: Xram

    MC96FR116C 8.3 XRAM There’s another kind of RAM called XRAM (External RAM) in MC96FR116C and the size is 2048B, NOTE 0000 through 07FF . This address space is assigned to XDATA region and used for data storage. 07FF Upper 2048 Bytes Internal XRAM (Direct Addressing) 0000...

  • Page 45: Registers

    MC96FR116C 8.4 Registers 8.4.1 SFR Map Reserved M8051 Compatible NOTE 0H/8H 1H/9H 2H/AH 3H/BH 4H/CH 5H/DH 6H/EH 7H/FH CFGCR --00_0000 WTCR0H WTCR0L WTCR1H WTCR1L WTCR2H WTCR2L KITSR 0000_0000 FARH FARM FARL FTCR MCCR UCTRL01 UCTRL02 UCTRL03 USTAT0 UBAUD0 UDATA0 0000_0000 WTDRH IRCC0 IRCC1...
  • Page 46 MC96FR116C 8.4.2 XSFR Map Page Buffer (32Bytes) 0H/8H 1H/9H 2H/AH 3H/BH 4H/CH 5H/DH 6H/EH 7H/FH 8020 8018 PBUF_18 PBUF_19 PBUF_1A PBUF_1B PBUF_1C PBUF_1D PBUF_1E PBUF_1F 8010 PBUF_10 PBUF_11 PBUF_12 PBUF_13 PBUF_14 PBUF_15 PBUF_16 PBUF_17 8008 PBUF_08 PBUF_09 PBUF_0A PBUF_0B PBUF_0C PBUF_0D PBUF_0E PBUF_0F...
  • Page 47 MC96FR116C 8.4.3 Compiler Compatible SFR Refer to section 8.2.3 for detailed description of these registers. ACC (Accumulator) Initial value : 00 Accumulator B (B Register) Initial value : 00 B Register SP (Stack Pointer) Initial value : 07 Stack Pointer DPL (Data Pointer Low Byte) Initial value : 00 Data Pointer Low Byte...
  • Page 48 MC96FR116C Initial value : 00 Carry Flag. Receives carry out from bit 1 for ALU operands. Auxiliary Carry Flag. Receives carry out from bit 1 of addition operands. General Purpose Status Flag Register Bank Selection bit 1 Register Bank Selection bit 0 Overflow Flag.

  • Page 49: I/O Ports

    MC96FR116C 9. I/O PORTS 9.1 Introduction The MC96FR116C has four I/O ports (P0, P1). Each port can be easily configured by software whether to use internal pull up resistor or not, whether to use open drain output or not, or whether the pin is input or output.
  • Page 50 MC96FR116C 9.2.6 Pin Change Interrupt Enable Register (P0PC) P0 port support Pin Change Interrupt (PCI) function. Pin Change Interrupt will trigger if any pin changes its status when P0nPC is set to 1. At reset, PCI function is disabled for all P0 pins. 9.2.7 Register Map Name Address...
  • Page 51 MC96FR116C 9.2.8 PORT 0 P0 (P0 Data Register) Initial value : 00 P0[7:0] I/O Data P0IO (P0 Direction Register) P07IO P06IO P05IO P04IO P03IO P02IO P01IO P00IO Initial value : 00 P0IO[7:0] P0 Direction Input Output P0PU (P0 Pull-up Resistor Selection Register) 2F00 P07PU P06PU...
  • Page 52 MC96FR116C Changed to input port and pull-up resistor is activated P0PC (P0 Pin Change Interrupt Enable Register) P07PC P06PC P05PC P04PC P03PC P02PC P01PC P00PC Initial value : 00 P0PC[7:0] Control Pin Change Interrupt function Disable PCI function Enable PCI function 9.2.9 PORT 1 P1 (P1 Data Register) Initial value : 00...
  • Page 53 MC96FR116C P1OD[7:0] Control P1 port type when configured as output port. Push-pull type output drive Open-drain type output drive P1BPC (P1 Pull-up Control Register) 2F51 P17BPC P16BPC P15BPC P14BPC P13BPC P12BPC P11BPC P10BPC Initial value : FB P1BPC[7:0] Control port direction and use of internal pull-up resistor when external VDD drops below V level.
  • Page 54 MC96FR116C IRPUD IR learning pull-up dynamic control with polarity of IR comparator output. Dynamic pull-up is used with IRPUST1 and IRPUST2 Disable Enable TRODSR The fast slew rate of REM_OD_OUT control. Refer to tREM_OD_R and tREM_OD_F of “7.12 AC CHARACTERISTICS” Disable.

  • Page 55: Interrupt Controller

    MC96FR116C 10. Interrupt Controller 10.1 Overview The interrupt controller has the following features to handle interrupt request from internal peripherals or external pins. NOTE support up to 21 interrupt sources 6 group of 4 priority level multiple interrupts handling global enable by EA bit and selective control by IEx bit Interrupt latency : 3~9 machine cycles in single interrupt system NOTE Interrupt controller can accept up to 24 interrupt sources, but there are only 19 interrupt sources in...

  • Page 56: External Interrupt

    MC96FR116C 10.2 External Interrupt The External Interrupts are triggered by the INT0, INT1, INT2, INT3 INT4 and INT5 pins. The External Interrupts can be triggered by a falling or rising edge or a low or high level. The trigger mode and trigger level is controlled by External Interrupt Edge Register (EIEDGEx) and External Interrupt Polarity Register (EIPOLA).

  • Page 57: Block Diagram

    MC96FR116C 10.3 Block Diagram IE[A8 IP[B8 IP1[F8 EIEDGE EIPOLA EIFLAG.0[`AC Priority High INT0 FLAG0 EIFLAG.1[`AC FLAG1 INT1 EIFLAG.2[`AC FLAG2 INT2 EIFLAG.3[`AC FLAG3 INT3 EIFLAG.4[`AC INT4 FLAG4 EIFLAG.5[`AC FLAG5 INT5 IE1[A9 INT6 BODIF INT7 USTAT0.5 [E5 UART RX0 INT8 USTAT0.7/6 [E5 UART TX0 INT9 INT10...

  • Page 58: Interrupt Vectors

    MC96FR116C 10.4 Interrupt Vectors There are 16 interrupt sources which are from internal peripherals or from external pin inputs. When a interrupt is requested while EA bit in IE register and its individual enable bit INTnE in IEx register is set, the CPU executes a long call instruction (LCALL) to the vector address listed in Table 10-2.

  • Page 59: Effective Time Of Interrupt Request

    MC96FR116C the program address is retrieved from the stack by executing RETI instruction to restart from the position where the interrupt is accepted. The following figure shows the sequence. NOTE Interrupt flags due to UART TX and FLASH are not auto-cleared when the CPU accepts the request. IE.EA Flag ...

  • Page 60: Multiple Interrupts

    MC96FR116C EA & INTnE set Next Instruction Setting both EA bit and individual interrupt enable bit INTnE makes the pending interrupt active after executing the next instruction. Next Instruction Figure 10-4 Effective time of interrupt request after setting IEx registers 10.7 Multiple Interrupts If more than two interrupts are requested simultaneously, one of higher priority level is serviced first and others remain pending.

  • Page 61: Interrupt Service Procedure

    MC96FR116C IP1 registers. Other interrupts having lower group priority than INT0 cannot be serviced until INT0 service routine is finished even if the INT0 interrupt handler allows those interrupt requests. Example) Software Multi Interrupt INT1 : IE, #01H ;Enable INT0 only IE1, #00H ;Disable other interrupts IE, #0FFH...

  • Page 62: Saving And Restoring General Purpose Registers

    MC96FR116C Basic Interval Timer Basic Interval Timer Vector Table Address Service Routine Address 0093H 0125H 0094H 0126H 0095H Figure 10-7 Generating branch address to BIT interrupt service routine from vector table 10.10 Saving and Restoring General Purpose Registers INTxx : PUSH PSW PUSH DPL Main Task...

  • Page 63: Interrupt Timing

    MC96FR116C 10.11 Interrupt Timing Interrupt sampled here NOTE CLP2 CLP1 CLP2 C1P1 C1P2 C2P1 C2P2 SCLK INT_SRC INTR_ACK LAST_CYC INTR_LCALL 8-bit interrupt Vector INT_VEC {8’h00, INT_VEC} PROGA Figure 10-9 Timing chart for Interrupt Accept and Branch Address Generation The interrupt request is sampled at the last cycle of the command currently being executed. On recognition of interrupt request, the interrupt controller hands over the corresponding lower 8-bit vector address to the CPU, M8051W and the CPU acknowledges the request at the first cycle of the next command to jump to the interrupt vector address.
  • Page 64 MC96FR116C EIPS2 2F1A External Interrupt Port Select 2 Register EIPS3 2F1B External Interrupt Port Select 3 Register EIPS4 2F1C External Interrupt Port Select 4 Register EIPS5 2F1D External Interrupt Port Select 5 Register Table 10-3 Register Map of Interrupt Controller 10.12.2 Interrupt Enable Register (IE, IE1, IE2, IE3) There’re 4 interrupt enable registers which are IE, IE1, IE2 and IE3.
  • Page 65 MC96FR116C .0<= EIPSx <= 7 : external interrupt x port is P0[EIPSx] .8<= EIPSx <= 15: external interrupt x port is P1[EIPSx-8] 10.12.8 Register Description IE (Interrupt Enable Register) INT5E INT4E- INT3E INT2E INT1E INT0E R/W- Initial value : 00 Global Interrupt Enable Bit Ignore interrupt request from any interrupt source.
  • Page 66 MC96FR116C INT9E Enable or disable UART TX0 Interrupt Disable Enable INT8E Enable or disable UART RX0 Interrupt Disable Enable INT7E Enable or disable BOD Flag Interrupt Disable Enable INT6E Enable or disable IRI Input Interrupt Disable Enable IE2 (Interrupt Enable Register 2) INT17E INT16E- INT15E...
  • Page 67 MC96FR116C INT22E Reserved Disable Enable INT21E Enable or disable Pin Change Interrupt Disable Enable INT20E Enable or disable KEYSCAN Interrupt Disable Enable INT19E Enable or disable FLASH Interrupt Disable Enable INT18E Enable or disable BIT Interrupt Disable Enable IP (Interrupt Priority Register) R/W- Initial value : 00 IP1 (Interrupt Priority Register 1)
  • Page 68 MC96FR116C EDGE3R EDGE3F EDGE2R EDGE2F EDGE1R EDGE1F EDGE0R EDGE0F R/W- R/W- R/W- Initial value : 00 EDGEnR Selects the trigger mode of each external interrupt pin. Trigger mode is also affected by the EDGEnF bit. External interrupt is triggered by level (default) External interrupt is triggered by a rising edge EDGEnF Selects the trigger mode of each external interrupt pin.
  • Page 69 MC96FR116C EIPS1 (External Interrupt Port Selection 1 Register) 2F19 EIPS17 EIPS16 EIPS15 EIPS14 EIPS13 EIPS12 EIPS11 EIPS10 Initial value : 01 EIPS1[3:0] Configure external interrupt 1 port pin as some pin EIPS2 (External Interrupt Port Selection 2 Register) 2F1A EIPS27 EIPS26 EIPS25 EIPS24...

  • Page 70: Peripheral Units

    MC96FR116C 11. Peripheral Units 11.1 Clock Generator 11.1.1 Overview The clock generator module plays a main role in making a stable operating clock, SCLK. There are two clock sources in MC96FR116C, which are the output of main oscillator connected to the XIN and XOUT pins and the output of INT-RC oscillator.
  • Page 71 MC96FR116C 11.1.3 Register Map Name Address Default Description SCCR System and Clock Control Register MCCR Main Oscillator Clock Control Register Table 11-1 Register Map of Clock Generator 11.1.4 Register Description SCCR (System and Clock Control Register) ROSCEN DIV1 DIV0 BCLKS MOSCEN IOSCEN CLKSEL...

  • Page 72: Basic Interval Timer (Bit)

    MC96FR116C MCCR (Main Oscillator Clock Control Register) ISELM1 ISELM0 ISEL1 ISEL0 Initial value : 33 ISELM[1:0] Monitors the current strength of main oscillator. ISELM is updated with ISEL at the MOSCEN of SCCR is 0 or STOP mode. ISELM1 ISELM1 Description ISEL[1:0] Selects the current strength of main oscillator.

  • Page 73: Figure 11-2 Block Diagram Of Bit

    MC96FR116C 11.2.2 Block Diagram ÷16 ÷32 WDT Source Clock 8-bit up-counter SCLK . . . (System Clock) Overflow BITR BITIF BIT Interrupt ÷2048 RING BCLKS BCLR ÷ 256 (1MHz) BCCR Read From CPU Interal BUS line Figure 11-2 Block Diagram of BIT 11.2.3 Register Map Name Address...
  • Page 74 MC96FR116C /2^8 16.384ms /2^9 32.768ms (default) /2^10 65.536ms /2^11 131.072ms BCLR Clears BIT Counter. Writing ‘1’ to this bit resets BIT counter to 00 BCLR bit is auto cleared. BIT counter free runs BIT counter is cleared and counter re-starts PRD[2:0] Selects BIT interrupt interval.

  • Page 75: Watch Dog Timer (Wdt)

    MC96FR116C 11.3 Watch Dog Timer (WDT) 11.3.1 Overview The WDT, if enabled, generates an interrupt or a system reset when the WDT counter reaches the given time-out value set in WDTR. In normal operation mode, it is required that the user software clears the WDT counter by setting WDTCL bit in WDTMR register before the time-out value is reached.

  • Page 76: Figure 11-4 Wdt Interrupt And Reset Timing

    MC96FR116C 11.3.3 Register Map Name Address Default Description WDTR Watch Dog Timer Register WDTCR Watch Dog Timer Counter Register WDTMR Watch Dog Timer Mode Register Table 11-3 Register Map of WDT 11.3.4 WDT Interrupt Timing Source Clock BIT Overflow WDTCR[7:0] Counter Clear WDTR[7:0] WDTCL...

  • Page 77: Timer/Pwm

    MC96FR116C 11.4 TIMER/PWM 11.4.1 Register Description WDTR (Watch Dog Timer Register, Write Case) WDTR7 WDTR 6 WDTR 5 WDTR 4 WDTR 3 WDTR 2 WDTR 1 WDTR 0 Initial value : FF WDTR[7:0] Time-out value of WDT counter (=the period of WDT interrupt) WDT Interrupt Interval = (BIT Interrupt Interval) x (WDTR + 1) Precaution must be taken when writing this register.
  • Page 78 MC96FR116C 11.4.2 8-bit Timer/Event Counter 0, 1 11.4.2.1 Overview Timer 0 and Timer 1 can be used as either separate 8-bit Timer/Counter or one combined 16-bit Timer/Counter. Each 8-bit Timer/Event Counter module has a multiplexer, 8-bit timer data register, 8- bit counter register, mode control register, input capture register and comparator.

  • Page 79: Figure 11-5 Block Diagram Of Timer 0,1 In 8-Bit Timer/Counter Mode

    MC96FR116C 11.4.2.2 8-Bit Timer/Counter Mode 8-bit Timer/Counter Mode is selected when the T0CR and T1CR registers are configured as follows. ADDRESS : B2 T0EN T0_PE CAP0 T0CK2 T0CK1 T0CK0 T0CN T0CR T0ST INITIAL VALUE : 0000_0000 ADDRESS : B4 T1CR POL1 16BIT CAP1...

  • Page 80: Figure 11-6 Interrupt Period Of Timer 0, 1

    MC96FR116C Match with T0DR/T1DR T0DR/T1DR Value Count Pulse Period Up-count TIME Interrupt Period x (n+1) Timer 0, 1 (T0IF, T1IF) Occur Occur Occur Interrupt Interrupt Interrupt Interrupt Figure 11-6 Interrupt Period of Timer 0, 1 T0DR/T1DR Value Disable Enable Clear &Start STOP Up-count TIME...

  • Page 81: Figure 11-8 Block Diagram Of Timer 0, 1 In 16-Bit Timer/ Counter Mode

    MC96FR116C 11.4.2.3 16-bit Timer/Counter Mode When Timer 0, 1 are configured as 16-bit Timer/Counter Mode, Timer 0 becomes the lower part of the new 16-bit counter. When the lower 8-bit counter T0 matches T0DR and higher 8-bit counter T1 matches T1DR simultaneously, a 16-bit timer interrupt is issued via Timer 0 interrupt(not Timer 1). Both T0 and T1 should use the same clock source, which leads to the configuration, T1CK1=1, T1CK0=1 and 16BIT=1 in T1CR register.
  • Page 82 MC96FR116C 11.4.2.4 8-bit Capture Mode By setting CAP0(CAP1) to ‘1’ in T0CR(T1CR) register, Timer 0(Timer 1) operates in Capture Mode. Basic timer function is still effective even in capture mode. So when the counter value reaches to the pre-defined data value in data register, an interrupt can be issued. When an external interrupt generating condition is detected on port P36(P37), the counter value is captured into capture register CDR0(CDR1).

  • Page 83: Figure 11-9 Block Diagram Of Timer 0, 1 In 8-Bit Capture Mode

    MC96FR116C ADDRESS : B2 T0CR T0EN T0_PE CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST INITIAL VALUE : 0000_0000 ADDRESS : B4 T1CR POL1 16BIT CAP1 T1CK1 T1CK0 T1CN T1ST INITIAL VALUE : 0000_0000 T0ST T0EN&T0CN ÷2 8-bit Timer2 Counter ÷4 ÷16 T0(8-bit) ÷64 SCLK...

  • Page 84: Figure 11-10 Timer 0,1 Operation In 8-Bit Input Capture Mode

    MC96FR116C CDR0, CDR1 Load T0/T1 Value Count Pulse Period Up-count TIME Ext. INT0 PIN Interrupt Request (INT0F,INT1F) Interrupt Interval Period Figure 11-10 Timer 0,1 Operation in 8-bit Input Capture Mode T0, T1 Interrupt Request (T0F,T1F) Ext. INT0 PIN Interrupt Request (INT0F,INT1F) Interrupt Interval Period = FF + FF...

  • Page 85: Figure 11-12 Block Diagram Of Timer 0, 1 In 16-Bit Capture Mode

    MC96FR116C 11.4.2.5 16-bit Capture Mode If two 8-bit timers are combined to operate as a single 16-bit timer, this new timer can be in 16-bit Capture Mode. The operating mechanism is just like a 8-bit timer in capture mode except counter and capture register is 16-bit wide which are concatenated T0+T1 and CDR0+CDR1.

  • Page 86: Figure 11-13 Block Diagram Of Timer 1 In Pwm Mode

    MC96FR116C Frequency Resolution T1CK[1:0]=00 (125ns) T1CK[1:0]=01 (250ns) T1CK[1:0]=10 (2us) 10-bit 7.8KHz 3.9KHz 0.49KHz 9-bit 15.6KHz 7.8KHz 0.98KHz 8-bit 31.2KHz 15.6KHz 1.95KHz 7-bit 62.4KHz 31.2KHz 3.91KHz Table 11-5 PWM Frequency vs. Resolution (In case frequency of SCLK(=f ) is 8MHz) SCLK The POL bit in T1CR register determines the polarity of PWM waveform.

  • Page 87: Figure 11-14 Example Of Pwm Waveform

    MC96FR116C Source Clock SCLK T1/PWM1 POL0 = 1 T1/PWM1 POL0 = 1 Duty Cycle(1+80 )X250ns = 32.25us )X250ns = 256us  3.9kHz Period Cycle(1+3FF T1CK[1:0] = 00 PWM1PR(8-bit) SCLK PWM1HR = 03 PWM1PR = FF PWM1DR = 80 PWM1DR(8-bit) Figure 11-14 Example of PWM Waveform (In case frequency of SCLK(=f ) is 4MHz) SCLK T1CR[1:0] = 10...
  • Page 88 MC96FR116C T1DR Timer 1 Data Register PWM1PR Timer 1 PWM Period Register Timer 1 Register PWM1DR Timer 1 PWM Duty Register CDR1 Capture 1 Data Register PWM1HR Timer 1 PWM High Register Table 11-6 Register Map of Timer 0, 1 11.4.2.8 Register Description T0CR (Timer 0 Mode Control Register) T0EN...
  • Page 89 MC96FR116C Initial value : 00 T0[7:0] T0 Counter value T0DR (Timer 0 Data Register, Write Case) T0D7 T0D6 T0D5 T0D4 T0D3 T0D2 T0D1 T0D0 Initial value : FF T0D[7:0] T0 Compare data CDR0 (Capture 0 Data Register, Read Case) CDR07 CDR06 CDR05 CDR04...
  • Page 90 MC96FR116C Stops counting Clear counter and starts up-counting T1DR (Timer 1 Data Register, Write Case) T1D7 T1D6 T1D5 T1D4 T1D3 T1D2 T1D1 T1D0 Initial value : FF T1D[7:0] T1 Compare data PWM1PR (Timer 1 PWM Period Register, Write Case) T1PP7 T1PP6 T1PP5 T1PP4...
  • Page 91 MC96FR116C Initial value : 00 T1_PE Controls whether to output Timer 1 output or not through I/O pin. Note this bit is write-only. Timer 1 output does not come out through I/O pin Timer 1 output overrides the normal port functionality of I/O pin PW1H[3:2] High (bit [9:8]) value of PWM period PW1H[1:0]...

  • Page 92: Figure 11-16 Block Diagram Of 16-Bit Timer 2 In Output Compare Or Event Counter Mode

    MC96FR116C ADDRESS : CE EC2E T2_PE CAP2 T2CK2 T2CK1 T2CK0 T2CN T2CR T2ST INITIAL VALUE : 0000_0000 EC2 (or IRSensor) T2ST T2CN ÷1 16-bit Timer2 Counter ÷2 ÷4 Clear ÷8 (8-bit) (8-bit) SCLK ÷16 ÷64 ÷256 Timer2 T2IF Interrupt Comparator T2DRH T2DRL (8-bit)

  • Page 93: Figure 11-18 Block Diagram Of Timer 2 In Carrier Counting Mode

    MC96FR116C When T2H+T2L reaches to the value of T2DRH+T2DRL, an interrupt is requested if enabled. When a compare-match occurs, the counter values T2H and T2L are captured into the capture registers CDR2H and CDR2L respectively. At the same time, the counter is cleared to 0000 and starts up- counting.
  • Page 94 MC96FR116C Timer 2 Counter Low T2DRL Timer 2 Data Register Low CDR2L Timer 2 Capture Data Register Low Table 11-7 Register Map of Timer 2 11.4.3.6 Register Description CDR2H, T2DRH and T2H registers share peripheral address. Reading T2DRH gives CDR0 in Capture Mode, T2H in Output Compare Mode.
  • Page 95 MC96FR116C T2L7 T2L6 T2L5 T2L4 T2L3 T2L2 T2L1 T2L0 Initial value : 00 T2L[7:0] T2 Counter Low T2DRL (Timer 2 Data Register Low, Write Case) T2DRL7 T2DRL6 T2DRL5 T2DRL4 T2DRL3 T2DRL2 T2DRL1 T2DRL0 Initial value : FF T2DRL[7:0] T2 Compare Data Low CDR2L (Capture Data Register 2 Low, Read Case) CDR2L7 CDR2L6...
  • Page 96 MC96FR116C 11.4.4 16-bit Timer 3 11.4.4.1 Overview 16-bit Timer 3 is composed of Multiplexer, Timer Data Register High/Low, Timer Register High/Low, Input Capture Register High/Low, Mode Control Register, PWM Duty High/Low and PWM Period High/Low Register. Timer 3 is can be clocked by Carrier Signal(CRF) from Carrier Generator module or by an internal clock source deriving from clock divider logic where the base clock is SCLK.

  • Page 97: Figure 11-19 Block Diagram Of Timer 3 In Output Compare Or Event Counter Mode

    MC96FR116C ADDRESS : CA PWM3 EC3E CAP3 T3CK2 T3CK1 T3CK0 T3CN T3CR T3ST INITIAL VALUE : 0000_0000 ADDRESS : C9 T3CR2 T3REQ T2REQ T1REQ T0REQ T3_PE INITIAL VALUE : 0000_--00 (or IR Sensor) T3ST T3CN ÷1 16-bit Timer3 Counter ÷2 ÷4 Clear ÷8...

  • Page 98: Figure 11-20 Block Diagram Of Timer 3 In Capture Mode

    MC96FR116C ADDRESS : CA T3CR PWM3 EC3E T3CK2 T3CK1 T3CK0 T3CN T3ST INITIAL VALUE : 0000_0000 ADDRESS : C9 T3CR2 T3REQ T2REQ T1REQ T0REQ T3_PE INITIAL VALUE : 0000_--00 (or IR Sensor) T3ST T3CN ÷1 ÷2 16-bit Counter ÷4 ÷8 T3H(8-bit) T3L(8-bit) SCLK...

  • Page 99: Figure 11-21 Block Diagram Of Timer 3 In Carrier Counting Mode

    MC96FR116C ADDRESS : CA T3CR PWM3 EC3E T3CK2 T3CK1 T3CK0 T3CN T3ST INITIAL VALUE : 0000_0000 ADDRESS : DF T3EDG T3EDG T2EDG T2EDG IRCC2 T3IR T2IR INITIAL VALUE : 0000_0000 T3ST T3CN 16-bit Timer3 Counter Clear IR Sensor (8-bit) (8-bit) Timer3 T3IF Interrupt...

  • Page 100: Figure 11-22 Block Diagram Of Timer 3 In Pwm Mode

    MC96FR116C ADDRESS : CA T3CR PWM3 T3ST EC3E T3CK2 T3CK1 T3CK0 T3CN INITIAL VALUE : 0000_0000 ADDRESS : C9 T3CR2 T3REQ T2REQ T1REQ T0REQ T3_PE INITIAL VALUE : 0000_--00 16-bit Timer3 PWM Period Register PWM3PRH PWM3PRL (8-bit) (8-bit) T3_PE ÷1 T3ST T3CN ÷2...

  • Page 101: Figure 11-23 Example Of Pwm Waveform

    MC96FR116C Source Clock SCLK T3/PWM3 POL0 = 1 T3/PWM3 POL0 = 1 Duty Cycle(1+0080 )X500ns = 64.50us )X500ns = 512us  1.95kHz Period Cycle(1+03FF T3CK[2:0] = 00 PWM3PRH(8-bit) PWM3PRL(8-bit) SCLK PWM3PRH = 03 PWM3PRL = FF PWM3DRH = 00 PWM3DRH(8-bit) PWM3DRL(8-bit) PWM3DRL = 80 Figure 11-23 Example of PWM waveform (In case of f...
  • Page 102 MC96FR116C CDR3L, PWM3DRL and T3L registers share peripheral address. When PWM mode is enabled, reading this address gives PWM3DRL. When PWM mode is disabled, reading this address gives CDR3L in Capture Mode or T3L in Output Compare Mode. Writing this address alters PWM3DRL when PWM3E bit is ‘1’.
  • Page 103 MC96FR116C Timer 2 interrupt not occurred Timer 2 interrupt occurred NOTE T1REQ Timer 1 Interrupt Flag Timer 1 interrupt not occurred Timer 1 interrupt occurred NOTE T0REQ Timer 0 Interrupt Flag Timer 0 interrupt not occurred Timer 0 interrupt occurred POL3 Selects polarity of PWM PWM waveform is low for duty value...
  • Page 104 MC96FR116C CDR3H (Capture Data Register 3 High, Read Case) CDR3H7 CDR3H6 CDR3H5 CDR3H4 CDR3H3 CDR3H2 CDR3H1 CDR3H0 Initial value : 00 CDR3H[7:0] T3 Capture Data High PWM3DRH (PWM3 Duty Register High, Write Case) T3PDH7 T3PDH6 T3PDH5 T3PDH4 T3PDH3 T3PDH2 T3PDH1 T3PDH0 Initial value : 00 T3PDH[7:0]...
  • Page 105 MC96FR116C P3PPH7 P3PPH6 P3PPH5 P3PPH4 P3PPH3 P3PPH2 P3PPH1 P3PPH0 Initial value : FF P3PPH[7:0] PWM3 Period High NOTE Writing is effective only when PWM3E = 1 and T3ST = 0. November, 2018 Rev.1.8...

  • Page 106: Watch Timer With Event Capture Function (Wt)

    MC96FR116C 11.5 Watch Timer with event capture function (WT) 11.5.1 Overview The watch timer (WT) has the function for RTC (Real Time Clock) operation. This module consists of the clock source select circuit, timer counter circuit, output select circuit and control registers. To activate watch timer, determine the input clock source, output interval and then set WTEN bit in Watch Timer Mode Register (WTMR).

  • Page 107: Figure 11-25 Block Diagram Of Watch Timer In Ir Capture Mode

    MC96FR116C IRCC1 CAP0/1/2EN (=Capture & IRCEN PHASE WTIR Clear source) WTCR0H/L WTCR1H/L WTCR2H/L WTCL WTCL WTCL CAP0EN CAP1EN CAP2EN ÷1 OVF = T x WTIR ÷2 14-bit Up Counter (WTIR) SCLK ÷3 ÷4 WTIF WTDR1:WTDR0 CP r SCLK WTMR WTEN WTCL WTCK1 WTCK0 RESETB...
  • Page 108 MC96FR116C 11.5.3 Register Map Name Address Default Description WTMR Watch Timer Mode Register WTDR1 Watch Timer Data Register 1 WTDR0 Watch Timer Data Register 0 WTSR Watch Timer Status Register WTDRH Watch Timer Data Register High WTCR0H Watch Timer Capture Register0 High WTCR0L Watch Timer Capture Register0 Low WTCR1H...
  • Page 109 MC96FR116C Initial value : 3F WTDR[13:8] Select WT overflow period. Reading this register returns the high 8-bit WTIR counter value. WT Interrupt Interval = (Twck x 2^14) x (7-bit WTDRH) + (Twck x 14-bit WTDR) WTDR0 (Watch Timer Data Register 0) WTDR7 WTDR6 WTDR5...
  • Page 110 MC96FR116C WTCR0L (Watch Timer Capture Register 0 Low) WTCR007 WTCR006 WTCR005 WTCR004 WTCR003 WTCR002 WTCR001 WTCR000 Initial value : FF WTCR0[7:0] When WT is in IR capture mode, the low 8-bit of WTIR counter is captured to this register at the first falling edge (when PHASE bit is ‘0’) or first rising edge (when PHASE bit is ‘1’) of input carrier signal.
  • Page 111 MC96FR116C captured to this register at the second falling edge (when PHASE bit is ‘0’) or second rising edge (when PHASE bit is ‘1’) of input carrier signal. This register is initialized by setting WTCL bit in WTMR. The WT interrupt is requested only when overflow condition occurs. That is when WT is in IR capture mode, the interrupt is not issued even when capture event is generated.

  • Page 112: Ir Capture Control (Ircc)

    MC96FR116C 11.6 IR Capture Control (IRCC) 11.6.1 Overview MC96FR116C has an IR capture module which receives and captures the incoming digital IR signal to detect the IR carrier frequency and count the carrier number. With this module, the Watch Timer and Timer 2 can be configured to operate in IR capture mode by setting IRCEN bit in IRCC1 register.

  • Page 113: Figure 11-29 Timing Diagram Of Ir Learning

    MC96FR116C SENSOR COMP_OUT 20/10KΩ Dynamic PULLUP (Note1) tIRPUDL (NOTE2) Note1. IRPUST[2:1]: 01  20KΩ Note2. IRPUDL[2:1]: 00  0.7us 10  10KΩ 01  1.0us 11  6.7KΩ (20KΩ//10KΩ) 10  1.5us 11  2.0us Figure 11-29 Timing Diagram of IR Learning 11.6.3 Register Map Name Address...
  • Page 114 MC96FR116C V0 (56/64 VDD_IR) V1 (57/64 VDD_IR) V2 (58/64 VDD_IR) V3 (59/64 VDD_IR) V4 (60/64 VDD_IR) V5 (61/64 VDD_IR) V6 (62/64 VDD_IR) V7 (63/64 VDD_IR) IRCC1 (IR Capture Register 1) IRCEN IRIIF IREDGE1 IREDGE0 IRPOL SINGLE PHASE Initial value : 00 IRCEN Control operation mode of WT, T2 and T3 IR capture mode is disabled, normal timer function...
  • Page 115 MC96FR116C Timer 3 is in normal operation Timer 3 calculates the number of incoming carrier signals. T2IR Make T3 to calculate the number of incoming carrier signal if CAP3 bit in T3CR bit is not ‘1’. Timer 2 is in normal operation Timer 2 calculates the number of incoming carrier signals.

  • Page 116: Carrier Generator

    MC96FR116C 11.7 Carrier Generator 11.7.1 Overview MC96FR116C has a specific module to generate carrier signal for remote control application. The internal carrier(CRF) signal is AND-ed with register value(RODR) and outputs through REMOUT port. The frequency and duty ratio of carrier signal is controlled by two 8-bit registers, CFRH and CFRL. Carrier signal can be on/off at previous stage of REMOUT port by the CEN bit in RMR register.
  • Page 117 MC96FR116C 11.7.3 Register Map Name Address Default Description Remocon Mode Register RMR2 2F56 Remocon Mode Register 2 RDCH Remocon Data Counter High CFRH Carrier Frequency Register High CFRL Carrier Frequency Register Low RDCL Remocon Data Counter Low RODR Remocon Output Data Register Remocon Output Buffer RDBH Remocon Data Buffer High...
  • Page 118 MC96FR116C Carrier Frequency Enable. This bit enables CRC counter. Carrier Frequency is not generated. Carrier Frequency is generated and goes out through the REMOUT port with RODR value and-ed. NOTE is the frequency of system clock, SCLK. SCLK RMR2 (Remocon Mode Register 2) 2F56 Initial value : 00 Carrier Mask Enable...
  • Page 119 MC96FR116C RDB7 RDB6 RDB5 RDB4 RDB3 RDB2 RDB1 RDB0 Initial value : FF RDB[7:0] Remote Data Low Buffer (Lower byte of RDB). The RDB is transferred to RDR when interrupt occurs. RDRH (Remocon Data Register High) RDR15 RDR14 RDR13 RDR12 RDR11 RDR10 RDR9...

  • Page 120: Figure 11-31 Period Of Carrier Signal And Remote Data Pulse

    MC96FR116C Initial value : 00 Remote Data Output ROB (Remocon Output Buffer) Initial value : 00 Remote Data Output Buffer 11.7.5 Carrier Signal and Data Pulse The Remote Out signal(=CGOUT in Block Diagram) on REMOUT port is generated from carrier signal and RODR value.

  • Page 121: Figure 11-32 Remout By Crf & Rob (In Case Of Cen=1, Rdpe=1)

    MC96FR116C 11.7.6 Examples of REMOUT control Three examples of controlling REMOUT port are shown below. RDPE Match with RDRH/RDRL Remocon Interrupt 0 or 1 RODR = 01 RODR=00 RODR=01 REMOUT : Min. 0.5us ~ Max. 32.64ms @ 4MHz Figure 11-32 REMOUT by CRF & ROB (In case of CEN=1, RDPE=1) The next figure shows the case carrier signal is off.

  • Page 122: Figure 11-33 Remout By Rob Only (In Case Of Cen=0, Rdpe=1)

    MC96FR116C RDPE Match with RDRH/RDRL Remocon Interrupt 0 or 1 RODR=01 RODR=00 RODR=01 RODR REMOUT : Min. 0.5us ~ Max. 32.64ms @ 4MHz Figure 11-33 REMOUT by ROB only (In case of CEN=0, RDPE=1) In the last figure, RODR is updated directly by writing to this register when the 16-bit Timer 2, 3 interrupts occur.
  • Page 123 MC96FR116C this flag is cleared when the interrupt is serviced, RDPE bit is cleared or software writes ‘0’ to the bit position. 11.7.8 Examples of Carrier Signal Selection The next table shows examples of selecting carrier signal according to CFRH and CFRL registers for two kinds of carrier clocks.

  • Page 124: Key Scan

    MC96FR116C 11.8 Key Scan 11.8.1 Overview Port 0 and Port 1 can be used as key input sources. If KEY interrupt is enabled, this can be a wake- up source in STOP mode. Usually Port 0(Port 1) is used as output strobe lines, and Port 1(Port 0) is used as key input sources.
  • Page 125 MC96FR116C 11.8.3 Register Map Name Address Default Description SMRR0 Standby Mode Release Register 0 SMRR1 Standby Mode Release Register 1 SRLC0 Standby Release Level Control Register 0 SRLC1 Standby Release Level Control Register 1 KITSR Key Interrupt Trigger Selection Register Table 11-15 Register Map of KEYSCAN module 11.8.4 Register Description SMRR0 (Standby Mode Release Register 0)
  • Page 126 MC96FR116C SRLC1 (Standby Release Level Control Register 1) SRLC17 SRLC16 SRLC15 SRLC14 SRLC13 SRLC12 SRLC11 SRLC10 Initial value : 00 SRLC1[7:0] Selects the trigger level of key input & interrupt when Port 1 is used as key input source. Triggered by a low level Triggered by a high level KITSR (Key Interrupt Trigger Select Register) KITSR...

  • Page 127: Uart

    MC96FR116C 11.9 UART 11.9.1 Overview The universal asynchronous serial receiver and transmitter (UART) is a highly flexible serial communication device. The main features are listed below. - Full Duplex Operation (Independent Serial Receive and Transmit Registers) - Baud Rate Generator - Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits - Odd or Even Parity Generation and Parity Check Supported by Hardware - Data Overrun Detection...

  • Page 128: Figure 11-36 The Block Diagram Of Uart

    MC96FR116C 11.9.2 Block Diagram To in terr upt block UBAUD WAKEIE RXCIE SCLK Baud Rate Generator At S top mode WAKE Low level detecto r Clock Control Recove ry Data Receive S hift Re gister Recove ry (RXSR) LOOPS DOR/PE/FE UDATA[0] Checke r (Rx)

  • Page 129: Figure 11-38 The Block Diagram Of Clock Generation

    MC96FR116C 11.9.3 Clock Generation UBAUD SCLK (UBAUD+1) Baud Rate Generator SCLK txclk rxclk Figure 11-38 The Block Diagram of Clock Generation The Clock generation logic generates the base clock for the Transmitter and Receiver. Table below contains equations for calculating the baud rate (in bps). Operating Mode Equation for Calculating Baud Rate Normal Mode (U2X=0)

  • Page 130: Figure 11-39 Frame Format

    MC96FR116C 11.9.4 Data format A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. The UART supports all 30 combinations of the following as valid frame formats. - 1 start bit - 5, 6, 7, 8 or 9 data bits - no, even or odd parity bit...
  • Page 131 MC96FR116C : Parity bit using even parity even : Parity bit using odd parity : Data bit n of the character 11.9.6 UART Transmitter The UART Transmitter is enabled by setting the TXE bit in UCTRL1 register. When the Transmitter is enabled, the normal port operation of the TXD pin is overridden by the serial output pin of UART.
  • Page 132 MC96FR116C 11.9.6.4 Disabling Transmitter Disabling the Transmitter by clearing the TXE bit will not become effective until ongoing transmission is completed. When the Transmitter is disabled, the TXD pin is used as normal General Purpose I/O (GPIO) or primary function pin. 11.9.7 UART Receiver The UART Receiver is enabled by setting the RXE bit in the UCTRL1 register.

  • Page 133: Figure 11-40 Start Bit Sampling

    MC96FR116C The Data Overrun (DOR) flag indicates data loss due to a receive buffer full condition. A DOR occurs when the receive buffer is full, and another new data is present in the receive shift register which are to be stored into the receive buffer. After the DOR flag is set, all the incoming data are lost. To prevent data loss or clear this flag, read the receive buffer.

  • Page 134: Figure 11-41 The Sampling Of Data And Parity Bit

    MC96FR116C mode to decide if a valid start bit is received. If more than 2 samples have logical low level, it is considered that a valid start bit is detected and the internally generated clock is synchronized to the incoming data frame. And the data recovery can begin. The synchronization process is repeated for each start bit.
  • Page 135 MC96FR116C UCTRL03 UART0 Control 3 Register USTAT0 UART0 Status Register UBAUD0 UART0 Baud Rate Generation Register UDATA0 UART0 Data Register Table 11-17 Register map of UART 11.9.9 Register Description UCTRL01 (UART0 Control 1 Register) UPM1 UPM0 USIZE2 USIZE1 USIZE0 Initial value : 00 UPM[1:0] Selects Parity Generation and Check methods UPM1...
  • Page 136 MC96FR116C Interrupt from Wake is inhibited When WAKE is set, request an interrupt Enables the transmitter unit. Transmitter is disabled Transmitter is enabled Enables the receiver unit. Receiver is disabled Receiver is enabled UARTEN Activate UART module by supplying clock. UART is disabled (clock is halted) UART is enabled This bit only has effect for the asynchronous operation and selects...
  • Page 137 MC96FR116C This flag is set when the entire frame in the transmit shift register has been shifted out and there is no new data currently present in the transmit buffer. This flag is automatically cleared when the interrupt service routine of a TXC interrupt is executed. It is also cleared by writing ‘0’...
  • Page 138 MC96FR116C Initial value : FF UDATA [7:0] The UART Transmit Buffer and Receive Buffer share the same I/O address with this DATA register. The Transmit Data Buffer is the destination for data written to the UDATA register. Reading the UDATA register returns the contents of the Receive Buffer. Write this register only when the UDRE flag is set.
  • Page 139 MC96FR116C 11.9.10 Baud Rate Setting (example) fOSC=1.00MHz fOSC=1.8432MHz fOSC=2.00MHz Baud U2X=0 U2X=1 U2X=0 U2X=1 U2X=0 U2X=1 Rate UBAU ERRO UBAU ERRO UBAU ERRO UBAU ERRO UBAU ERRO UBAU ERRO 2400 0.2% 0.2% 0.0% 0.0% 0.2% 0.2% 4800 0.2% 0.2% 0.0% 0.0% 0.2% 0.2%...
  • Page 140 MC96FR116C 76.8K -7.0% 0.2% 0.0% 0.0% 0.0% 0.0% 115.2 8.5% -3.5% 0.0% 0.0% 0.0% 0.0% 230.4 8.5% 8.5% 0.0% 0.0% 0.0% 0.0% 250K 0.0% 0.0% -7.8% -7.8% -7.8% 5.3% 0.5M 0.0% -7.8% -7.8% -7.8% -7.8% November, 2018 Rev.1.8...

  • Page 141: I 2 C

    MC96FR116C 11.10 I 11.10.1 Overview The I C is one of industrial standard serial communication protocols, and which uses 2 bus lines Serial Data Line (SDA) and Serial Clock Line (SCL) to exchange data. Because both SDA and SCL lines are open-drain output, each line needs pull-up resistor. The features are as shown below. Compatible with I C bus standard Multi-master operation...

  • Page 142: Figure 11-44 Bit Transfer On The I C-Bus

    MC96FR116C 11.10.3 I C Bit Transfer The data on the SDA line must be stable during HIGH period of the clock, SCL. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. The exceptions are START(S), repeated START(Sr) and STOP(P) condition where data line changes when clock line is high.

  • Page 143: Figure 11-46 Stop Or Repeated Start Condition

    MC96FR116C the most significant bit (MSB) first. If a slave can’t receive or transmit another complete byte of data until it has performed some other function, it can hold the clock line SCL LOW to force the master into a wait state. Data transfer then continues when the slave is ready for another byte of data and releases clock line SCL.

  • Page 144: Figure 11-48 Clock Synchronization During Arbitration Procedure

    MC96FR116C 11.10.7 Synchronization / Arbitration Clock synchronization is performed using the wired-AND connection of I C interfaces to the SCL line. This means that a HIGH to LOW transition on the SCL line will cause the devices concerned to start counting off their LOW period and it will hold the SCL line in that state until the clock HIGH state is reached.
  • Page 145 MC96FR116C 11.10.8 Operation The I C is byte-oriented and interrupt based. Interrupts are issued after all bus events except for a transmission of a START condition. Because the I C is interrupt based, the application software is free to carry on other operations during a I C byte transfer.
  • Page 146 MC96FR116C 3), move to step 6 after transmitting the data in I2CDR and if transfer direction bit is ‘1’ go to master receiver section. 7. 1-Byte of data is being transmitted. During data transfer, bus arbitration continues. 8. This is ACK signal processing stage for data packet transmitted by master. I C holds the SCL LOW.

  • Page 147: Figure 11-50 Formats And States In The Master Transmitter Mode

    MC96FR116C The next figure depicts above process for master transmitter operation of I Master SLA+R S or Sr Receiver SLA+W 0x86 0x22 STOP 0x0E 0x87 LOST DATA STOP LOST LOST& Slave Receiver (0x1D) 0x0F 0x1D 0x1F or Transmitter (0x1F) 0x46 0x22 STOP 0x0E...
  • Page 148 MC96FR116C 11.10.8.2 Master Receiver To operate I C in master receiver, follow the recommended steps below. 1. Enable I C by setting IICEN bit in I2CMR. This provides main clock to the peripheral. 2. Load SLA+R into the I2CDR where SLA is address of slave device and R is transfer direction from the viewpoint of the master.

  • Page 149: Figure 11-51 Formats And States In The Master Receiver Mode

    MC96FR116C load SLA+R/W into the I2CDR and set the START bit in I2CMR. After doing one of the actions above, write arbitrary value to I2CSR to release SCL line. In case of 1) and 2), move to step 7. In case of 3), move to step 9 to handle STOP interrupt. In case of 4), move to step 6 after transmitting the data in I2CDR, and if transfer direction bit is ‘0’...
  • Page 150 MC96FR116C 11.10.8.3 Slave Transmitter To operate I C in slave transmitter, follow the recommended steps below. 1. If the main operating clock (SCLK) of the system is slower than that of SCL, load value 0x00 into I2CSDAHR to make SDA change within one system clock period from the falling edge of SCL.

  • Page 151: Figure 11-52 Formats And States In The Slave Transmitter Mode

    MC96FR116C The next figure shows flow chart for handling slave transmitter function of I IDLE S or Sr SLA+R GCALL 0x97 0x1F LOST& 0x17 DATA 0x22 STOP 0x47 0x46 IDLE From master to slave / Interrupt, SCL line is held low Master command or Data Write From slave to master Interrupt after stop command...
  • Page 152 MC96FR116C 11.10.8.4 Slave Receiver To operate I C in slave receiver, follow the recommended steps below. 1. If the main operating clock (SCLK) of the system is slower than that of SCL, load value 0x00 into I2CSDAHR to make SDA change within one system clock period from the falling edge of SCL.

  • Page 153: Figure 11-53 Formats And States In The Slave Receiver Mode

    MC96FR116C IDLE S or Sr SLA+W GCALL 0x95 0x1D LOST& 0x15 DATA 0x20 STOP 0x44 0x45 IDLE From master to slave / Interrupt, SCL line is held low Master command or Data Write From slave to master Interrupt after stop command Arbitration lost as master and 0xxx LOST&...
  • Page 154 MC96FR116C 11.10.10 I C Register description C Registers are composed of I C Mode Control Register (I2CMR), I C Status Register (I2CSR), SCL Low Period Register (I2CSCLLR), SCL High Period Register (I2CSCLHR), SDA Hold Time Register (I2CSDAHR), I C Data Register (I2CDR), and I C Slave Address Register (I2CSAR).
  • Page 155 MC96FR116C I2CSR (I C Status Register) GCALL TEND STOP SSEL MLOST BUSY TMODE RXACK Initial value : 00 GCALL This bit has different meaning depending on whether I C is master or slave. Note 1) When I C is a master, this bit represents whether it received AACK (Address ACK) from slave.
  • Page 156 MC96FR116C I2CSCLLR (SCL Low Period Register) SCLL7 SCLL6 SCLL5 SCLL4 SCLL3 SCLL2 SCLL1 SCLL0 Initial value : 3F SCLL[7:0] This register defines the LOW period of SCL when I C operates in master mode. The base clock is SCLK, the system clock, and the ×...
  • Page 157 MC96FR116C I2CSAR (I C Slave Address Register) SLA07 SLA06 SLA05 SLA04 SLA03 SLA02 SLA01 SLA00 Initial value : 00 SLA0[7:1] These bits configure the slave address of this I C module when I operates in slave mode. GCALLEN This bit decides whether I C allows general call address or not when I C operates in slave mode.

  • Page 158: Power Management

    MC96FR116C 12. POWER MANAGEMENT 12.1 Overview MC96FR116C supports two kinds of power saving modes, SLEEP and STOP. In these modes, the program execution is stopped. There’s also BOD mode caused by voltage drop, which is almost the same as STOP mode. 12.2 PERIPHERAL OPERATION IN SLEEP/STOP/BOD MODE Peripheral SLEEP Mode...

  • Page 159: Stop Mode

    MC96FR116C CPU Clock External Interrupt Release Normal Operation SLEEP Mode Normal Operation Figure 12-1 Wake-up from SLEEP mode by an interrupt CPU Clock RESETB Release Set PCON to 01 BIT Counter 64 T Clear & Start TST = 32ms @ 4Mhz Normal Operation SLEEP Mode Normal Operation...

  • Page 160: Figure 12-3 Wake-Up From Stop Mode By An Interrupt

    MC96FR116C NOTE The oscillation stability time is up to the characteristic of an oscillator or a resonator connected to the device. So the 20ms of recommended stability time is not absolute. CPU Clock Release External Interrupt STOP Command BIT Counter Clear &...

  • Page 161: Bod Mode

    MC96FR116C unless the power level is recovered. Thereafter the device wakes up by another interrupt when the power level detected by BOD is sufficient. In this case, BOD reset is generated to initialize the device. To wake up by an interrupt and accept interrupt request, the EA bit in IE register and the individual interrupt enable bit INTnE in IEx registers should be set.

  • Page 162: Figure 12-5 Bod Mode During Normal Mode

    MC96FR116C Figure 12-5 BOD mode during normal mode November, 2018 Rev.1.8...

  • Page 163: Figure 12-6 Bod Mode During Stop Mode

    MC96FR116C Figure 12-6 BOD mode during stop mode November, 2018 Rev.1.8...

  • Page 164: Register Map

    MC96FR116C 12.6 Register Map Name Address Default Description PCON Power Control Register Table 12-2 Register Map of Power Control Logic 12.7 Register Description PCON (Power Control Register) BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Initial value : 00 SLEEP mode Enters SLEEP mode STOP mode Enters STOP mode...

  • Page 165: Reset

    MC96FR116C 13. RESET 13.1 Overview When a reset event occurs, the CPU immediately stops whatever it is doing and all internal logics except for BODR register is initialized. The external reset pin(P15) shares normal I/O pin and the functionality is defined by fuse configuration(FUSE_CONF register). The hardware configuration right after reset event is as follows.

  • Page 166: Noise Canceller For External Reset Pin

    MC96FR116C NOTE Unlike other reset sources, BOD reset does not take place as soon as BODR goes HIGH(=voltage drops below BOD stop level). On detecting low voltage while the device is in normal run mode, the device enters BOD(STOP) mode first. And then by detecting voltage rise, the power control logic wakes the device up to give a reset signal.

  • Page 167: Figure 13-4 Reset Release Timing When Power Is Supplied (Vdd Rises Slowly)

    MC96FR116C Slow VDD Rise Time, max 0.02v/ms =1.4V (Typ) nPOR BIT Overflows (Internal Signal) BIT Starts Internal RESETb Oscillation Figure 13-4 Reset Release Timing when Power is supplied (VDD Rises Slowly) Counting for config read start after POR is released Internal nPOR PAD RESETB (P15) “H”...

  • Page 168: External Resetb Input

    MC96FR116C :VDD Input : RC-OSC ⑥ ④ Reset Release Config Read ② BODR ⑦ ⑤ ① ③ Figure 13-6 Operation according to Power Level The above figure shows internal operation according to the voltage level and time. And the following table is short description about the figure.

  • Page 169: Brown Out Detector

    MC96FR116C When the external reset input goes high, the internal reset is released after 32ms of stability time. For 5 clock periods from the point internal reset is released, an initialization procedure is performed. Thereafter the user program is executed from the address 0000 INT RC OSC RESETB Release...

  • Page 170: Figure 13-8 Block Diagram Of Bod

    MC96FR116C External VDD Brown Out Detector BODLS[1:0] STOP_OSCB BODEN BODR STOP MODE DEBOUNCE VDD Rise CP r VDC Lock RESET_BODB BODRF D s Q Write (BOD Reset Flag) STOP_OSCB : Indicates STOP mode (active low signal) SCLK CP r (System CLK) VDC Lock : VDC Lock detect signal indicating that VDC is stable after BOD(STOP) mode exit.

  • Page 171: Register Map

    MC96FR116C “H” “H” Internal nPOR “H” PAD RESETB (R15) BOD_RESETB .. F1 F2 BIT (for Config) 00 01 02 BIT (for Reset) 01 02 FE FF 00 01 02 03 250us X F2 = about 30ms Config Read 250us X FF = about 32ms RESET_SYSB INT RC OSC (4MHz)
  • Page 172 MC96FR116C No external reset detected after clear External reset occurred NOTE WDTRF Watchdog reset event No WDT reset detected after clear WDT reset occurred NOTE OCDRF On-chip debugger reset event No OCD reset detected after clear OCD reset occurred NOTE BODRF Brown-out detector reset event No BOD reset detected after clear...
  • Page 173 MC96FR116C BODI3 VDD level indicator 3. After calibration, this flag turns on around 2.2V only when BODLS[2:0] = 010 VDD level is higher than V BODI3 VDD dropped below V BODI3 BODI2 VDD level indicator 2. After calibration, this flag turns on around 2.0V only when BODLS[2:0] = 001 VDD level is higher than V BODI2...

  • Page 174: On-Chip Debug System

    MC96FR116C 14. On-chip Debug System 14.1 Overview 14.1.1 Description The On-chip debug system(OCD) of MC96FR116C is used to program/erase the non-volatile memory or debug the device. The main features are shown as follows. 14.1.2 Features • Two-wire external interface : 1-wire serial clock input, 1-wire bi-directional serial data bus •...

  • Page 175: Two-Pin External Interface

    MC96FR116C Target MCU internal circuit Format converter DSCL Control DSDA DBG Register Address bus Internal data bus User I/O Data memory Code memory Peripherals - EEPROM - FLASH - SRAM Figure 14-1 Block Diagram of On-Chip Debug System 14.2 Two-pin external interface 14.2.1 Basic transmission packet ...

  • Page 176: Figure 14-2 10-Bit Transmission Packets

    MC96FR116C Figure 14-2 10-bit transmission packets 14.2.2 Packet transmission timing 14.2.2.1 Data transfer Figure 14-3 Data transfer on the twin bus November, 2018 Rev.1.8...

  • Page 177: Figure 14-4 Bit Transfer On The Serial Bus

    MC96FR116C 14.2.2.2 Bit transfer DSDA DSCL data line change stable: of data data valid allowed except Start and Stop Figure 14-4 Bit transfer on the serial bus 14.2.2.3 Start and stop condition DSDA DSDA DSCL DSCL START condition STOP condition Figure 14-5 Start and stop condition 14.2.2.4 Acknowledge bit Data output...

  • Page 178: Figure 14-7 Clock Synchronization During Wait Procedure

    MC96FR116C Acknowledge bit Acknowledge bit transmission transmission Minimum 500ns wait HIGH start HIGH Host PC DSCL OUT Start wait Target Device DSCL OUT minimum 1 T SCLK for next byte Maximum 5 T SCLK transmission DSCL Internal Operation Figure 14-7 Clock synchronization during wait procedure 14.2.3 Connection of transmission Two-pin interface connection uses open-drain (wired-AND bidirectional I/O).

  • Page 179: Flash Memory Controller

    MC96FR116C 15. FLASH Memory Controller 15.1 Overview 15.1.1 Description The MC96FR116C has 16KB of embedded FLASH memory. On reset, this non-volatile memory is used as code memory. In user application program, parts of this non-volatile memory can be updated. Program and erase is performed by ISP via OCD or parallel ROM writer in byte size. 15.1.2 Features of FLASH •...

  • Page 180: Register Map

    MC96FR116C Boot Area Size 3FFF BSIZE[1:0] = 00  512B (0000 ~ 01FF = 01 1024B (0000 ~ 03FF = 10 2048B (0000 ~ 07FF = 11 4096B (0000 ~ 0FFF 12KB Bank0 (16Kbytes) 0FFF 07FF 03FF 512B 01FF 0FFF Boot Code Area 256B 00FF...

  • Page 181: Register Description

    MC96FR116C 15.4 Register Description 15.4.1 FLASH Control Registers Description FMR (FLASH Mode Register) PBUFF FSEL ESEL OTPE READ nFERST Initial value : 01 FLASH Bulk Erase Enable. FLASH Bulk Erase Disabled FLASH Bulk Erase Enabled PBUFF Select Flash Page Buffer. Main cell selected.
  • Page 182 MC96FR116C FADDR15 FADDR14 FADDR13 FADDR12 FADDR11 FADDR10 FADDR9 FADDR8 Initial value : 00 FADDR[15:8] Flash Address Middle (Write) Checksum result in auto verify mode (Read, PCRCRD=0) CRC result in auto verify mode (Read, PCRCRD=1) FARL (FLASH Address Register Low) FADDR7 FADDR6 FADDR5 FADDR4...
  • Page 183 MC96FR116C going, active low. This bit is auto-set when operation is done. Busy (Operation processing) Operation completed VFYGOOD Auto-verification result flag Auto-verification failed Auto-verification succeeded PCRCRD CRC calculation data read control. For correct operation, clear the FARH, FARM and FARL before starting CRC or setting READ bit in FEMR.
  • Page 184 MC96FR116C The CSUMH, CSUMM and CSUML registers are test purpose only. CSUMH (FLASH Read Check Sum Register High) 2F06 CSUM23 CSUM22 CSUM21 CSUM20 CSUM19 CSUM18 CSUM17 CSUM16 Initial value : 00 CSUM[23:16] FLASH Read Checksum in auto-verify mode CSUMM (FLASH Read Check Sum Register Middle) 2F07 CSUM15 CSUM14...
  • Page 185 MC96FR116C FSLTA1 (FLASH Secure Lock Top Address 1 Register) 2F64 FSLTA15 FSLTA14 FSLTA13 FSLTA12 FSLTA11 FSLTA10 FSLTA9 FSLTA8 Initial value : 00 FSLTA[15:8] Flash Secure Lock Top Address FSLTA1 (FLASH Secure Lock Top Address 0 Register) 2F65 FSLTA7 FSLTA6 FSLTA5 FSLTA4 FSLTA3 FSLTA2...
  • Page 186 MC96FR116C FSUTA[7:0] Flash Secure Unlock Top Address FSCTRL (FLASH Secure Control Register) 2F6C UCTRL LCTRL Initial value : 00 UCTRL FLASH unlock control FLASH unlock control is disabled FLASH unlock control is enabled LCTRL FLASH lock control FLASH lock control is disabled FLASH lock control is disabled FSLBAx, FSLTAx, FSUBAx, FSUTAx and FSCTRL registers are used for code write protection.

  • Page 187: Memory Map

    MC96FR116C 15.5 Memory map As described previously, MC96FR116C has 16KB of Program Memory called FLASH. It is needed to write page address into FARH, FARM and FARL registers to program or erase the non-volatile memory. 15.5.1 FLASH area division 03FFF pgm/ers/vfy MC96FR116C Code Memory...

  • Page 188: Serial In-System Program Mode

    MC96FR116C 15.6 Serial In-System Program Mode Serial In-System Program is performed via the interface of debugger which uses two wires. For more information about debugger, refer to chapter 14. 15.6.1 ISP or Self Programming Sequence In MC96FR116C, the commands needed to update FLASH is commenced by FECR register only. PROGRAM or ERASE sequence is as follows : NOTE1 1.
  • Page 189 MC96FR116C Mode Exit 9) Mode Exit 9) Mode Exit 9) Mode Exit Table 15-2 Program or Erase sequence in ISP or Self Program Mode 15.6.1.1 FLASH Read Step 1. Enter OCD(=ISP) mode. Step 2. Set ENBDM bit of BCR. Step 3. Enable debug and Request debug mode. Step 4.
  • Page 190 MC96FR116C // PGM or ERASE Timing, normally the same values are set. #define PGMTIME 0x4F // 2.5ms @4MHz #define ERSTIME 0x4F // 2.5ms @4MHz void page_buffer_reset(); void flash_page_write(unsigned int addr, unsigned char *wdata); void flash_page_erase(unsigned int addr); void flash_program_enter(); void flash_program_exit(); xdata unsigned char pagerom[FLASH_PBUFF_SIZE] _at_ 0x8000;...
  • Page 191 MC96FR116C for (i=0; I < FLASH_PBUFF_SIZE; i++) { pagerom[i] = 0x00; // Step 5 FARL = (unsigned char) addr; FARM = (unsigned char) (addr>>8); // Step 8 FCR = 0x0B; // Step 9 : It is optional because the CPU clock halts while in program or erase operation. while(FESR>>7 == 0x00);...

  • Page 192: Security

    MC96FR116C void flash_program_exit() FCR = 0x31; 15.6.3 Summary of FLASH Program/Erase Mode Flash Operation Description FLASH read Read cell by byte. FLASH write Write cell by bytes or page. FLASH page erase Erase cell by page. FLASH bulk erase Erase the whole cells. FLASH program verify Read cell in verify mode after programming.

  • Page 193: Fuse

    MC96FR116C 16. FUSE 16.1 FUSE Control Register FUSE_CONF (Pseudo-Configure Data) 2FF0 BSIZE1 BSIZE0 RSTDIS LOCKB LOCKF Initial value : 00 BSIZE[1:0] Select Specific Area for Write Protection (Boot Area) Note) When LOCKB=’1’, it is applied. 512B (0000h~01FFh) 1024B (0000h~03FFh) 2048B (0000h~07FFh) 4096B (0000h~0FFFh) RSTDIS Select external reset function...

  • Page 194: Appendix

    MC96FR116C 17. APPENDIX A. Instruction Table The instruction length of M8051W can be 1, 2, or 3 bytes as listed in the following table. It takes 1, 2, or 4 cycles for the CPU to execute an instruction. The cycle is composed of two internal clock periods. ARITHMETIC Mnemonic Description...
  • Page 195 MC96FR116C XRL A, @Ri Exclusive-OR indirect memory to A 66-67 XRL A,#data Exclusive-OR immediate to A XRL dir,A Exclusive-OR A to direct byte XRL dir,#data Exclusive-OR immediate to direct byte CLR A Clear A CPL A Complement A SWAP A Swap Nibbles of A RL A Rotate A left...
  • Page 196 MC96FR116C ANL C,bit AND direct bit to carry ANL C,/bit AND direct bit inverse to carry ORL C,bit OR direct bit to carry ORL C,/bit OR direct bit inverse to carry MOV C,bit Move direct bit to carry MOV bit,C Move carry to direct bit BRANCHING Mnemonic...

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