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Abov A96G140 User Manual

16 mhz 8-bit microcontroller 64/32 kbyte flash memory, 12-bit adc, 6 timers, usart, usi, high current port
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16 MHz 8-bit A96G140/A96G148/A96A148 Microcontroller
64/32 Kbyte Flash memory, 12-bit ADC, 6 Timers, USART,

Introduction

This user's manual targets application developers who use A96G140/A96G148/A96A148 for their
specific needs. It provides complete information of how to use A96G140/A96G148/A96A148 device.
Standard functions and blocks including corresponding register information of A96G140/ A96G148/
A96A148 are introduced in each chapter, while instruction set is in Appendix.
A96G140/A96G148/A96A148 is based on M8051 core and provides standard features of 8051 such as
8-bit ALU, PC, 8-bit registers, timers and counters, serial data communication, PSW, DPTR, SP, 8-bit
data bus and 2x16-bit address bus, and 8/11/16-bit operations.
In addition, this device incorporates followings to offer highly flexible and cost-effective solutions:
64Kbytes of FLASH, 256bytes of IRAM, 2304bytes of XRAM, general purpose I/O, basic interval timer,
watchdog timer, 8/16-bit timer/counter, 16-bit PPG output, 8-bit PWM output, 16-bit PWM output, watch
timer, buzzer driving port, USI, 12-bit A/D converter, on-chip POR, LVR, LVI, on-chip oscillator and
clock circuitry.
As a field proven best seller, A96G140/A96G148/A96A148 has been sold more than 3 billion units up
to now, and introduces rich features such as excellent noise immunity, code optimization, cost
effectiveness, and so on.

Reference document

A96G140/A96G148/A96A148 programming tools and manuals released by ABOV: They are
available at ABOV website, www.abovsemi.com.
SDK-51 User's guide (System Design Kit) released by Intel in 1982: It contains all of
components of a single-board computer based on Intel's 8051 single-chip microcomputer
Information on Mentor Graphics 8051 microcontroller: The technical document is provided at
Mentor website:
A96G140/A96G148/A96A148
https://www.mentor.com/products/ip/peripheral/microcontroller/
Global Top Smart MCU Innovator
www.abovsemi.com
User's Manual
USI, High Current Port
Version 1.30

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Summary of Contents for Abov A96G140

  • Page 1: Introduction

    USI, 12-bit A/D converter, on-chip POR, LVR, LVI, on-chip oscillator and clock circuitry. As a field proven best seller, A96G140/A96G148/A96A148 has been sold more than 3 billion units up to now, and introduces rich features such as excellent noise immunity, code optimization, cost effectiveness, and so on.

  • Page 2: Table Of Contents

    Contents Introduction.............................. 1 Reference document ..........................1 Description ........................... 13 Device overview ........................ 13 A96G140/A96G148/A96A148 block diagram ..............16 Pinouts and pin description ......................17 Pinouts ..........................17 Pin description ........................22 Port structures ..........................27 Central Processing Unit (CPU) ....................29 Architecture and registers ....................
  • Page 3 A96G140/A96G148/A96A148 User’s manual Contents Interrupt controller ........................64 External interrupt ....................... 65 Block diagram ........................66 Interrupt vector table ......................68 Interrupt sequence ......................69 Effective timing after controlling interrupt bit ..............70 Multi-interrupt ........................71 Interrupt enable accept timing ................... 72 Interrupt service routine address ..................
  • Page 4 Contents A96G140/A96G148/A96A148 User’s manual 12.3 Timer 2 ..........................111 12.3.1 16-bit timer/counter mode................... 112 12.3.2 16-bit capture mode .................... 114 12.3.3 16-bit PPG mode ....................116 12.3.4 16-bit timer 2 block diagram ................118 12.3.5 Register map ...................... 118 12.3.6 Register description .................... 118 12.4...
  • Page 5 A96G140/A96G148/A96A148 User’s manual Contents 15.8.4 USIn UART disabling transmitter ............... 164 15.9 USIn UART receiver ......................164 15.9.1 USIn UART receiver RX data ................164 15.9.2 USIn UART receiver flag and interrupt ............... 165 15.9.3 USIn UART parity checker ................. 165 15.9.4 USIn UART disabling receiver ................
  • Page 6 Contents A96G140/A96G148/A96A148 User’s manual Power down operation ....................... 217 17.1 Peripheral operation in IDLE/ STOP mode ..............217 17.2 IDLE mode ........................218 17.3 STOP mode ........................218 17.4 Released operation of STOP mode ................219 17.5 Register map ........................220 17.6...
  • Page 7 A96G140/A96G148/A96A148 User’s manual List of figures List of figures Table 1. A96G140/A96G148/A96A148 Device Features and Peripheral Counts (continued) ....15 Figure 1. A96G140/A96G148/A96A148 Block Diagram ............... 16 Figure 2. A96G140/A96G148 48LQFP/48QFN Pin Assignment ............17 Figure 3. A96G140/A96G148 44MQFP-1010 Pin Assignment ............. 18 Figure 4.
  • Page 8 List of figures A96G140/A96G148/A96A148 User’s manual Figure 48. 16-bit Capture Mode of Timer 2 ..................114 Figure 49. 16-bit Capture Mode Operation Example ................115 Figure 50. Express Timer Overflow in Capture Mode ................. 115 Figure 51. 16-bit PPG Mode of Timer 2 ....................116 Figure 52.
  • Page 9 A96G140/A96G148/A96A148 User’s manual List of figures Figure 98. Clock Synchronization during Arbitration Procedure (USIn) ..........174 Figure 99. Arbitration Procedure of Two Masters (USIn) ..............174 Figure 100. USIn I2C Block Diagram ....................181 Figure 101. USART2 Block Diagram ....................194 Figure 102.
  • Page 10 List of figures A96G140/A96G148/A96A148 User’s manual...
  • Page 11 List of tables List of tables Table 1. A96G140/A96G148/A96A148 Device Features and Peripheral Counts ......... 13 Table 1. A96G140/A96G148/A96A148 Device Features and Peripheral Counts (continued) ....14 Table 3. Normal Pin Description ......................22 Table 4. SFR Map Summary ......................... 38 Table 5.
  • Page 12 List of tables A96G140/A96G148/A96A148 User’s manual Table 49. Security Policy using Lock Bits .................... 247 Table 50. Information of Core and Debug Emulation Interfaces ............251 Table 51. Cores and Debug Interfaces by Series ................251 Table 52. Feature Comparison Chart By Series and Core ..............252 Table 53.

  • Page 13: Description

    A96G140/A96G148/A96A148 User’s manual 1. Description Description A96G140/A96G148/A96A148 is an advanced CMOS 8-bit microcontroller with 64/32Kbytes of FLASH. This is a powerful microcontroller which provides a highly flexible and cost-effective solution to many embedded control applications. Device overview In this section, features of A96G140/A96G148/A96A148 and peripheral counts are introduced.

  • Page 14: Table 1. A96G140/A96G148/A96A148 Device Features And Peripheral Counts (Continued)

    1. Description A96G140/A96G148/A96A148 User’s manual Table 1. A96G140/A96G148/A96A148 Device Features and Peripheral Counts (continued) Peripherals Description Reset Power Reset release level: 1.2V on reset Low voltage 16 levels detect  reset 1.61/1.68/1.77/1.88/2.00/2.13/2.28/2.46/2.68/2.81/3.06/  3.21/3.56/3.73/3.91/4.25V Low voltage indicator 13 levels detect ...
  • Page 15 A96G140/A96G148/A96A148 User’s manual 1. Description Table 1. A96G140/A96G148/A96A148 Device Features and Peripheral Counts (continued) Peripherals Description Pb-free packages  48 LQFP 7x7 mm, 48 QFN 6x6 mm  Package 44 MQFP 10x10 mm  32 LQFP, 32 SOP  28 SOP, 28 TSSOP...

  • Page 16: A96G140/A96G148/A96A148 Block Diagram

    1. Description A96G140/A96G148/A96A148 User’s manual A96G140/A96G148/A96A148 block diagram In this section, A96G140/A96G148/A96A148 device with peripherals are described in a block diagram. Flash 64/32KB CORE XRAM M8051 2304B IRAM 256B General purpose I/O In-system programming 46 ports normal I/O Power control...

  • Page 17: Pinouts And Pin Description

    A96G140/A96G148/A96A148 User’s manual 2. Pinouts and pin description Pinouts and pin description In this chapter, A96G140/A96G148/A96A148 device pinouts and pin descriptions are introduced. Pinouts A96G140CL A96G148CL (48LQFP-0707) A96G140CU A96G148CU (48QFN-0606) NOTE: Programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA.

  • Page 18: Figure 3. A96G140/A96G148 44Mqfp-1010 Pin Assignment

    The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA. The P44-P47 pins should be selected as a push-pull output or an input with pull-up resistor by software control when the 44-pin package is used. Figure 3. A96G140/A96G148 44MQFP-1010 Pin Assignment...

  • Page 19: Figure 4. A96G140/A96G148 32Lqfp Pin Assignment

    The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA. The P14-P17, P23-P25, P34-P37 and P43-P47 pins should be selected as a push-pull output or an input with pull-up resistor by software control when the 32-pin package is used. Figure 4. A96G140/A96G148 32LQFP Pin Assignment...

  • Page 20: Figure 5. A96G140/A96G148 32Sop Pin Assignment

    The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA. The P14-P17, P23-P25, P34-P37 and P43-P47 pins should be selected as a push-pull output or an input with pull-up resistor by software control when the 32-pin package is used. Figure 5. A96G140/A96G148 32SOP Pin Assignment P50/XO UT P00/EC3/DSDA/(RXD2)

  • Page 21: Figure 7. A96A148 28Sop Pin Assignment

    A96G140/A96G148/A96A148 User’s manual 2. Pinouts and pin description VS S P50/XOUT P00/EC3/DSDA/(RXD2) P51/XIN P01/T3O/PWM3O/DSCL/(TXD2) P52/EINT8/EC0 P02/AN0/AVREF/EINT0/T4O/PWM4O P53/SXIN/T0O/PWM0O P03/AN1/EINT1 P54/SXOUT/EINT10 P04/AN2/EINT2/(T3O)/(PWM3O) A96A148GD P55/RESE TB P05/AN3/EINT3/(EC3) (28-SOP) P37/LED0 P06/AN4/EINT4/T5O/PWM5O P36/LED1 P07/AN5/EINT5 P35/LED2 P12/AN11/EINT11/T1O/PWM1O P34/LED3 P11/AN12/EINT12/T2O/PWM2O P33/LED4 P10/AN13/RXD1/SCL1/MISO1 P32/LED5 P20/AN14/TXD1/SDA1/MOSI1 P31/LED6 P30/LED7 NOTES: The programmer (E-PGM+, E-Gang4/6) uses P0[1:0] pin as DSCL, DSDA.

  • Page 22: Pin Description

    2. Pinouts and pin description A96G140/A96G148/A96A148 User’s manual Pin description Table 2. Normal Pin Description Remark Pin no. Description Name A96A148 LQFP P00* IOUS Port 0 bit 0 Input/output Timer 3(Event Capture) input Pull-up DSDA OCD debugger data input/output RXD2...
  • Page 23 A96G140/A96G148/A96A148 User’s manual 2. Pinouts and pin description Table 2. Normal Pin Description (Continue) Remark Pin no. Description Name A96A148 LQFP P07* IOUS Port 0 bit 7 Input/output ADC input ch-5 EINT5 External interrupt input ch-5 P10* IOUS Port 1 bit 0 Input/output...
  • Page 24 2. Pinouts and pin description A96G140/A96G148/A96A148 User’s manual Table 2. Normal Pin Description (Continue) Remark Pin no. Description Name A96A148 LQFP P16* IOUS Port 1 bit 6 Input/output ADC input ch-7 EINT7 External interrupt input ch-7 USART2 clock signal P17*...
  • Page 25 A96G140/A96G148/A96A148 User’s manual 2. Pinouts and pin description Table 2. Normal Pin Description (Continue) Remark Pin no. Description Name A96A148 LQFP P35* IOUS Port 3 bit 5 Input /output LED2 High sink current ports P36* IOUS Port 3 bit 6 Input/output...
  • Page 26 2. Pinouts and pin description A96G140/A96G148/A96A148 User’s manual Table 2. Normal Pin Description (Continue) Remark Pin no. Description Name A96A148 LQFP P53* IOUS Port 5 bit 3 Input/output SXIN Sub Oscillator Input Timer 0 interval output PWM0O Timer 0 PWM output...

  • Page 27: Port Structures

    A96G140/A96G148/A96A148 User’s manual 3. Port structure Port structures In this chapter, two port structures are introduced in Figure 8 and Figure 9 regarding general purpose I/O port and external interrupt I/O port respectively. Level Shift (1.8V to ExtVDD) Level Shift (ExtVDD to 1.8V)

  • Page 28: Figure 9. External Interrupt I/O Port

    3. Port structure A96G140/A96G148/A96A148 User’s manual LevelShift (1.8V to ExtVDD) LevelShift (ExtVDD to 1.8V) PULL-UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE DIRECTION REGISTER SUB-FUNC DIRECTION R(400Ω) EXTERNAL INTERRUPT POLARITY INTERRUPT ENABLE EDGE FLAG CLEAR PORTx INPUT...

  • Page 29: Central Processing Unit (Cpu)

    A96G140/A96G148/A96A148 User’s manual 4. Central processing unit ABOV Central Processing Unit (CPU) Central Processing Unit (CPU) of A96G140/A96G148/A96A148 is based on Mentor Graphics M8051EW core, which offers improved code efficiency and high performance. Architecture and registers Figure 10 shows a block diagram of the M8051EW architecture. As shown in the figure, the M8051EW supports both Program Memory and External Data Memory.
  • Page 30 4. Central processing unit ABOV A96G140/A96G148/A96A148 User’s manual Debug support (OCD and OCD II):  The M8051EW offers a Debug Mode together with a set of dedicated debug signals which can be used by external debug hardware, OCD and OCD II, to provide start/stop program execution in response to both hardware and software triggers, single step operation and program execution tracing.

  • Page 31: Addressing

    A96G140/A96G148/A96A148 User’s manual 4. Central processing unit ABOV Addressing The M8051EW supports six types of addressing modes as listed below: Direct addressing mode: In this mode, the operand is specified by the 8-bit address field. Only internal data and SFRs can be accessed using this mode.

  • Page 32: Instruction Set

    4. Central processing unit ABOV A96G140/A96G148/A96A148 User’s manual Instruction set An instruction is a single operation of a processor that is defined by the instruction set. The M8051EW uses the instruction set of 8051 that is broadly classified into five functional categories:...
  • Page 33 A96G140/A96G148/A96A148 User’s manual 4. Central processing unit ABOV External data memory: Data can be moved between the accumulator and the external memory  location in one of two addressing modes. In 8-bit addressing mode, the external location is addressed by either R0 or R1; in 16-bit addressing mode, the location is addressed by the DPTR.

  • Page 34: Memory Organization

    Internal data memory (IRAM) is 256bytes and it includes the stack area. External data memory (XRAM) is 2304bytes. Program memory A 16-bit program counter is capable of addressing up to 64Kbytes, and A96G140/A96G148/A96A148 has just 64Kbytes program memory space. Figure 9 shows a map of the lower part of the program memory.

  • Page 35: Data Memory

    A96G140/A96G148/A96A148 User’s manual 5. Memory organization FFFFH 64KB FLASH 7FFFH 32KB FLASH 0000H NOTE: The 64Kbytes includes the Interrupt Vector Region. Figure 11. Program Memory Map Data memory Internal data memory space is divided into three blocks, which are generally referred to as lower 128bytes, upper 128bytes, and SFR space.

  • Page 36: Figure 12. Data Memory Map

    5. Memory organization A96G140/A96G148/A96A148 User’s manual All of the bytes in the lower 128bytes can be accessed by either direct or indirect addressing. The upper 128bytes of RAM can only be accessed by indirect addressing. These spaces are used for data RAM and stack.

  • Page 37: External Data Memory

    Register Bank 0 8bytes (8bytes) Figure 13. Lower 128bytes of RAM External data memory A96G140/A96G148/A96A148 has 2304bytes of XRAM and XSFR. This area has no relation with RAM/FLASH. It can be read and written to through SFR with 8-bit unit.

  • Page 38: Sfr Map

    5. Memory organization A96G140/A96G148/A96A148 User’s manual 107FH Extended Special Function Registers 128bytes (Indirect Addressing) 1000H Not used 08FFH External RAM 2304bytes (Indirect Addressing) 0000H Figure 14. XDATA Memory Area SFR map 5.4.1 SFR map summary Table 3. SFR Map Summary ―...

  • Page 39: Table 5. Xsfr Map Summary

    A96G140/A96G148/A96A148 User’s manual 5. Memory organization Table 3. SFR Map Summary (Continued) ― Reserved M8051 compatible 00H/8H 01H/9H 02H/0AH 03H/0BH 04H/0CH 05H/0DH 06H/0EH 07H/0FH 0B8H P2IO T1CRL T1CRH T1ADRL T1ADRH T1BDRL T1BDRH 0B0H P1IO T0CR T0CNT T0DR/ – – –...

  • Page 40: Sfr Map

    5. Memory organization A96G140/A96G148/A96A148 User’s manual 5.4.2 SFR map Table 5. SFR Map Address Function Symbol @Reset P0 Data Register Stack Pointer Data Pointer Register Low Data Pointer Register High Data Pointer Register Low 1 DPL1 Data Pointer Register High 1...
  • Page 41 A96G140/A96G148/A96A148 User’s manual 5. Memory organization Table 5. SFR Map (continued) Address Function Symbol @Reset P4 Data Register P0 Direction Register P0IO Extended Operation Register – – – – P4 Pull-up Resistor Selection Register P4PU External Interrupt Polarity 0 Low Register...
  • Page 42 5. Memory organization A96G140/A96G148/A96A148 User’s manual Table 5. SFR Map (continued) Address Function Symbol @Reset External Interrupt Flag 0 Register EIFLAG0 P3 Direction Register P3IO Timer 2 Control Low Register T2CRL – – Timer 2 Control High Register T2CRH –...
  • Page 43 A96G140/A96G148/A96A148 User’s manual 5. Memory organization Table 5. SFR Map (continued) Address Function Symbol @Reset Accumulator Register USI0 Status Register 1 USI0ST1 – USI0 Status Register 2 USI0ST2 USI0 Baud Rate Generation Register USI0BD USI0 SDA Hold Time Register USI0SHDR...

  • Page 44: Table 7. Xsfr Map

    5. Memory organization A96G140/A96G148/A96A148 User’s manual Table 6. XSFR Map Address Function Symbol @Reset 1000H Timer 3 Control High Register T3CRH – – – – 1001H Timer 3 Control Low Register T3CRL – – 1002H Timer 3 A Data High Register...

  • Page 45: Compiler Compatible Sfr

    A96G140/A96G148/A96A148 User’s manual 5. Memory organization 5.4.3 Compiler compatible SFR ACC (Accumulator Register): E0H Initial value: 00H Accumulator B (B Register): F0H Initial value: 00H B Register SP (Stack Pointer): 81H Initial value: 07H Stack Pointer DPL (Data Pointer Register Low): 82H...
  • Page 46 5. Memory organization A96G140/A96G148/A96A148 User’s manual DPH1 (Data Pointer Register High 1): 85H DPH1 Initial value: 00H DPH1 Data Pointer High 1 PSW (Program Status Word Register): D0H Initial value: 00H Carry Flag Auxiliary Carry Flag General Purpose User-Definable Flag...

  • Page 47: O Ports

    6. I/O ports I/O ports A96G140/A96G148/A96A148 has ten groups of I/O ports (P0 ~ P5). Each port can be easily configured by software as I/O pin, internal pull up and open-drain pin to meet various system configurations and design requirements. P0 includes a function that can generate interrupt signals according to state of a pin.

  • Page 48: Register Map

    6. I/O ports A96G140/A96G148/A96A148 User’s manual 6.1.7 Register Map Table 7. Port Register Map Name Address Direction Default Description P0 Data Register P0IO P0 Direction Register P0PU P0 Pull-up Resistor Selection Register P0OD P0 Open-drain Selection Register P0DB P0 De-bounce Enable Register...

  • Page 49: P0 Port

    A96G140/A96G148/A96A148 User’s manual 6. I/O ports P0 port 6.2.1 P0 port description P0 is an 8-bit I/O port. P0 control registers consist of P0 data register (P0), P0 direction register (P0IO), debounce enable register (P0DB), P0 pull-up resistor selection register (P0PU), and P0 open-drain selection register (P0OD).
  • Page 50 6. I/O ports A96G140/A96G148/A96A148 User’s manual P0OD (P0 Open-drain Selection Register): 91H P07OD P06OD P05OD P04OD P03OD P02OD P01OD P00OD Initial value: 00H P0OD[7:0] Configure Open-drain of P0 Port Push-pull output Open-drain output P0DB (P0 De-bounce Enable Register): DEH DBCLK1...
  • Page 51 A96G140/A96G148/A96A148 User’s manual 6. I/O ports P0FSRH (Port 0 Function Selection High Register): D3H P0FSRH7 P0FSRH6 P0FSRH5 P0FSRH4 P0FSRH3 P0FSRH2 P0FSRH1 P0FSRH0 Initial value: 00H P0FSRH[7:6] P07 Function Select P0FSRH7 P0FSRH6 Description I/O Port (EINT5 function possible when input) reserved...

  • Page 52: P1 Port

    6. I/O ports A96G140/A96G148/A96A148 User’s manual P0FSRL (Port 0 Function Selection Low Register): D2H P0FSRL7 P0FSRL6 P0FSRL5 P0FSRL4 P0FSRL3 P0FSRL2 P0FSRL1 P0FSRL0 Initial value: 00H P0FSRL[7:6] P03 Function Select P0FSRL7 P0FSRL6 Description I/O Port(EINT1 function possible when input) reserved AN1 Function...
  • Page 53 A96G140/A96G148/A96A148 User’s manual 6. I/O ports P1 (P1 Data Register): 88H Initial value: 00H P1[7:0] I/O Data P1IO (P1 Direction Register): B1H P17IO P16IO P15IO P14IO P13IO P12IO P11IO P10IO Initial value: 00H P1IO[7:0] P1 Data I/O Direction Input Output...
  • Page 54 6. I/O ports A96G140/A96G148/A96A148 User’s manual P15DB (P1/P5 De-bounce Enable Register): DFH – – P54DB P52DB P17DB P16DB P12DB P11DB – – Initial value: 00H P54DB Configure De-bounce of P54 Port Disable Enable P52DB Configure De-bounce of P52 Port Disable...
  • Page 55 A96G140/A96G148/A96A148 User’s manual 6. I/O ports P1FSRH (Port 1 Function Selection High Register): D5H P1FSRH7 P1FSRH6 P1FSRH5 P1FSRH4 P1FSRH3 P1FSRH2 P1FSRH1 P1FSRH0 Initial value: 00H P1FSRH[7:6] P17 Function Select P1FSRH7 P1FSRH6 Description I/O Port(EINT6 function possible when input) reserved AN6 Function...

  • Page 56: P2 Port

    6. I/O ports A96G140/A96G148/A96A148 User’s manual P1FSRL (Port 1 Function Selection Low Register): D4H P1FSRL7 P1FSRL6 P1FSRL5 P1FSRL4 P1FSRL3 P1FSRL2 P1FSRL1 P1FSRL0 Initial value: 00H P1FSRL[7:6] P13 Function Select P1FSRL7 P1FSRL6 Description I/O Port(EC1 function possible when input) reserved AN10 Function...
  • Page 57 A96G140/A96G148/A96A148 User’s manual 6. I/O ports P2 (P2 Data Register): 90H Initial value: 00H P2[7:0] I/O Data P2IO (P2 Direction Register): B9H P27IO P26IO P25IO P24IO P23IO P22IO P21IO P20IO Initial value: 00H P2IO[7:0] P2 Data I/O Direction Input Output...

  • Page 58: P3 Port

    6. I/O ports A96G140/A96G148/A96A148 User’s manual P2FSR (Port 2 Function Selection Register): D6H P2FSR4 P2FSR3 P2FSR2 P2FSR1 P2FSR0 Initial value: 00H P2FSR4 P22 Function Select I/O Port SS1 Function P2FSR[3:2] P21 Function Select P2FSR3 P2FSR2 Description I/O Port reserved AN15 Function...
  • Page 59 A96G140/A96G148/A96A148 User’s manual 6. I/O ports P3IO (P3 Direction Register): C1H P37IO P36IO P35IO P34IO P33IO P32IO P31IO P30IO Initial value: 00H P3IO[7:0] P3 Data I/O Direction Input Output P3PU (P3 Pull-up Resistor Selection Register): AFH P37PU P36PU P35PU P34PU...

  • Page 60: P4 Port

    6. I/O ports A96G140/A96G148/A96A148 User’s manual P3FSR (Port 3 Function Selection Register): EEH P3FSR7 P3FSR6 P3FSR5 P3FSR4 P3FSR3 P3FSR2 P3FSR1 P3FSR0 Initial value: 00H P3FSR7 P37 Function select I/O Port LED0 Function P3FSR6 P36 Function Select I/O Port LED1 Function...
  • Page 61 A96G140/A96G148/A96A148 User’s manual 6. I/O ports P4 (P4 Data Register): A0H Initial value: 00H P4[7:0] I/O Data P4IO (P4 Direction Register): C9H P47IO P46IO P45IO P44IO P43IO P42IO P41IO P40IO Initial value: 00H P4IO[7:0] P4 Data I/O Direction Input Output...

  • Page 62: P5 Port

    6. I/O ports A96G140/A96G148/A96A148 User’s manual P4FSR (Port 4 Function Selection Register): EFH P4FSR3 P4FSR2 P4FSR1 P4FSR0 Initial value: 00H P4FSR3 P43 Function Select I/O Port SS0 Function P4FSR2 P42 Function Select I/O Port SCK0 Function P4FSR1 P41 Function Select...
  • Page 63 A96G140/A96G148/A96A148 User’s manual 6. I/O ports P5PU (P5 Pull-up Resistor Selection Register): 95H – – P55PU P54PU P53PU P52PU P51PU P50PU – – Initial value: 00H P5PU[5:0] Configure Pull-up Resistor of P5 Port Disable Enable P5FSR (Port 5 Function Selection Register): FFH...

  • Page 64: Interrupt Controller

    7. Interrupt controller A96G140/A96G148/A96A148 User’s manual Interrupt controller A96G140/A96G148/A96A148 supports up to 23 interrupt sources. The interrupts have separate enable register bits associated with them, allowing software control. In addition, they have four levels of priority assigned to themselves. A non-maskable interrupt source is always enabled with a higher priority than any other interrupt sources, and is not controllable by software.

  • Page 65: External Interrupt

    A96G140/A96G148/A96A148 User’s manual 7. Interrupt controller Interrupt Highest Lowest Group 0 (Bit0) Interrupt 0 Interrupt 6 Interrupt 12 Interrupt 18 Highest 1 (Bit1) Interrupt 1 Interrupt 7 Interrupt 13 Interrupt 19 2 (Bit2) Interrupt 2 Interrupt 8 Interrupt 14 Interrupt 20...

  • Page 66: Block Diagram

    7. Interrupt controller A96G140/A96G148/A96A148 User’s manual EINT8 Pin FLAG8 INT6 Interrupt EINT10 Pin INT0 Interrupt FLAG10 EINT11 Pin FLAG11 INT1 Interrupt EINT12 Pin FLAG12 INT11 Interrupt EIPOL1 FLAG0 EINT0 Pin FLAG1 EINT1 Pin FLAG2 EINT2 Pin FLAG3 EINT3 Pin INT5 Interrupt...

  • Page 67: Figure 17. Interrupt Controller Block Diagram

    A96G140/A96G148/A96A148 User’s manual 7. Interrupt controller EIPOL1 EI FLAG1.1 EINT10 FLAG10 EI FLAG1.2 EINT11 Priority High FLAG11 USI1 I2C I2C1IFR USI1 Rx USI1 Tx EIPOL0H/L EI FLAG0.0 EINT0 FLAG0 EI FLAG0.1 EINT1 FLAG1 EI FLAG0.2 EINT2 FLAG2 EI FLAG0.3 EINT3 FLAG3 EI FLAG0.4...

  • Page 68: Interrupt Vector Table

    A96G140/A96G148/A96A148 User’s manual Interrupt vector table Interrupt controller of A96G140/A96G148/A96A148 supports 24 interrupt sources as shown in table 8. When interrupt is served, long call instruction (LCALL) is executed and program counter jumps to the vector address. All interrupt requests have their own priority order.

  • Page 69: Interrupt Sequence

    A96G140/A96G148/A96A148 User’s manual 7. Interrupt controller And it remains ‘1’ until CPU accepts interrupt. If the interrupt is served, the interrupt request flag will be cleared automatically. Interrupt sequence An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to ‘0’ by a reset or an instruction.

  • Page 70: Effective Timing After Controlling Interrupt Bit

    7. Interrupt controller A96G140/A96G148/A96A148 User’s manual IE.EA Flag 0 Program Counter low Byte SP  SP + 1 M (SP)  (PCL) Saves PC value in order to continue process again after executing ISR Program Counter high Byte SP  SP + 1 M (SP) ...

  • Page 71: Multi-Interrupt

    A96G140/A96G148/A96A148 User’s manual 7. Interrupt controller Interrupt Enable Register command After executing IE set/clear, enable register is effective. Next Instruction Next Instruction Figure 19. Effective Timing of Interrupt Enable Register Case B in figure 18 shows the effective time after controlling Interrupt Flag Registers.

  • Page 72: Interrupt Enable Accept Timing

    7. Interrupt controller A96G140/A96G148/A96A148 User’s manual Main Program Service INT1 ISR INT0 ISR Set EA Occur Occur INT1 Interrupt INT0 Interrupt RETI RETI Figure 21. Effective Timing of Multi-Interrupt Figure 19 shows an example of multi-interrupt processing. While INT1 is served, INT0 which has higher priority than INT1 is occurred.

  • Page 73: Interrupt Service Routine Address

    A96G140/A96G148/A96A148 User’s manual 7. Interrupt controller System Max. 4 Machine Cycle 4 Machine Cycle Clock Interrupt goes Interrupt Interrupt Processing active latched Interrupt Routine : LCALL & LJMP Figure 22. Interrupt Response Timing Diagram Interrupt service routine address Basic Interval Timer...

  • Page 74: Interrupt Timing

    7. Interrupt controller A96G140/A96G148/A96A148 User’s manual 7.10 Interrupt timing Interrupt sampled here CLP2 CLP1 CLP2 C1P1 C1P2 C2P1 C2P2 SCLK INT_SRC INTR_ACK LAST_CYC INTR_LCALL 8-bit interrupt Vector INT_VEC PROGA NOTE: Variable x and n of a command cycle CLPx imply the followings: ...

  • Page 75: External Interrupt Flag Register (Eiflag0 And Eiflag1)

    A96G140/A96G148/A96A148 User’s manual 7. Interrupt controller After a reset, IP and IP1 are cleared to ‘00H’. If interrupts have the same priority level, lower number interrupt is served first. 7.11.3 External Interrupt Flag Register (EIFLAG0 and EIFLAG1) External Interrupt Flag 0 Register (EIFLAG0) and External Interrupt Flag 1 Register (EIFLAG1) are set to ‘1’...
  • Page 76 7. Interrupt controller A96G140/A96G148/A96A148 User’s manual IE (Interrupt Enable Register): A8H – INT5E INT4E INT3E INT2E INT1E INT0E – Initial value: 00H Enable or Disable All Interrupt bits All Interrupt disable All Interrupt enable INT5E Enable or Disable External Interrupt 0 ~ 7 (EINT0 ~ EINT7)
  • Page 77 A96G140/A96G148/A96A148 User’s manual 7. Interrupt controller IE1 (Interrupt Enable Register 1): A9H – – INT11E INT10E INT9E INT8E INT7E INT6E – – Initial value: 00H INT11E Enable or Disable External Interrupt 12 (EINT12) Disable Enable INT10E Enable or Disable USI0Tx Interrupt...
  • Page 78 7. Interrupt controller A96G140/A96G148/A96A148 User’s manual IE2 (Interrupt Enable Register 2): AAH –- – INT17E INT16E INT15E INT14E INT13E INT12E – – Initial value: 00H INT17E Enable or Disable Timer 4/5 Match Interrupt Disable Enable INT16E Enable or Disable Timer 3 Match Interrupt...
  • Page 79 A96G140/A96G148/A96A148 User’s manual 7. Interrupt controller IE3 (Interrupt Enable Register 3): ABH – – INT23E INT22E INT21E INT20E INT19E INT18E – – Initial value: 00H INT23E Enable or Disable LVI Interrupt Disable Enable INT22E Enable or Disable BIT Interrupt Disable...
  • Page 80 7. Interrupt controller A96G140/A96G148/A96A148 User’s manual EIFLAG0 (External Interrupt Flag0 Register): C0H FLAG7 FLAG6 FLAG5 FLAG4 FLAG3 FLAG2 FLAG1 FLAG0 Initial value: 00H When an External Interrupt 0-7 is occurred, the flag becomes ‘1’.The EIFLAG0[7:0] flag is cleared only by writing ‘0’ to the bit. So, the flag should be cleared by software.
  • Page 81 A96G140/A96G148/A96A148 User’s manual 7. Interrupt controller EIFLAG1 (External Interrupt Flag 1 Register): A6H – – T0OVIFR T0IFR FLAG12 FLAG11 FLAG10 FLAG8 – – Initial value: 00H When T0 overflow interrupt occurs, this bit becomes ‘1’. For clearing T0OVIFR bit, write‘0’ to this bit or automatically clear by INT_ACK signal.

  • Page 82: Clock Generator

    — HSIRC OSC/32 (1MHz) — HSIRC OSC/64 (0.5MHz) Main crystal oscillator (4~12MHz)  Sub-crystal Oscillator (32.768kHz)  Internal LSIRC oscillator (128kHz)  Clock generator block diagram In this section, a clock generator of A96G140/A96G148/A96A148 is described in a block diagram.

  • Page 83: Register Map

    A96G140/A96G148/A96A148 User’s manual 8. Clock generator Main OSC XOUT STOP Mode IRCS[2:0] XCLKE System SCLK Clock Gen. (Core, System, Clock Per ipheral) Chang e HIRC HIRC O SC 1/16 (32MHz) 1/32 Stabilization Time 1/64 Generation BITCK[2:0] STOP Mode overflow HSIRCE...
  • Page 84 8. Clock generator A96G140/A96G148/A96A148 User’s manual OSCCR (Oscillator Control Register): C8H – LSIRCE IRCS2 IRCS1 IRCS0 HSIRCE XCLKE SCLKE – Initial value: 28H LSIRCE Control the Operation of the Low Frequency (128kHz) internal RC Oscillator at Stop mode Disable operation of LSIRC OSC...
  • Page 85 A96G140/A96G148/A96A148 User’s manual 8. Clock generator XTFLSR (Main Crystal OSC Filter Selection Register): 1038H NFSEL1 NFSEL0 MX_FIL_DIS MX_ISEL1 MX_ISEL0 SUB_FIL_DIS SUB_ISEL1 SUB_ISEL0 Initial value: 00H NFSEL[1:0] Noise Filter Selective Option NFSEL1 NFSEL0 Description 18ns (Default, 12MHz) 22ns (12MHz) 26ns (8MHz)

  • Page 86: Basic Interval Timer

    On exiting Stop mode, BIT gives a stable clock generation time  As a timer, BIT generates a timer interrupt.  BIT block diagram In this section, basic interval timer of A96G140/A96G148/A96A148 is described in a block diagram. WDT Source Clock 1/4096 8-bit up-counter 1/1024...

  • Page 87: Bit Register Description

    A96G140/A96G148/A96A148 User’s manual 9. Basic interval timer BIT register description BITCNT (Basic Interval Timer Counter Register): 8CH BITCNT7 BITCNT6 BITCNT5 BITCNT4 BITCNT3 BITCNT2 BITCNT1 BITCNT0 Initial value: 00H BITCNT[7:0] BIT Counter BITCR (Basic Interval Timer Control Register): 8BH BITIFR BITCK2...

  • Page 88: Watchdog Timer

    10. Watchdog timer A96G140/A96G148/A96A148 User’s manual Watchdog timer Watchdog timer (WDT) rapidly detects the CPU malfunction such as endless looping caused by noise or something like that, and resumes the CPU to the normal state. Watchdog timer signal for malfunction detection can be used as either a CPU reset or an interrupt request.

  • Page 89: Wdt Block Diagram

    A96G140/A96G148/A96A148 User’s manual 10. Watchdog timer 10.2 WDT block diagram BIT Overflow Watchdog Timer Counter Register Clear To Reset BIT Overflow/8 WDTCNT Circuit WDTEN WDTCK Clear WDTIFR INT_ACK BIT Overflow comparator BIT Overflow/8 WDTIF WDTDR Watchdog Timer Data Register WDTCL...
  • Page 90 10. Watchdog timer A96G140/A96G148/A96A148 User’s manual WDTDR (Watch Dog Timer Data Register: Write Case): 8EH WDTDR7 WDTDR 6 WDTDR 5 WDTDR 4 WDTDR 3 WDTDR 2 WDTDR 1 WDTDR 0 Initial value: FFH WDTDR[7:0] Set a period WDT Interrupt Interval=(BIT Interrupt Interval) x(WDTDR Value+1) NOTE: Do not write “0”...

  • Page 91: Watch Timer

    7-bit counter in order to increase resolution. In WTDR, it can control WT clear and set interval value at write time, and it can read 7-bit WT counter value at read time. 11.1 WT block diagram In this section, watch timer of A96G140/A96G148/A96A148 is described in a block diagram. S UB Match Clear...

  • Page 92: Watch Timer Register Description

    11. Watch timer A96G140/A96G148/A96A148 User’s manual Table 13. Watch Timer Register Map Name Address Direction Default Description WTCNT Watch Timer Counter Register WTDR Watch Timer Data Register WTCR Watch Timer Control Register 11.3 Watch timer register description WTCNT (Watch Timer Counter Register: Read Case): 89H –...
  • Page 93 A96G140/A96G148/A96A148 User’s manual 11. Watch timer WTCR (Watch Timer Control Register): 96H – – WTEN WTIFR WTIN1 WTIN0 WTCK1 WTCK0 – – Initial value: 00H WTEN Control Watch Timer Disable Enable When WT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write WTIFR ‘0’...

  • Page 94: Timer 0/1/2/3/4/5

    12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual Timer 0/1/2/3/4/5 12.1 Timer 0 An 8-bit timer 0 consists of a multiplexer, a timer 0 counter register, a timer 0 data register, a timer 0 capture data register and a timer 0 control register (T0CNT, T0DR, T0CDR, T0CR).

  • Page 95: Figure 31. 8-Bit Timer/Counter Mode For Timer 0

    A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5 ADDRESS : B2H T0CR T0EN T0MS1 T0MS0 T0CK2 T0CK1 T0CK0 T0CC INITIAL VALUE: 0000_0000B Match signal Clear fx/2 T0CC fx/4 8-bit Timer 0 Counter fx/8 INT_ACK T0CNT(8Bit) fx/32 Clear fx/128 fx/512 Match To interrupt...

  • Page 96: 8-Bit Pwm Mode

    12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual 12.1.2 8-bit PWM mode Timer 0 has a high speed PWM (Pulse Width Modulation) function. In PWM mode, T0O/PWM0O pin outputs up to 8-bit resolution PWM output. This pin should be configured as a PWM output by setting the T0O/PWM0O function by P5FSR[5:4] bits.

  • Page 97: Figure 34. Pwm Output Waveforms In Pwm Mode For Timer 0

    A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5 PWM Mode(T0MS = 01b) Set T0EN Timer 0 clock T0CNT T0DR T0 Overflow Interrupt 1. T0DR = 4AH T0PWM T0 Match Interrupt 2. T0DR = 00H T0PWM T0 Match Interrupt 3. T0DR = FFH...

  • Page 98: 8-Bit Capture Mode

    12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual 12.1.3 8-bit capture mode Timer 0 capture mode is set by configuring T0MS[1:0] as ‘1x’. Clock source can use the internal/external clock. Basically, it has the same function as the 8-bit timer/counter mode has, and the interrupt occurs when T0CNT equals to T0DR.

  • Page 99: Figure 36. Input Capture Mode Operation For Timer 0

    A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5 Figure 36. Input Capture Mode Operation for Timer 0 Figure 37. Express Timer Overflow in Capture Mode...

  • Page 100: Timer 0 Block Diagram

    12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual 12.1.4 Timer 0 block diagram INT_ACK Clear To interrupt T0OVIFR block fx/2 fx/4 8-bit Timer 0 Counter Match signal fx/8 Clear INT_ACK T0CNT (8Bit) fx/32 T0CC Clear fx/128 Clear fx/512 Match To interrupt T0EN...
  • Page 101 A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5 T0DR (Timer 0 Data Register): B4H T0DR7 T0DR6 T0DR5 T0DR4 T0DR3 T0DR2 T0DR1 T0DR0 Initial value: FFH T0DR[7:0] T0 Data T0CDR (Timer 0 Capture Data Register: Read Case, Capture mode only): B4H T0CDR7 T0CDR6...

  • Page 102: Timer 1

    12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual 12.2 Timer 1 A 16-bit timer 1 consists of multiplexer, timer 1 A data register high/low, timer 1 B data register high/low and timer 1 control register high/low (T1ADRH, T1ADRL, T1BDRH, T1BDRL, T1CRH, T1CRL).

  • Page 103: Figure 39. 16-Bit Timer/Counter Mode Of Timer 1

    A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5 ADDRESS:BBH – – – – T1EN T1MS1 T1MS0 T1CC T1CRH INITIAL VALUE : 0000_0000B – – – – ADDRESS:BAH – T1CK2 T1CK1 T1CK0 T1IFR T1POL T1ECE T1CNTR T1CRL INITIAL VALUE : 0000_0000B – 16-bit A Data Register...

  • Page 104: 16-Bit Capture Mode

    12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual 12.2.2 16-bit capture mode It uses an internal/external clock as a clock source. Basically, the 16-bit timer 1 capture mode has the same function as the 16-bit timer/counter mode, and the interrupt occurs when T1CNTH/T1CNTL is equal to T1ADRH/T1ADRL.

  • Page 105: 16-Bit Ppg Mode

    A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5 Figure 42. 16-bit Capture Mode Operation Example 12.2.3 16-bit PPG mode TIMER 1 has a PPG (Programmable Pulse Generation) function. In PPG mode, T1O/PWM1O pin outputs up to 16-bit resolution PWM output. For this function, T1O/PWM1O pin must be configured as a PWM output by setting P1FSRL[5:4] to ‘11’.

  • Page 106: Figure 43. 16-Bit Ppg Mode Of Timer 1

    12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual ADDRESS:BBH – – – – T1EN T1MS1 T1MS0 T1CC T1CRH INITIAL VALUE : 0000_0000B – – – – ADDRESS:BAH – T1CK2 T1CK1 T1CK0 T1IFR T1POL T1ECE T1CNTR T1CRL INITIAL VALUE : 0000_0000B – 16-bit A Data Register...

  • Page 107: Figure 44. 16-Bit Ppg Mode Operation Example

    A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5 Repeat Mode(T1MS = 11b) and "Start High"(T1POL = 0b). Clear and Start Set T1EN Timer 1 clock Counter T1ADRH/L T1 Interrupt 1. T1BDRH/L(5) < T1ADRH/L PWM1O B Match A Match 2. T1BDRH/L >= T1ADRH/L...

  • Page 108: 16-Bit Timer 1 Block Diagram

    12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual 12.2.4 16-bit timer 1 block diagram In this section, a 16-bit timer 1 is described in a block diagram. 16-bit A Data Register T1ADRH/T1ADRL A Match Reload T1CC T1EN To Timer 2 T1CK[2:0] block...
  • Page 109 A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5 T1ADRH (Timer 1 A data High Register): BDH T1ADRH7 T1ADRH6 T1ADRH5 T1ADRH4 T1ADRH3 T1ADRH2 T1ADRH1 T1ADRH0 Initial value: FFH T1ADRH[7:0] T1 A Data High Byte T1ADRL (Timer 1 A Data Low Register): BCH T1ADRL7...
  • Page 110 12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual T1CRH (Timer 1ControlHigh Register): BBH – – – – T1EN T1MS1 T1MS0 T1CC – – – – Initial value: 00H T1EN Control Timer 1 Timer 1 disable Timer 1 enable (Counter clear and start)

  • Page 111: Timer 2

    A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5 T1CRL (Timer 1ControlLow Register): BAH – T1CK2 T1CK1 T1CK0 T1IFR T1POL T1ECE T1CNTR – Initial value: 00H T1CK[2:0] Select Timer 1 clock source. fx is main system clock frequency T1CK2 T1CK1 T1CK0 Description fx/2048...

  • Page 112: 16-Bit Timer/Counter Mode

    12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual The timer/counter 2 can be a divided clock of a system clock which is selected from prescaler output and T1 A Match (timer 1 A match signal). The clock source is selected by a clock selection logic, controlled by clock selection bits (T2CK[2:0]).

  • Page 113: Figure 46. 16-Bit Timer/Counter Mode Of Timer 2

    A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5 ADDRESS:C3H – – – – T2EN T2MS1 T2MS0 T2CC T2CRH INITIAL VALUE : 0000_0000B – – – – ADDRESS:C2H – – T2CK2 T2CK1 T2CK0 T2IFR T2POL T2CNTR T2CRL INITIAL VALUE : 0000_0000B – –...

  • Page 114: 16-Bit Capture Mode

    12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual 12.3.2 16-bit capture mode Timer 2 capture mode is set by configuring T2MS[1:0] as ‘01’. It uses an internal clock as a clock source. Basically, the 16-bit timer 2 capture mode has the same function as the 16-bit timer/counter mode, and the interrupt occurs when T2CNTH/T2CNTL is equal to T2ADRH/T2ADRL.

  • Page 115: Figure 49. 16-Bit Capture Mode Operation Example

    A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5 Figure 49. 16-bit Capture Mode Operation Example Figure 50. Express Timer Overflow in Capture Mode...

  • Page 116: 16-Bit Ppg Mode

    12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual 12.3.3 16-bit PPG mode TIMER 2 has a PPG (Programmable Pulse Generation) function. In PPG mode, T2O/PWM2O pin outputs up to 16-bit resolution PWM output. For this function, T2O/PWM2O pin must be configured as a PWM output by setting P1FSRL[3:2] to ‘11’.

  • Page 117: Figure 52. 16-Bit Ppg Mode Operation Example

    A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5 Repeat Mode(T2MS = 11b) and "Start High"(T2POL = 0b). Clear and Start Set T2EN Timer 2 clock Counter T2ADRH/L T2 Interrupt 1. T2BDRH/L(5) < T2ADRH/L PWM2O B Match A Match 2. T2BDRH/L >= T2ADRH/L...

  • Page 118: 16-Bit Timer 2 Block Diagram

    12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual 12.3.4 16-bit timer 2 block diagram In this section, a 16-bit timer 2 is described in a block diagram. 16-bit A Data Register T2ADRH/T2ADRL A Match Reload T2CC T2CK[2:0] T2EN INT_ACK Buffer Register A...
  • Page 119 A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5 T2ADRH (Timer 2 A data High Register): C5H T2ADRH7 T2ADRH6 T2ADRH5 T2ADRH4 T2ADRH3 T2ADRH2 T2ADRH1 T2ADRH0 Initial value: FFH T2ADRH[7:0] T2 A Data High Byte T2ADRL (Timer 2 A Data Low Register): C4H T2ADRL7...
  • Page 120 12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual T2CRH (Timer 2ControlHigh Register): C3H – – – – T2EN T2MS1 T2MS0 T2CC – – – – Initial value: 00H T2EN Control Timer 2 Timer 2 disable Timer 2 enable (Counter clear and start)

  • Page 121: Timer 3

    A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5 12.4 Timer 3 A 16-bit timer 3 consists of a multiplexer, timer 3 A data high/low register, timer 3 B data high/low register and timer 3 control high/low register (T3ADRH, T3ADRL, T3BDRH, T3BDRL, T3CRH, and T3CRL).

  • Page 122: Figure 47. 16-Bit Timer/Counter Mode Operation Example

    12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual ADDRES S:1000H – – – – T3EN T3MS1 T3MS0 T3CC T3CRH INITIAL VALUE : 0000_0000B – – – – ADDRES S:1001H – T3CK2 T3CK1 T3CK0 T3IFR T3POL T3ECE T3CNTR T3CRL INITIAL VALUE : 0000_0000B –...

  • Page 123: 16-Bit Capture Mode

    A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5 12.4.2 16-bit capture mode Timer 3 capture mode is set by configuring T3MS[1:0] as ‘01’. It uses an internal/external clock as a clock source. Basically, the 16-bit timer 3 capture mode has the same function as the 16-bit timer/counter mode, and the interrupt occurs when T3CNTH/T3CNTL is equal to T3ADRH/T3ADRL.

  • Page 124: Figure 57. 16-Bit Capture Mode Operation Example

    12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual Figure 57. 16-bit Capture Mode Operation Example Figure 58. Express Timer Overflow in Capture Mode...

  • Page 125: 16-Bit Ppg Mode

    A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5 12.4.3 16-bit PPG mode TIMER 3 has a PPG (Programmable Pulse Generation) function. In PPG mode, T3O/PWM3O pin outputs up to 16-bit resolution PWM output. For this function, T3O/PWM3O pin must be configured as a PWM output by setting P0FSRH[1:0] to ‘11’...

  • Page 126: Figure 60. 16-Bit Ppg Mode Operation Example

    12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual Repeat Mode(T3MS = 11b) and "Start High"(T3POL = 0b). Clear and Start Set T3EN Timer 3 clock Counter T3ADRH/L T3 Interrupt 1. T3BDRH/L(5) < T3ADRH/L PWM3O B Match A Match 2. T3BDRH/L >= T3ADRH/L...
  • Page 127 A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5...

  • Page 128: 16-Bit Timer 3 Block Diagram

    12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual 12.4.4 16-bit timer 3 block diagram In this section, a 16-bit timer 3 is described in a block diagram. 16-bit A Data Register T3ADRH/T3ADRL A Match Reload T3CC T3EN To Timer 4 T3CK[2:0] block...
  • Page 129 A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5 T3ADRH (Timer 3 A data High Register): 1002H T3ADRH7 T3ADRH6 T3ADRH5 T3ADRH4 T3ADRH3 T3ADRH2 T3ADRH1 T3ADRH0 Initial value: FFH T3ADRH[7:0] T3 A Data High Byte T3ADRL (Timer 3 A Data Low Register): 1003H T3ADRL7...
  • Page 130 12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual T3CRH (Timer 3 Control High Register): 1000H – – – – T3EN T3MS1 T3MS0 T3CC – – – – Initial value: 00H T3EN Control Timer 3 Timer 3 disable Timer 3 enable (Counter clear and start)

  • Page 131: Timer 4

    A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5 T3CRL (Timer 3 Control Low Register): 1001H – T3CK2 T3CK1 T3CK0 T3IFR T3POL T3ECE T3CNTR – Initial value: 00H T3CK[2:0] Select Timer 3 clock source. fx is main system clock frequency T3CK2 T3CK1 T3CK0 Description...

  • Page 132: 16-Bit Timer/Counter Mode

    12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual The timer/counter 4 can be a divided clock of a system clock selected from prescaler output and T3 A Match (timer 3 A match signal). The clock source is selected by a clock selection logic controlled by clock selection bits (T4CK[2:0]).

  • Page 133: Figure 55. 16-Bit Timer/Counter Mode Operation Example

    A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5 ADDRES S:1008H – – – – T4EN T4MS1 T4MS0 T4CC T4CRH INITIAL VALUE : 0000_0000B – – – – ADDRES S:1009H – – T4CK2 T4CK1 T4CK0 T4IFR T4POL T4CNTR T4CRL INITIAL VALUE : 0000_0000B –...

  • Page 134: 16-Bit Capture Mode

    12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual 12.5.2 16-bit capture mode Timer 4 capture mode is set by configuring T4MS[1:0] as ‘01’. It uses an internal clock as a clock source. Basically, the 16-bit timer 4 capture mode has the same function as the 16-bit timer/counter mode, and the interrupt occurs when T4CNTH/T4CNTL is equal to T4ADRH/T4ADRL.

  • Page 135: Figure 65. 16-Bit Capture Mode Operation Example

    A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5 Figure 65. 16-bit Capture Mode Operation Example Figure 66. Express Timer Overflow in Capture Mode...

  • Page 136: 16-Bit Ppg Mode

    12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual 12.5.3 16-bit PPG mode TIMER 4 has a PPG (Programmable Pulse Generation) function. In PPG mode, T4O/PWM4O pin outputs up to 16-bit resolution PWM output. For this function, T4O/PWM4O pin must be configured as a PWM output by setting P0FSRH[3:2] to ‘11’.

  • Page 137: Figure 68. 16-Bit Ppg Mode Operation Example

    A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5 Repeat Mode(T4MS = 11b) and "Start High"(T4POL = 0b). Clear and Start Set T4EN Timer 4 clock Counter T4ADRH/L T4 Interrupt 1. T4BDRH/L(5) < T4ADRH/L PWM4O B Match A Match 2. T4BDRH/L >= T4ADRH/L...

  • Page 138: 16-Bit Timer 4 Block Diagram

    12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual 12.5.4 16-bit timer 4 block diagram In this section, a 16-bit timer 4 is described in a block diagram. 16-bit A Data Re gister T4ADRH/T4ADRL A Match Reload T4CC T4CK[2:0] T4EN Buffer Register A...
  • Page 139 A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5 T4ADRH (Timer 4 A data High Register): 100AH T4ADRH7 T4ADRH6 T4ADRH5 T4ADRH4 T4ADRH3 T4ADRH2 T4ADRH1 T4ADRH0 Initial value: FFH T4ADRH[7:0] T4 A Data High Byte T4ADRL (Timer 4 A Data Low Register): 100BH T4ADRL7...
  • Page 140 12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual T4CRH (Timer 4 Control High Register): 1008H – – – – T4EN T4MS1 T4MS0 T4CC – – – – Initial value: 00H T4EN Control Timer 4 Timer 4 disable Timer 4 enable (Counter clear and start)

  • Page 141: Timer 5

    A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5 12.6 Timer 5 A 16-bit timer 5 consists of a multiplexer, timer 5 A data high/low register, timer 5 B data high/low register and timer 5 control high/low register (T5ADRH, T5ADRL, T5BDRH, T5BDRL, T5CRH, and T5CRL).

  • Page 142: Figure 63. 16-Bit Timer/Counter Mode Operation Example

    12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual ADDRES S:1010H – – – – T5EN T5MS1 T5MS0 T5CC T5CRH INITIAL VALUE : 0000_0000B – – – – ADDRES S:1011H – – T5CK2 T5CK1 T5CK0 T5IFR T5POL T5CNTR T5CRL INITIAL VALUE : 0000_0000B –...

  • Page 143: 16-Bit Capture Mode

    A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5 12.6.2 16-bit capture mode Timer 5 capture mode is set by configuring T5MS[1:0] as ‘01’. It uses an internal clock as a clock source. Basically, the 16-bit timer 5 capture mode has the same function as the 16-bit timer/counter mode, and the interrupt occurs when T5CNTH/T5CNTL is equal to T5ADRH/T5ADRL.

  • Page 144: 16-Bit Ppg Mode

    12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual Figure 73. 16-bit Capture Mode Operation Example Figure 74. Express Timer Overflow in Capture Mode 12.6.3 16-bit PPG mode TIMER 5 has a PPG (Programmable Pulse Generation) function. In PPG mode, T5O/PWM5O pin...

  • Page 145: Figure 75. 16-Bit Ppg Mode Of Timer 5

    A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5 outputs up to 16-bit resolution PWM output. For this function, T5O/PWM5O pin must be configured as a PWM output by setting P0FSRH[5:4] to ‘11’. Period of the PWM output is determined by T5ADRH/T5ADRL, and duty of the PWM output is determined by T5BDRH/T5BDRL.

  • Page 146: Figure 76. 16-Bit Ppg Mode Operation Example

    12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual Repeat Mode(T5MS = 11b) and "Start High"(T5POL = 0b). Clear and Start Set T5EN Timer 5 clock Counter T5ADRH/L T5 Interrupt 1. T5BDRH/L(5) < T5ADRH/L PWM5O B Match A Match 2. T5BDRH/L >= T5ADRH/L...

  • Page 147: 16-Bit Timer 5 Block Diagram

    A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5 12.6.4 16-bit timer 5 block diagram In this section, a 16-bit timer 5 is described in a block diagram. 16-bit A Data Re gister T5ADRH/T5ADRL A Match Reload T5CC T5CK[2:0] T5EN Buffer Register A...
  • Page 148 12. Timer 0/1/2/3/4/5 A96G140/A96G148/A96A148 User’s manual T5ADRH (Timer 5 A data High Register): 1012H T5ADRH7 T5ADRH6 T5ADRH5 T5ADRH4 T5ADRH3 T5ADRH2 T5ADRH1 T5ADRH0 Initial value: FFH T5ADRH[7:0] T5 A Data High Byte T5ADRL (Timer 5 A Data Low Register): 1013H T5ADRL7...
  • Page 149 A96G140/A96G148/A96A148 User’s manual 12. Timer 0/1/2/3/4/5 T5CRH (Timer 5 Control High Register): 1010H – – – – T5EN T5MS1 T5MS0 T5CC – – – – Initial value: 00H T5EN Control Timer 5 Timer 5 disable Timer 5 enable (Counter clear and start)

  • Page 150: Buzzer Driver

    A96G140/A96G148/A96A148 User’s manual Buzzer driver A buzzer of A96G140/A96G148/A96A148 consists of 8-bit counter, a buzzer data register (BUZDR), and a buzzer control register (BUZCR). It outputs square wave (61.035Hz to 125.0KHz @ 8MHz) through P13/AN10/EC1/BUZO pin, and its buzzer data register (BUZDR) controls the buzzer frequency (refer to the following expression).

  • Page 151: Register Description

    A96G140/A96G148/A96A148 User’s manual 13. Buzzer driver Table 27. Buzzer Driver Register Map Name Address Direction Default Description BUZDR Buzzer Data Register BUZCR Buzzer Control Register 13.3 Register description BUZDR (Buzzer Data Register): 8FH BUZDR7 BUZDR6 BUZDR5 BUZDR4 BUZDR3 BUZDR2 BUZDR1...

  • Page 152: 12-Bit Adc

    A96G140/A96G148/A96A148 User’s manual 12-bit ADC Analog-to-digital converter (ADC) of A96G140/A96G148/A96A148 allows conversion of an analog input signal to corresponding 12-bit digital value. This A/D module has eight analog inputs. Output of the multiplexer becomes input into the converter which generates the result through successive approximation.

  • Page 153: Figure 79. 12-Bit Adc Block Diagram

    A96G140/A96G148/A96A148 User’s manual 14. 12-bit ADC TRIG[2:0] ADSEL[3:0] (Select one input pin ADST of the assigned pins) T1 A match signal Start T3 A match signal EXTINT0~7 EXTINT8 Clock ADCLK Selector Clear Input Pins AFLAG AN14 AN15 Comparator Control To interrupt...

  • Page 154: Adc Operation

    14. 12-bit ADC A96G140/A96G148/A96A148 User’s manual 14.3 ADC operation In this section, control registers and align bits are introduced in figure 80, and ADC operation flow sequence is introduced in figure 81. Align bit set “0” ADCO11 ADCO10 ADCO9 ADCO8...

  • Page 155: Register Map

    A96G140/A96G148/A96A148 User’s manual 14. 12-bit ADC Figure 83. ADC Operation Flow Sequence 14.4 Register map Table 28. ADC Register Map Name Address Direction Default Description ADCDRH A/D Converter Data High Register ADCDRL A/D Converter Data Low Register ADCCRH A/D Converter Control High Register...
  • Page 156 14. 12-bit ADC A96G140/A96G148/A96A148 User’s manual ADCDRL (A/D Converter Data Low Register): 9EH ADDM3 ADDM2 ADDM1 ADDM0 ADDL7 ADDL6 ADDL5 ADDL4 ADDL3 ADDL2 ADDL1 ADDL0 Initial value: xxH ADDM[3:0] MSB align, A/D Converter Low Data (4-bit) ADDL[7:0] LSB align, A/D Converter Low Data (8-bit)
  • Page 157 A96G140/A96G148/A96A148 User’s manual 14. 12-bit ADC ADCCRL (A/D Converter Counter Low Register): 9CH STBY ADST REFSEL AFLAG ADSEL3 ADSEL2 ADSEL1 ADSEL0 Initial value: 00H STBY Control Operation of A/D (The ADC module is automatically disabled at stop mode) ADC module disable...

  • Page 158: Usi (Usart + Spi + I2C)

    A96G140/A96G148/A96A148 User’s manual USI (USART + SPI + I2C) USI stands for the combination of USART, SPI and I2C. A96G140/A96G148/A96A148 has two USI function blocks, USI0 and USI1, which are identical to each other functionally. Each USI block consists of USI control registers 1/2/3/4, USI status registers 1/2, USI baud-rate generation register, USI data...

  • Page 159: Usin Uart Block Diagram

    A96G140/A96G148/A96A148 User’s manual 15. USI Transmitter consists of a single write buffer, a serial shift register, parity generator and control logic for handling different serial frame formats. A write buffer allows continuous transfer of data without any delay between frames.

  • Page 160: Usin Clock Generation

    15. USI A96G140/A96G148/A96A148 User’s manual 15.3 USIn clock generation Figure 85. Clock Generation Block Diagram (USIn) Clock generation logic generates base clock signal for the transmitter and the receiver. The USIn supports four modes of clock operation such as normal asynchronous mode, double speed asynchronous mode, master synchronous mode and slave synchronous mode.

  • Page 161: Usin External Clock (Sckn)

    A96G140/A96G148/A96A148 User’s manual 15. USI 15.4 USIn external clock (SCKn) External clocking is used in synchronous mode of operation. External clock input from the SCKn pin is sampled by a synchronization logic to remove meta-stability. The output from the synchronization logic must be passed through an edge detector before it is used by the transmitter and receiver.

  • Page 162: Usin Uart Parity Bit

    15. USI A96G140/A96G148/A96A148 User’s manual 1 start bit  5, 6, 7, 8 or 9 data bits  no, even or odd parity bit  1 or 2 stop bits  A frame starts with a start bit followed by the least significant data bit (LSB). The next data bits, up to nine, are succeeding, ending with the most significant bit (MSB).

  • Page 163: Usin Uart Transmitter

    A96G140/A96G148/A96A148 User’s manual 15. USI = Dn-1 ^ … ^ D3 ^ D2 ^ D1 ^ D0 ^ 0  even = Dn-1 ^ … ^ D3 ^ D2 ^ D1 ^ D0 ^ 1  : Parity bit using even parity ...

  • Page 164: Usin Uart Parity Generator

    15. USI A96G140/A96G148/A96A148 User’s manual The TXCn flag is automatically cleared when the transmit complete interrupt serve routine is executed, or it can be cleared by writing ‘0’ to TXCn bit in USInST1 register. When the transmit complete interrupt enable (TXCIEn) bit in USInCR2 register is set and the global interrupt is enabled, UART transmit complete interrupt is generated while TXCn flag is set.

  • Page 165: Usin Uart Receiver Flag And Interrupt

    A96G140/A96G148/A96A148 User’s manual 15. USI 15.9.2 USIn UART receiver flag and interrupt The UART receiver has one flag that indicates the receiver state. The receive complete (RXCn) flag indicates whether there are unread data in the receive buffer. This flag is set when there is unread data in the receive buffer and cleared when the receive buffer is empty.

  • Page 166: Figure 88. Asynchronous Start Bit Sampling (Usin)

    15. USI A96G140/A96G148/A96A148 User’s manual The data recovery logic does sampling and low pass filtering the incoming bits, and removing the noise of RXDn pin. The next figure illustrates the sampling process of the start bit of an incoming frame. The sampling rate is 16 times of the baud-rate in normal mode and 8 times the baud-rate for double speed mode (DBLSn=1).

  • Page 167: 15.10 Usin Spi Mode

    A96G140/A96G148/A96A148 User’s manual 15. USI BIT n RXDn Sample (DBLSn = 0) Sample (DBLSn = 1) Figure 89. Asynchronous Sampling of Data and Parity Bit (USIn) The process for detecting stop bit is same as clock and data recovery process. That is, if 2 or more samples of 3 center values have high level, correct stop bit is detected, else a frame error (FEn) flag is set.

  • Page 168: 15.11 Usin Spi Clock Formats And Timing

    15. USI A96G140/A96G148/A96A148 User’s manual Note that during SPI mode of operation, the pin RXDn is renamed as MISOn and TXDn is renamed as MOSIn for compatibility to other SPI devices. 15.11 USIn SPI clock formats and timing To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the USIn has a clock polarity bit (CPOLn) and a clock phase control bit (CPHAn) to select one of four clock formats for data transfers.

  • Page 169: Figure 92. Usin Spi Clock Formats When Cphan = 1

    A96G140/A96G148/A96A148 User’s manual 15. USI goes to active low. The first SCKn edge causes both the master and the slave to sample the data bit value on their MISOn and MOSIn inputs, respectively. At the second SCKn edge, the USIn shifts the second data bit value out to the MOSIn and MISOn outputs of the master and slave, respectively.

  • Page 170: 15.12 Usin Spi Block Diagram

    15. USI A96G140/A96G148/A96A148 User’s manual In master mode of operation, even if transmission is not enabled (TXEn=0), writing data to the USInDR register is necessary because the clock SCKn is generated from transmitter block. 15.12 USIn SPI block diagram USInBD...

  • Page 171: 15.14 Usin I2C Bit Transfer

    A96G140/A96G148/A96A148 User’s manual 15. USI Both master and slave operation  Bus busy detection  15.14 USIn I2C bit transfer The data on the SDAn line must be stable during HIGH period of the clock, SCLn. The HIGH or LOW state of the data line can only change when the clock signal on the SCLn line is LOW.

  • Page 172: 15.16 Usin I2C Data Transfer

    15. USI A96G140/A96G148/A96A148 User’s manual SDAn SCLn START Condition STOP Condition Figure 95. START and STOP Condition (USIn) 15.16 USIn I2C data transfer Every byte put on the SDAn line must be 8-bits long. The number of bytes that can be transmitted per transfer is unlimited.

  • Page 173: 15.18 Usin I2C Synchronization/ Arbitration

    A96G140/A96G148/A96A148 User’s manual 15. USI The master can then generate either a STOP condition to abort the transfer, or a repeated START condition to start a new transfer. If a master receiver is involved in a transfer, it must signal the end of data to the slave transmitter by not generating an acknowledge on the last byte that was clocked out of the slave.

  • Page 174: 15.19 Usin I2C Operation

    15. USI A96G140/A96G148/A96A148 User’s manual Wait High Start High Counting Counting Fast Device SCLOUT High Counter Reset Slow Device SCLOUT SCLn Figure 98. Clock Synchronization during Arbitration Procedure (USIn) Arbitration Process Device 1 loses Device1 outputs not adapted Arbitration High...

  • Page 175: Usin I2C Master Transmitter

    A96G140/A96G148/A96A148 User’s manual 15. USI 15.19.1 USIn I2C master transmitter To operate I2C in master transmitter, follow the recommended steps below: Enable I2C by setting USInMS[1:0] bits in USInCR1 and USInEN bit in USInCR2. This provides main clock to the peripheral.
  • Page 176 15. USI A96G140/A96G148/A96A148 User’s manual set the STOPCn bit in USInCR4. Case 3: Master transmits repeated START condition with not checking ACK signal. In this case, load SLAn+R/W into the USInDR and set STARTCn bit in USInCR4. After doing one of the actions above, write any arbitrary to USInST2 to release SCLn line.

  • Page 177: Usin I2C Master Receiver

    A96G140/A96G148/A96A148 User’s manual 15. USI 15.19.2 USIn I2C master receiver To operate I2C in master receiver, follow the recommended steps below: Enable I2C by setting USInMS[1:0] bits in USInCR1and USInEN bit in USInCR2. This provides main clock to the peripheral.

  • Page 178: Usin I2C Slave Transmitter

    15. USI A96G140/A96G148/A96A148 User’s manual Case 2: Master stops data transfer because it receives no ACK signal from slave. In this case, set the STOPCn bit in USInCR4. Case 3: Master transmits repeated START condition due to no ACK signal from slave. In this case, load SLAn+R/W into the USInDR and set STARTCn bit in USInCR4.

  • Page 179: Usin I2C Slave Receiver

    A96G140/A96G148/A96A148 User’s manual 15. USI If the main operating clock (SCLK) of the system is slower than that of SCLn, load value 0x00 into USInSDHR to make SDAn change within one system clock period from the falling edge of SCLn. Note that the hold time of SDAn is calculated by SDAH x period of SCLK where SDAH is multiple of number of SCLK coming from USInSDHR.
  • Page 180 15. USI A96G140/A96G148/A96A148 User’s manual If the main operating clock (SCLK) of the system is slower than that of SCLn, load value 0x00 into USInSDHR to make SDAn change within one system clock period from the falling edge of SCLn. Note that the hold time of SDAn is calculated by SDAH x period of SCLK where SDAH is multiple of number of SCLK coming from USInSDHR.

  • Page 181: 15.20 Usin I2C Block Diagram

    A96G140/A96G148/A96A148 User’s manual 15. USI 15.20 USIn I2C block diagram IICnIFR To interrupt block Slave Address Register USInSAR RXACKn, GCALLn, Interrupt IICnIE TENDn, STOPDn, Generator SSELn, MLOSTn, General Call And USInGCE BUSYn, TMODEn Address Detector Receive Shift Register SDAn USInDR, (Rx)

  • Page 182: 15.22 Usin Register Description

    15. USI A96G140/A96G148/A96A148 User’s manual Table 31. USI Register Map (continued) Name Address Direction Default Description USI0ST1 USI0 Status Register 1 USI0ST2 USI0 Status Register 2 USI1BD USI1 Baud Rate Generation Register USI1DR USI1 Data Register USI1SDHR USI1 SDA Hold Time Register...
  • Page 183 A96G140/A96G148/A96A148 User’s manual 15. USI USInDR (USIn Data Register: For UART, SPI, and I2C mode): E5H/F5H, n = 0, 1 USInDR7 USInDR 6 USInDR 5 USInDR 4 USInDR 3 USInDR 2 USInDR 1 USInDR 0 Initial value: 00H USInDR[7:0] The USIn transmit buffer and receive buffer share the same I/O address with this DATA register.
  • Page 184 15. USI A96G140/A96G148/A96A148 User’s manual USInSCLR (USInSCL Low Period Register: For I2C mode): E6H/F6H, n = 0, 1 USInSCLR7 USInSCLR6 USInSCLR5 USInSCLR 4 USInSCLR 3 USInSCLR 2 USInSCLR 1 USInSCLR 0 Initial value: 3FH USInSCLR[7:0] This register defines the high period of SCLn when it operates in I2C master mode.
  • Page 185 A96G140/A96G148/A96A148 User’s manual 15. USI USInCR1 (USIn Control Register 1: For UART, SPI, and I2C mode): D9H/E9H, n = 0, 1 USInS1 USInS0 USInMS1 USInMS0 USInPM1 USInPM0 USInS2 CPOLn ORDn CPHAn Initial value: 00H USInMS[1:0] Selects operation mode of USIn...
  • Page 186 15. USI A96G140/A96G148/A96A148 User’s manual USInCR2 (USIn Control Register 2: For UART, SPI, and I2C mode): DAH/EAH, n = 0, 1 DRIEn TXCIEn RXCIEn WAKEIEn TXEn RXEn USInEN DBLSn Initial value: 00H DRIEn Interrupt enable bit for data register empty (only UART and SPI mode).
  • Page 187 A96G140/A96G148/A96A148 User’s manual 15. USI USInCR3 (USIn Control Register 3: For UART, SPI, and I2C mode): DBH/EBH, n = 0, 1 MASTERn LOOPSn DISSCKn USInSSEN FXCHn USInSB USInTX8 USInRX8 Initial value: 00H MASTERn Selects master or slave in SPI and synchronous mode operation and controls the direction of SCKn pin Slave mode operation (External clock for SCKn).
  • Page 188 15. USI A96G140/A96G148/A96A148 User’s manual USI0CR4 (USIn Control Register 4: For I2C mode): DCH/ECH, n = 0, 1 – IICnIFR RESETn IICnIE ACKnEN IMASTERn STOPCn STARTCn – Initial value: 00H IICnIFR This is an interrupt flag bit for I2C mode. When an interrupt occurs, this bit becomes ‘1’.
  • Page 189 A96G140/A96G148/A96A148 User’s manual 15. USI USInST1 (USIn Status Register 1: For UART and SPI mode): E1H/F1H, n = 0, 1 DREn TXCn RXCn WAKEn USInRST DORn Initial value: 80H DREn The DREn flag indicates if the transmit buffer (USInDR) is ready to receive new data.

  • Page 190: Baud Rate Settings (Example)

    15. USI A96G140/A96G148/A96A148 User’s manual USInST2 (USIn Status Register 2: For I2C mode): E2H/F2H, n = 0, 1 GCALLn TENDn STOPDn SSELn MLOSTn BUSYn TMODEn RXACKn Initial value: 00H (NOTE) GCALLn This bit has different meaning depending on whether I2C is master or slave.

  • Page 191: Table 33. Example1 Of Usi0Bd And Usi1Bdsettings For Commonly Used Oscillator Frequencies

    A96G140/A96G148/A96A148 User’s manual 15. USI Table 32. Example1 of USI0BD and USI1BDSettings for Commonly Used Oscillator Frequencies Baud fx = 1.00MHz fx = 1.8432MHz fx = 2.00MHz rate USI0BD/USI1BD Error USI0BD/USI1BD Error USI0BD/USI1BD Error (bps) 2400 0.2% 0.0% 0.2% 4800 0.2%...

  • Page 192: Table 34. Example2 Of Usi0Bd And Usi1Bdsettings For Commonly Used Oscillator Frequencies

    15. USI A96G140/A96G148/A96A148 User’s manual Table 33. Example2 of USI0BD and USI1BDSettings for Commonly Used Oscillator Frequencies Baud rate fx = 8.00MHz fx = 11.0592MHz (bps) USI0BD/USI1BD Error USI0BD/USI1BD Error ― ― 2400 0.2% 4800 0.2% 0.0% 9600 0.2% 0.0% 14.4k...

  • Page 193: Usart2

    16. USART 2 USART2 Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. USART2 of A96G140/A96G148/A96A148 features the followings: Full Duplex Operation (Independent Serial Receive and Transmit Registers)  Asynchronous or Synchronous Operation ...

  • Page 194: Block Diagram

    16. USART 2 A96G140/A96G148/A96A148 User’s manual 16.1 Block diagram UBAUD SCLK Baud Rate Generator Master Clock Sync Logic Control UMSEL[1:0] Rx Interrupt RXD2/ MISO2 Clock Control Recovery Data Recovery UMSEL1&UMSEL0 DOR/PE/FE UDATA[0] Master Checker (Rx) UDATA[1] Stop bit UMSEL0 (Rx)

  • Page 195: Clock Generation

    A96G140/A96G148/A96A148 User’s manual 16. USART 2 16.2 Clock generation Clock generation logic generates a base clock signal for the Transmitter and the Receiver. USART2 supports four modes of clock operation such as Normal Asynchronous mode, Double Speed Asynchronous mode, Master Synchronous mode, and Slave Synchronous mode.

  • Page 196: External Clock (Xck)

    16. USART 2 A96G140/A96G148/A96A148 User’s manual 16.3 External clock (XCK) External clocking is used by the synchronous or SPI slave modes of operation. External clock input from the XCK pin is sampled by a synchronization logic to remove meta-stability. The output from the synchronization logic must then pass through an edge detector before it can be used by the Transmitter and Receiver.

  • Page 197: Data Format

    A96G140/A96G148/A96A148 User’s manual 16. USART 2 16.5 Data format A serial frame is defined to consist of one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. USART2 supports all 30 combinations of the followings as a valid frame format.

  • Page 198: Parity Bit

    16. USART 2 A96G140/A96G148/A96A148 User’s manual 16.6 Parity bit Parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result of the exclusive-or is inverted. The parity bit is located between St + bits and first stop bit of a serial frame.

  • Page 199: Parity Generator

    A96G140/A96G148/A96A148 User’s manual 16. USART 2 this bit field. Writing ‘1’ to this field is not valid. When Data Register Empty Interrupt Enable (UDRIE) bit in UCTRL2 register is set and Global Interrupt is enabled, USART2 Data Register Empty Interrupt is generated while UDRE flag is set.

  • Page 200: Receiver Flag And Interrupt

    16. USART 2 A96G140/A96G148/A96A148 User’s manual If 9-bit characters are used (USIZE[2:0] = 7), the ninth bit is stored in RX8 bit field in the UCTRL3 register. The 9th bit must be read from the RX8 bit before reading the low 8 bits from the UDATA register.

  • Page 201: Asynchronous Data Reception

    A96G140/A96G148/A96A148 User’s manual 16. USART 2 becomes normal GPIO or primary function pin. 16.8.5 Asynchronous data reception To receive asynchronous data frame, the USART2 includes a clock and data recovery unit. The Clock Recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frame on the RXD2 pin.

  • Page 202: Spi Mode

    16. USART 2 A96G140/A96G148/A96A148 User’s manual Internally, after receiving the first stop bit, the Receiver is in idle state and waiting to find start bit. BIT n RxD2 Sample (U2X = 0) Sample (U2X = 1) Figure 106. Sampling of Data and Parity Bit A process for detecting stop bit is similar to the clock and data recovery process.

  • Page 203: Spi Clock Formats And Timing

    A96G140/A96G148/A96A148 User’s manual 16. USART 2 Note that during SPI mode of operation, the pin RXD2 is renamed as MISO2, and TXD2 is renamed as MOSI2 for compatibility to other SPI devices. 16.9.1 SPI clock formats and timing To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the USART2 has a clock polarity bit (UCPOL) and a clock phase control bit (UCPHA) to select one of four clock formats for data transfers.

  • Page 204: Figure 109. Spi Clock Formats When Ucpha = 1

    16. USART 2 A96G140/A96G148/A96A148 User’s manual When UCPHA=0, the slave begins to drive its MISO2 output with the first data bit value when SS goes to active low. The first XCK edge causes both the master and the slave to sample the data bit value on their MISO2 and MOSI inputs, respectively.

  • Page 205: Receiver Time Out (Rto)

    A96G140/A96G148/A96A148 User’s manual 16. USART 2 In master mode of operation, even if transmission is not enabled (TXE=0), writing data to UDATA register is necessary because the clock XCK is generated from a transmitter block. 16.10 Receiver time out (RTO) This USART2 system supports the time out function.

  • Page 206: 16.11 Register Map

    16. USART 2 A96G140/A96G148/A96A148 User’s manual 16.11 Register map Table 37. USART2 Register Map Name Address Direction Default Description UCTRL1 USART2 Control 1 Register UCTRL2 USART2 Control 2 Register UCTRL3 USART2 Control 3 Register UCTRL4 1018H USART2 Control 4 Register...
  • Page 207 A96G140/A96G148/A96A148 User’s manual 16. USART 2 UCTRL1 (USART2 Control 1 Register) CBH USIZE1 USIZE0 UMSEL1 UMSEL0 UPM1 UPM0 USIZE2 UCPOL UDORD UCPHA Initial value: 00 UMSEL[1:0] Selects operation mode of USART2 UMSEL1 UMSEL0 Operating Mode Asynchronous Mode (Normal Uart) Synchronous Mode (Synchronous Uart)
  • Page 208 16. USART 2 A96G140/A96G148/A96A148 User’s manual UCTRL2 (USART2 Control 2 Register) CCH UDRIE TXCIE RXCIE WAKEIE USARTEN Initial value: 00 UDRIE Interrupt enable bit for USART2 Data Register Empty. Interrupt from UDRE is inhibited (use polling) When UDRE is set, request an interrupt TXCIE Interrupt enable bit for Transmit Complete.
  • Page 209 A96G140/A96G148/A96A148 User’s manual 16. USART 2 UCTRL3 (USART2 Control 3 Register) CDH MASTER LOOPS DISXCK SPISS USBS Initial value: 00 MASTER Selects master or slave in SPI or Synchronous mode operation and controls the direction of XCK pin. Slave mode operation and XCK is input pin.
  • Page 210 16. USART 2 A96G140/A96G148/A96A148 User’s manual UCTRL4 (USART2 Control 4 Register) 1018H RTOEN RTO_FLAG FPCREN AOVSSEL AOVSEN Initial value: 00 RTOEN Enable receiver time out. Disable Enable RTO_FLAG This bit is set when RTO count overflows. This flag can generate an RTO interrupt.
  • Page 211 A96G140/A96G148/A96A148 User’s manual 16. USART 2 USTAT (USART2 Status Register) CFH UDRE WAKE SOFTRST Initial value: 80 UDRE The UDRE flag indicates if the transmit buffer (UDATA) is ready to be loaded with new data. If UDRE is ‘1’, it means the transmit buffer is empty and can hold one or two new data.
  • Page 212 16. USART 2 A96G140/A96G148/A96A148 User’s manual UBAUD (USART Baud-Rate Generation Register) FCH UBAUD7 UBAUD6 UBAUD5 UBAUD4 UBAUD3 UBAUD2 UBAUD1 UBAUD0 Initial value: FF UBAUD [7:0] The value in this register is used to generate internal baud rate in asynchronous mode or to generate XCK clock in synchronous or SPI mode.
  • Page 213 A96G140/A96G148/A96A148 User’s manual 16. USART 2 RTOCH (Receiver Time Out Counter High Register) 101AH RTOCH7 RTOCH6 RTOCH5 RTOCH4 RTOCH3 RTOCH2 RTOCH1 RTOCH0 Initial value: 00 RTOCL (Receiver Time Out Counter Low Register) 101BH RTOCL7 RTOCL6 RTOCL5 RTOCL4 RTOCL3 RTOCL2 RTOCL1...

  • Page 214: Baud Rate Settings (Example)

    16. USART 2 A96G140/A96G148/A96A148 User’s manual 16.13 Baud rate settings (example) Table 38. Examples of UBAUD Settings for Commonly Used Oscillator Frequencies fOSC=1.00MHz fOSC=1.8432MHz fOSC=2.00MHz Baud U2X=0 U2X=1 U2X=0 U2X=1 U2X=0 U2X=1 Rate UBAUD ERROR UBAUD ERROR UBAUD ERROR UBAUD...

  • Page 215: 16.14 0% Error Baud Rate

    16. USART 2 16.14 0% error baud rate USART2 system of A96G140/A96G148/A96A148 supports floating point counter logic for 0% error of baud rate. By using 8-bit floating point counter logic, cumulative error to below the decimal point can be removed.

  • Page 216: Figure 111. 0% Error Baud Rate Block Diagram

    16. USART 2 A96G140/A96G148/A96A148 User’s manual Integer count value TXD clock 0% Error Baud rate Generator Integer count value - 1 8bit Max floating point count value 8bit floating point counter Figure 111. 0% Error Baud Rate Block Diagram...

  • Page 217: Power Down Operation

    A96G140/A96G148/A96A148 User’s manual 17. Power down operation Power down operation A96G140/A96G148/A96A148 has two power-down modes to minimize the power consumption of the device. power down mode, power consumption reduced considerably. A96G140/A96G148/A96A148 provides three kinds of power saving functions such as Main-IDLE mode, Sub-IDLE mode and STOP mode.

  • Page 218: Idle Mode

    17. Power down operation A96G140/A96G148/A96A148 User’s manual Table 39. Peripheral Operation Status during Power Down Mode (continued) Peripheral IDLE mode STOP mode Release Method By RESET By RESET   All Interrupts Timer Interrupt (EC0, EC1,   EC3) External Interrupt ...

  • Page 219: Released Operation Of Stop Mode

    A96G140/A96G148/A96A148 User’s manual 17. Power down operation Sources to exit from STOP mode is hardware reset and interrupts. The hardware reset re-defines all control registers. When awaking from STOP mode, enough oscillation stabilization time is required to normal operation. Figure 111 shows the timing diagram.

  • Page 220: Register Map

    17. Power down operation A96G140/A96G148/A96A148 User’s manual SET PCON[7:0] SET IEx.b STOP Mode Interrupt Request Corresponding Interrupt IEx.b==1 ? Enable Bit (IE, IE1, IE2, IE3) STOP Mode Release Interrupt Service Routine Next Instruction Figure 114. STOP Mode Release Flow 17.5 Register map Table 40.
  • Page 221 A96G140/A96G148/A96A148 User’s manual 17. Power down operation PCON (Power Control Register): 87H PCON7 – – – PCON3 PCON2 PCON1 PCON0 – – – Initial value: 00H PCON[7:0] Power Control IDLE mode enable STOP mode enable Other Values Normal operation NOTES: To enter into IDLE mode, PCON must be set to ‘01H’.

  • Page 222: Reset

    Accumulator Stack Pointer (SP) Peripheral Clock Control Register Refer to the Peripheral Registers A96G140/A96G148/A96A148 has five types of reset sources as shown in the followings: External RESETB  Power ON RESET (POR)  WDT Overflow Reset (In the case of WDTEN = `1`) ...

  • Page 223: Figure 116. Fast Vdd Rising Time

    A96G140/A96G148/A96A148 User’s manual 18. Reset Fast VDD Rising Time, max. 50.0V/ms nPOR BIT Overflows (Internal Signal) BIT Starts Internal RESETB Oscillation Figure 116. Fast VDD Rising Time Slow VDD Rising Time, min. 0.05V/ms =1.32V (Typ) nPOR BIT Overflows (Internal Signal)

  • Page 224: Figure 118. Configuration Timing When Power-On

    18. Reset A96G140/A96G148/A96A148 User’s manual Counting for configure option read start after POR is released. Internal nPOR PAD RESETB “H” LVR_RESETB External reset have not an effect on counter value for config read. BIT (for Configure) 27 28 01 02 03 04 05 …...

  • Page 225: External Resetb Input

    A96G140/A96G148/A96A148 User’s manual 18. Reset Table 42. Boot Process Description Process Description Remarks ① No Operation 0.7V to 0.9V  LSIRC (128KHz) ON  ② 1st POR level Detection About 1.1V to 1.3V ③ (LSIRC 128KHz/32)x32h Delay Slew Rate >= 0.025V/ms ...

  • Page 226: Low Voltage Reset Process

    18.4 Low voltage reset process A96G140/A96G148/A96A148 has an On-chip brown-out detection circuit (BOD) for monitoring VDD level during operation by comparing it to a fixed trigger level. Trigger level for the BOD can be selected by configuring LVRVS[3:0] bits to be 1.61V, 1.68V, 1.77V, 1.88V, 2.00V, 2.13V, 2.28V, 2.46V, 2.68V, 2.81V, 3.06V, 3.21V, 3.56V, 3.73V, 3.91V, 4.25V.

  • Page 227: Figure 122. Block Diagram Of Lvr

    A96G140/A96G148/A96A148 User’s manual 18. Reset External VDD Brown Out Detector LVRVS[3:0] RESET_BODB (BOD) LVREN LVRF CPU Write (Low Voltage Reset Flag) SCLK (System CLK) nPOR Figure 122. Block Diagram of LVR Internal 16ms RESETB t < 16ms 16ms Internal RESETB...

  • Page 228: Lvi Block Diagram

    18. Reset A96G140/A96G148/A96A148 User’s manual “H” “H” Internal nPOR “H” PAD RESETB LVR_RESETB BIT (for Config) 02 03 27 28 … … BIT (for Reset) 00 01 02 3F 40 01 02 … … … 250us X 28h = 10ms...

  • Page 229: Register Map

    A96G140/A96G148/A96A148 User’s manual 18. Reset 18.6 Register Map Table 43. Reset Operation Register Map Name Address Direction Default Description RSTFR Reset Flag Register LVRCR Low Voltage Reset Control Register LVICR Low Voltage Indicator Control Register 18.7 Reset Operation Register Description RSTFR (Reset Flag Register): E8H –...
  • Page 230 18. Reset A96G140/A96G148/A96A148 User’s manual LVRCR (Low Voltage Reset Control Register): D8H – – – LVRVS3 LVRVS2 LVRVS1 LVRVS0 LVREN – – – Initial value: 00H LVRVS[3:0] LVR Voltage Select LVRVS3 LVRVS2 LVRVS1 LVRVS0 Description 1.61V 1.68V 1.77V 1.88V 2.00V 2.13V...
  • Page 231 A96G140/A96G148/A96A148 User’s manual 18. Reset LVICR (Low Voltage Indicator Control Register): 86H – – LVIF LVIEN LVILS3 LVILS2 LVILS1 LVILS0 – – Initial value: 00H LVIF Low Voltage Indicator Flag Bit No detection Detection LVIEN LVI Enable/Disable Disable Enable LVIVS[3:0]...

  • Page 232: Memory Programming

    19. Memory programming A96G140/A96G148/A96A148 User’s manual Memory programming A96G140/A96G148/A96A148 has flash memory to which a program can be written, erased, and overwritten while mounted on the board. Serial ISP mode is supported. Flash of A96G140/A96G148/A96A148 features the followings: Flash Size : 64Kbytes ...

  • Page 233: Register Description

    A96G140/A96G148/A96A148 User’s manual 19. Memory programming 19.1.2 Register description FEMR (Flash Mode Register): 1020H FSEL ERASE PBUFF OTPE FEEN Initial value: 00H FSEL Select flash memory. Deselect flash memory Select flash memory Enable program or program verify mode with VFY...
  • Page 234 19. Memory programming A96G140/A96G148/A96A148 User’s manual FECR (Flash Control Register): 1021H EXIT1 EXIT0 WRITE READ nFERST nPBRST Initial value: 03H Enable flash bulk erase mode Disable bulk erase mode of Flash memory Enable bulk erase mode of Flash memory EXIT[1:0] Exit from program mode.
  • Page 235 A96G140/A96G148/A96A148 User’s manual 19. Memory programming FESR (Flash Status Register): 1022H PEVBSY REMAPSI REMAP- ROMINT WMODE EMODE VMODE Initial value: 80H PEVBSY Operation status flag. It is cleared automatically when operation starts. Operations are program, erase or verification Busy (Operation processing)
  • Page 236 19. Memory programming A96G140/A96G148/A96A148 User’s manual FEARM (Flash address middle Register): 1029H ARM7 ARM6 ARM5 ARM4 ARM3 ARM2 ARM1 ARM0 Initial value: 00H ARM[7:0] Flash address middle FEARH (Flash address high Register): 1028H ARH7 ARH6 ARH5 ARH4 ARH3 ARH2 ARH1...

  • Page 237: Figure 126. Read Device Internal Checksum (Full Size)

    A96G140/A96G148/A96A148 User’s manual 19. Memory programming Start OCD mode entry Write(OCD_CODE, 0xF555, 0xAA) Set checksum read mode Write(OCD_CODE, 0xFAAA, 0x55) Write(OCD_CODE, 0xF555, 0xA5) Write(OCD_XDATA, FEMR, 0x81) Set auto verify mode Write(OCD_CODE, FETR, 0x08) Write(OCD_CODE, FECR, 0x07) Busy check (FESR[7]=L) Read 24 - bit Checksum (H, M, L)

  • Page 238: Figure 127. Read Device Internal Checksum (User Define Size)

    19. Memory programming A96G140/A96G148/A96A148 User’s manual Start OCD mode entry Write(OCD_CODE, 0xF555, 0xAA) Set checksum read mode Write(OCD_CODE, 0xFAAA, 0x55) Write(OCD_CODE, 0xF555, 0xA5) Write(OCD_XDATA, FEARM,Start Address Upper) Set auto verify mode Write(OCD_XDATA, FEARL,Start Address Lower) Write(OCD_XDATA, FEARM1,End Address Upper) Write(OCD_XDATA, FEARL1,End Address Lower)

  • Page 239: Memory Map

    A96G140/A96G148/A96A148 User’s manual 19. Memory programming FETCR (Flash Time control Register): 1023H TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0 Initial value: 00H TCR[7:0] Flash Time control Program and erase time is controlled by setting FETCR register. Program and erase timer uses 10-bit counter.

  • Page 240: Serial In-System Program Mode

    19. Memory programming A96G140/A96G148/A96A148 User’s manual FFFFh pgm/ers/vfy Code Memory (PROGRAM) 0000h Figure 128. Flash Memory Map PAGE ADDRESS WORD ADDRESS Program Memory 0x3FF Page 1023 0x3F Page 1022 0x00 Page 1 Page 0 * Page buffer size: 64Bytes 0x000 Figure 129.

  • Page 241: Figure 130. The Sequence Of Page Program And Erase Of Flash Memory

    A96G140/A96G148/A96A148 User’s manual 19. Memory programming Configuration (This Configuration is just used for follow description) FEMR[4] & [1] FEMR[5] & [1] FEMR[2] FECR[6] FECR[7] ERASE&VFY PGM&VFY OTPE Master Reset Page Buffer Reset Page Buffer Load (0X00H) Page Buffer Reset Page Buffer Load...

  • Page 242: Figure 131. The Sequence Of Bulk Erase Of Flash Memory

    19. Memory programming A96G140/A96G148/A96A148 User’s manual Master Reset Page Buffer Reset Page Buffer Load Configuration Reg.<0> Set Erase Erase Latency (500us) Page Buffer Reset Configuration Reg.<0> clear Reg.<6:5> setting Cell Read Pass/Fail? Figure 131. The Sequence of Bulk Erase of Flash Memory Flash read ①...
  • Page 243 A96G140/A96G148/A96A148 User’s manual 19. Memory programming ④ Enter program/erase mode sequence. NOTE2 Write 0xAA to 0xF555. Write 0x55 to 0xFAAA. Write 0xA5 to 0xF555. NOTES: Refer to how to enter ISP mode. Command sequence to activate Flash write/erase mode. It is composed of sequentially writing data of Flash memory.
  • Page 244 19. Memory programming A96G140/A96G148/A96A148 User’s manual ⑨ Insert one NOP operation ⑩ Read FESR until PEVBSY is 1. ⑪ Repeat ② to ⑧ until all pages are erased Flash bulk erase mode ① Enable program mode. ② Reset page buffer. FEMR: 1000_0001 FECR:0000_0010 ③...
  • Page 245 A96G140/A96G148/A96A148 User’s manual 19. Memory programming ⑥ Set page address. FEARH:FEARM:FEARL=20’hx_xxxx ⑦ Set FETCR. ⑧ Start program. FECR:0000_1011 ⑨ Insert one NOP operation ⑩ Read FESR until PEVBSY is 1. Flash OTP area erase mode ① Enable program mode. ② Reset page buffer. FEMR: 1000_0001 FECR:0000_0010 ③...

  • Page 246: Mode Entrance Method Of Isp Mode

    19. Memory programming A96G140/A96G148/A96A148 User’s manual ③ Read data from Flash Flash page buffer read ① Enable program mode. ② Select page buffer. FEMR:1000_1001 ③ Read data from Flash. Summary of flash program/erase mode Table 46. Operation Mode Operation mode...

  • Page 247: Security

    19.5 Security A96G140/A96G148/A96A148 provides Lock bits which can be left un-programmed (“0”) or can be programmed (“1”) to obtain the additional features listed in table 47. The Lock bit can only be erased to “0” with the bulk erase command and a value of more than 0x40 at FETCR.
  • Page 248 19. Memory programming A96G140/A96G148/A96A148 User’s manual CONFIGURE OPTION 2: ROM Address 0001H – VAPEN – – – RSTS Initial value: 00H Code Read Protection Disable Enable Code Write Protection Disable Enable VAPEN Vector area (00H~FFH) Protection Disable Protection Enable Protection...
  • Page 249 A96G140/A96G148/A96A148 User’s manual 19. Memory programming CONFIGURE OPTION 1: ROM Address 0000H (A96G140 64K Series) – – – – PAEN PASS2 PASS1 PASS0 Initial value: 00H PAEN Enable Specific Area Write Protection Disable Protection Enable Protection PASS [2:0] Select Specific Area for Write Protection NOTE: When PAEN = ‘1’, it is applied.

  • Page 250: Development Tools

    Since the A96G140/A96G148/A96A148 has the Mentor 8051 as a core, and ROM is smaller than 64Kbytes in size, a developer can use any standard 8051 compiler from other providers.

  • Page 251: Core And Debug Tool Information

    NOTES: The A96G140/A96G148/A96A148 has the 96 series core and OCD 1 interface. The A96G140/A96G148/A96A148 can be operated with OCD II dongle too, because the OCD II dongle includes all of OCD1 functions. The 95 series core is the old version of the 96 series core.
  • Page 252 Whole interrupts: 0, 6, 12, and 18 have higher priorities. The A96G140/A96G148/A96A148 has the 96 series core and OCD 1 interface. The A96G140/A96G148/A96A148 can be operated with the OCD II dongle too, because the OCD II dongle includes all functions of the OCD1.

  • Page 253: Ocd Type Of 94/96/97 Series Core

    A96G140/A96G148/A96A148 User’s manual 20 Development tools 20.2.2 OCD type of 94/96/97 series core Cores of the 96-series use the OCD 1 for debug interfaces, while cores of the 94-series and 97-series use the OCD 2 for debug interfaces. The OCD 1 and OCD 2 use the same method on the Hardware, however, the protocols are incompatible with each other.

  • Page 254: Interrupt Priority Of 94/96/97 Series Core

    Appendix A96G140/A96G148/A96A148 User’s manual 20.2.3 Interrupt priority of 94/96/97 series core In the M8051, users can set interrupt priorities by group. The 96-series microcontroller with the basic M8051 core only supports interrupt priorities in group units. In the 94-series or 97-series microcontroller, users set interrupt priorities to have more functionalities than existing features, and can set individual priority for each interrupt source.

  • Page 255: Extended Stack Pointer Of 94/96/97 Series Core

    A96G140/A96G148/A96A148 User’s manual 20 Development tools 20.2.4 Extended stack pointer of 94/96/97 series core The M8051 uses IRAM area for Stack Pointer. However, 94-series and 97-series microcontrollers use both IRAM area and XRAM area for the Stack Pointer by configuring additional registers.

  • Page 256: Ocd (On-Chip Debugger) Emulator And Debugger

    Appendix A96G140/A96G148/A96A148 User’s manual 20.3 OCD (On-chip debugger) emulator and debugger Microcontrollers with 8051 cores have an OCD (On-Chip Debugger), a debug emulation block. The OCD is connected to a target microcontroller using two lines such as DSCL and DSDA. The DSCL is used for clock signal and the DSDA is used for bi-directional data.

  • Page 257: Figure 134. Ocd 1 And Ocd 2 Connector Pin Diagram

    ― Logic power supply pin. The OCD emulator supports ABOV’s 8051 series MCU emulation. The OCD uses two wires that are interfaces between PC and MCU, which is attached to user’s system. The OCD can read or change the value of MCU’s internal memory and I/O peripherals. In addition, the OCD controls MCU’s internal debugging logic.

  • Page 258: On-Chip Debug System

    On-chip debug system The A96G140/A96G148/A96A148 supports On-chip Debug (OCD) system. We recommend developing and debugging program with A96G1xx series. The OCD system of the A96G140/A96G148/A96A148 can be used for programming the non-volatile memories and on-chip debugging. In this section, you can find detailed descriptions for programming via the OCD interface. Table 57 introduces features of the OCD.

  • Page 259: Figure 136. On-Chip Debugging System Block Diagram

    A96G140/A96G148/A96A148 User’s manual 20 Development tools Figure 136 shows a block diagram of the OCD interface and On-chip Debug system. Figure 136. On-Chip Debugging System Block Diagram Entering debug mode While communicating through the OCD, you can enter the microcontroller into DEBUG mode by applying power to it.

  • Page 260: Two-Wire Communication Protocol

    Appendix A96G140/A96G148/A96A148 User’s manual 20.3.2 Two-wire communication protocol For the OCD interface, the semi-duplex communication protocol is used through separate two wires, the DSCL and DSDA. The DSCL is used for serial clock signal and the DSDA is used for bi-directional serial address and data.

  • Page 261: Figure 139. Data Transfer On Ocd

    A96G140/A96G148/A96A148 User’s manual 20 Development tools Packet transmission timing Figure 139 shows a timing diagram of a packet transmission using the OCD communication protocol. A start bit in the figure means start of a packet and is valid when the DSDA falls from ‘H’ to ‘L’ while External Host maintains the DSCL to ‘H’.

  • Page 262: Figure 140. Bit Transfer On Serial Bus

    Appendix A96G140/A96G148/A96A148 User’s manual Figure 140 shows a timing diagram of each bit based on state of the DSCL clock and the DSDA data. Similar to I2C signal, the DSDA data is allowed to change when the DSCL is ‘L’. If the data changes when the DSCL is ‘H’, the change means ‘START’...

  • Page 263: Figure 142. Acknowledge On Serial Bus

    A96G140/A96G148/A96A148 User’s manual 20 Development tools As shown in Figure 142, when transferring data, a receiver outputs the DSDA to ‘L’ to inform the normal reception of data. If a receiver outputs DSDA to ‘H’, it means error reception of data.

  • Page 264: Programmers

    Appendix A96G140/A96G148/A96A148 User’s manual 20.4 Programmers 20.4.1 E-PGM+ E-PGM+ USB is a single programmer. You can program A96G140/A96G148/A96A148 directly using the E-PGM+. 8 10 Figure 144. E-PGM+ (Single Writer) and Pinouts 20.4.2 OCD emulator OCD emulator allows users to write code on the device too, since OCD debugger supports In System...

  • Page 265: Gang Programmer

    A96G140/A96G148/A96A148 User’s manual 20 Development tools 20.4.3 Gang programmer E-Gang4 and E-Gang6 allow users to program multiple devices simultaneously. They can be run not only in PC controlled mode but also in standalone mode without the PC control. USB interface is available, and it is easy to connect to the handler.

  • Page 266: Flash Programming

    20.5 Flash programming Program memory for A96G140/A96G148/A96A148 is Flash type. This Flash ROM is accessed through four pins such as DSCL, DSDA, VDD and VSS in serial data format. For detailed information about the Flash memory programming, please refer to 오류! 참조 원본을 찾을 수 없습니다.. 오류! 참조 원본...

  • Page 267: Connection Of Transmission

    A96G140/A96G148/A96A148 User’s manual 20 Development tools 20.6 Connection of transmission OCD’s two-wire communication interfaces use the Open-Drain Method (Wire-AND Bi-Directional I/O). Normally, it is recommended to place a resister greater than 4.7kΩ for the DSCL and DSDA respectively. The capacitive load is recommended to be less than 100pF. Outside these ranges, because the communication may not be accomplished, the connection to Debug mode is not guaranteed.

  • Page 268: Circuit Design Guide

    Appendix A96G140/A96G148/A96A148 User’s manual 20.7 Circuit design guide To program Flash memory, programming tools require 4 signal lines, DSCL, DSDA, VDD, and VSS. When designing a PCB circuit, you should consider these 4 signal lines for on-board programming. In addition, you need to be careful when designing the related circuit of these signal pins, because rising/falling timing of the DSCL and DSDA is very important for proper programming.

  • Page 269: Figure 147. Pcb Design Guide For On-Board Programming

    A96G140/A96G148/A96A148 User’s manual 20 Development tools E-PGM+ , E-GANG4 , E-GANG6 VDD VSS DSCL DSDA Four-wire Interface R1 (2k ~ 5k ) P01/DSCL(I) To application circuit R2 (2k ~ 5k ) P00/DSDA(I/O) To application circuit NOTES: In on-board programming mode, very high-speed signal will be provided to pin DSCL and DSDA. And it will cause some damages to the application circuits connected to DSCL or DSDA port if the application circuit is designed as high-speed response such as relay control circuit.

  • Page 270: Appendix

    Appendix A96G140/A96G148/A96A148 User’s manual Appendix Instruction table Instructions are either1, 2 or 3bytes long as listed in the ‘Bytes’ column below. Each instruction takes either 1, 2 or 4 machine cycles to execute as listed in the following table. 1 machine cycle comprises 2 system clock cycles.
  • Page 271 A96G140/A96G148/A96A148 User’s manual Appendix Table 59. Instruction Table (continued) LOGICAL Mnemonic Description Bytes Cycles Hex code ANL A,Rn AND register to A 58-5F ANL A,dir AND direct byte to A ANL A,@Ri AND indirect memory to A 56-57 ANL A,#data...
  • Page 272 Appendix A96G140/A96G148/A96A148 User’s manual Table 59. Instruction Table (continued) DATA TRANSFER Mnemonic Description Bytes Cycles Hex code MOV A,Rn Move register to A E8-EF MOV A,dir Move direct byte to A MOV A,@Ri Move indirect memory to A E6-E7 MOV A,#data...
  • Page 273 A96G140/A96G148/A96A148 User’s manual Appendix Table 59. Instruction Table (continued) BOOLEAN Mnemonic Description Bytes Cycles Hex code CLR C Clear carry CLR bit Clear direct bit SETB C Set carry SETB bit Set direct bit CPL C Complement carry CPL bit...
  • Page 274 Appendix A96G140/A96G148/A96A148 User’s manual Table 59. Instruction Table (continued) BRANCHING Mnemonic Description Bytes Cycles Hex code ACALL addr 11 Absolute jump to subroutine 11→F1 LCALL addr 16 Long jump to subroutine Return from subroutine RETI Return from interrupt AJMP addr 11 Absolute jump unconditional 01→E1...
  • Page 275 A96G140/A96G148/A96A148 User’s manual Appendix Table 59. Instruction Table (continued) MISCELLANEOUS Mnemonic Description Bytes Cycles Hex code No operation ADDITIONAL INSTRUCTIONS (selected through EO[7:4]) Mnemonic Description Bytes Cycles Hex code MOVC M8051W/M8051EW-specific instruction @(DPTR++),A supporting software download into program memory TRAP...

  • Page 276: Revision History

    USART on page 15. Corrected device name from A96G140/A96G148KL A96G140/A96G148KN on page 19. Corrected the internal frequency from 16MHz to 32MHz in 7.6 High Internal RC Oscillator Characteristics on page 246. Added additional description of UCTRL4 on page229. 2019.10.14 1.11 Deleted Special Test Mark (V, High voltage stressed) on page 284 Changed the minimum voltage of crystal OSC from 2.0V to 2.2V on page...
  • Page 277 A96G140/A96G148/A96A148 User’s manual Revision history characteristics. Corrected the minimum A/D Conversion time to 7.5us 2020.08.31 1.23 Advanced Flash Endurance times from 10,000 to 30,000. 2020.09.28 1.24 Updated the initial value in Table 5. SFR Map. Updated a typo in Figure 116. Fast VDD Rising Time and Figure 117.
  • Page 278 ABOV Semiconductor ("ABOV") reserves the right to make changes, corrections, enhancements, modifications, and improvements to ABOV products and/or to this document at any time without notice. ABOV does not give warranties as to the accuracy or completeness of the information included herein. Purchasers should obtain the latest relevant information of ABOV products before placing orders.

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