Abov MC96F6432 Series User Manual
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Abov MC96F6432 Series User Manual

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MC96F6432
ABOV SEMICONDUCTOR Co., Ltd.
8-BIT MICROCONTROLLERS
MC96F6432
User's Manual (Ver. 2.9)
June 22, 2018 Ver. 2.9
1

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  • Page 1 MC96F6432 ABOV SEMICONDUCTOR Co., Ltd. 8-BIT MICROCONTROLLERS MC96F6432 User’s Manual (Ver. 2.9) June 22, 2018 Ver. 2.9...
  • Page 2 MC96F6432 REVISION HISTORY VERSION 0.0 (January 14, 2011) VERSION 1.0 (June 27, 2011) Change ‘Typ/Max’ to “LVR/LVI level” in LVR/LVI electrical characteristics. Change ‘600/1200/2000 kΩ (Min/Typ/Max)’ to “RX1” in DC electrical characteristics. Change ‘3/6/9 kHz (Min/Typ/Max)’ to “f ” in INTERNAL WATCH-DOG RC OSCILLATION characteristics. WDTRC Remove WDTRC Current Max value at INTERNAL WATCH-DOG RC OSCILLATION characteristics.
  • Page 3 MC96F6432 VERSION 1.7 (November 19, 2013) Retype a typo on ‘P5FSR register’s contents’. VERSION 1.8 (February 26, 2014) Change a package diagram, “44-Pin MQFP-1010”. VERSION 1.9 (March 21, 2014) AVREF range changed from 1.8V~VDD to 2.7V~VDD Figure 10.3 and Figure 10.6 modified Appendix 1 “DJNZ Rn,rel”...
  • Page 4 Additional information of this manual may be served by ABOV Semiconductor offices in Korea or Distributors. ABOV Semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, ABOV Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.

  • Page 5: Table Of Contents

    MC96F6432 Table of Contents 1. Overview ................................13 1.1 Description ..............................13 1.2 Features ..............................14 1.3 Ordering Information ..........................15 1.4 Development Tools ............................ 16 2. Block Diagram ..............................19 3. Pin Assignment ..............................20 4. Package Diagram .............................. 24 5.
  • Page 6 MC96F6432 9.8 P5 Port ............................... 83 9.9 Port Function .............................. 84 10. Interrupt Controller ............................93 10.1 Overview ..............................93 10.2 External Interrupt ............................94 10.3 Block Diagram ............................95 10.4 Interrupt Vector Table ..........................96 10.5 Interrupt Sequence ........................... 96 10.6 Effective Timing after Controlling Interrupt Bit ..................
  • Page 7 MC96F6432 16. Configure Option ............................317 16.1 Configure Option Control ........................317 17. APPENDIX ..............................318 List of Figures Figure 1.1 Debugger(OCD1/OCD2) and Pin description ................ 16 Figure 1.2 E-PGM+(Single writer) ......................17 Figure 1.3 E-GANG4 and E-GANG6 (for Mass Production) ..............18 Figure 2.1 Block Diagram ........................
  • Page 8 MC96F6432 Figure 10.2 Block Diagram of Interrupt ....................95 Figure 10.3 Interrupt Sequence Flow ...................... 97 Figure 10.4 Effective Timing of Interrupt Enable Register..............98 Figure 10.5 Effective Timing of Interrupt Flag Register ................98 Figure 10.6 Effective Timing of Multi-Interrupt ..................99 Figure 10.7 Interrupt Response Timing Diagram ..................
  • Page 9 MC96F6432 Figure 11.41 Example of PWM External Synchronization with BLNK Input .......... 163 Figure 11.42 Example of Force Drive All Channel with A-ch ..............164 Figure 11.43 Example of Force Drive 6-ch Mode ................. 165 Figure 11.44 Example of PWM Delay ....................167 Figure 11.45 Two 8-Bit Timer 3, 4 Block Diagram ................
  • Page 10 MC96F6432 Figure 11.90 Data Transfer on the I2C-Bus (USI1) ................248 Figure 11.91 Acknowledge on the I2C-Bus (USI1) ................249 Figure 11.92 Clock Synchronization during Arbitration Procedure (USI1) ..........250 Figure 11.93 Arbitration Procedure of Two Masters (USI1) ..............250 Figure 11.94 Formats and States in the Master Transmitter Mode (USI1)..........
  • Page 11 MC96F6432 Table 7-1 Absolute Maximum Ratings ....................36 Table 7-2 Recommended Operating Conditions ..................36 Table 7-3 A/D Converter Characteristics ....................37 Table 7-4 Power-on Reset Characteristics ..................... 37 Table 7-5 LVR and LVI Characteristics ....................38 Table 7-6 High Internal RC Oscillator Characteristics ................39 Table 7-7 Internal WDTRC Oscillator Characteristics ................
  • Page 12 MC96F6432 Table 11-23 CPOL1 Functionality ......................243 Table 11-24 USI1 Register Map ......................260 Table 11-25 Examples of USI0BD and USI1BD Settings for Commonly Used Oscillator Frequencies 269 Table 11-26 LCD Register Map ......................278 Table 11-27 LCD Frame Frequency ..................... 280 Table 12-1 Peripheral Operation during Power Down Mode ..............

  • Page 13: Overview

    MC96F6432 MC96F6432 CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH 12-BIT A/D CONVERTER 1. Overview 1.1 Description The MC96F6432 is an advanced CMOS 8-bit microcontroller with 32k bytes of FLASH. This is powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications. This provides the following features : 32 Kbytes of FLASH, 256 bytes of IRAM, 768 bytes of XRAM , general purpose I/O, basic interval timer, watchdog timer, 8/16-bit timer/counter, 16-bit PPG output, 8-bit PWM output, 10-bit PWM output, watch timer, buzzer driving port, SPI, USI, 12-bit A/D converter, LCD driver, on-chip POR,...

  • Page 14: Features

    MC96F6432 1.2 Features • CPU • Low Voltage Reset - 8-bit CISC Core (8051 Compatible) - 14 level detect (1.60V/ 2.00V/ 2.10V/ 2.20V/ 2.32V/ 2.44V/ 2.59V/ 2.75V/ 2.93V/ 3.14V/ • ROM (FLASH) Capacity 3.38V/ 3.67V/ 4.00V/ 4.40V) - 32 Kbytes •...

  • Page 15: Ordering Information

    MC96F6432 1.3 Ordering Information Table 1-1 Ordering Information of MC96F6432 Device name ROM size IRAM size XRAM size Package MC96F6432L 48 LQFP-0707 MC96F6432Q 44 MQFP MC96F6332L 32 Kbytes FLASH 256 bytes 768 bytes 32 LQFP MC96F6332D 32 SOP MC96F6332M 28 SOP June 22, 2018 Ver.

  • Page 16: Development Tools

    8051 compiler. 1.4.2 OCD emulator and debugger The OCD (On Chip Debug) emulator supports ABOV Semiconductor’s 8051 series MCU emulation. The OCD interface uses two-wire interfacing between PC and MCU which is attached to user’s system. The OCD can read or change the value of MCU internal memory and I/O peripherals.

  • Page 17: Figure 1.2 E-Pgm+(Single Writer)

    MC96F6432 1.4.3 Programmer Single programmer: E-PGM+ : It programs MCU device directly. Figure 1.2 E-PGM+(Single writer) June 22, 2018 Ver. 2.9...

  • Page 18: Figure 1.3 E-Gang4 And E-Gang6 (For Mass Production)

    MC96F6432 OCD emulator: It can write code in MCU device too, because OCD debugging supports ISP (In System Programming). It does not require additional H/W, except developer’s target system. Gang programmer: E-GANG4 and E-GANG6 It can run PC controlled mode. It can run standalone without PC control too.

  • Page 19: Block Diagram

    MC96F6432 2. Block Diagram DSDA DSCL Low Voltage AN0-AN5/P02-P07 12 – Bit Indicator AN6-AN13/P17-P10 A/D Converter AN14-AN15/P20-P21 On-Chip Debug AVREF/P02 Buzzer BUZO/P13/SEG17/AN10/EC1 T0O/PWM0O/P53 8 – Bit Timer 0 EINT10/P54 MOSI2/P14 EC0/P52 M8051 Core MISO2/P15 SPI2 SCK2/P16 SS2/P17 T1O/PWM1O/P12 16 – Bit Timer 1 EINT11/P12 EC1/P13 TXD0/P41...

  • Page 20: Pin Assignment

    MC96F6432 3. Pin Assignment P55/RESETB P04/SEG25/AN2/EINT2/PWM4BA P40/VLC3/RXD0/SCL0/MISO0 P05/SEG24/AN3/EINT3/PWM4BB P41/VLC2/TXD0/SDA0/MOSI0 P06/SEG23/AN4/EINT4/PWM4CA P42/VLC1/SCK0 P43/VLC0/SS0 P07/SEG22/AN5/EINT5/PWM4CB MC96F6432L P37/COM0 P17/SEG21/AN6/EINT6/SS2 P36/COM1 (48LQFP-0707) P16/SEG20/AN7/EINT7/SCK2 P35/COM2/SEG0 P15/SEG19/AN8/MISO2 P14/SEG18/AN9/MOSI2 P34/COM3/SEG1 P13/SEG17/AN10/EC1/BUZO P33/COM4/SEG2 P12/SEG16/AN11/EINT11/T1O/PWM1O P32/COM5/SEG3 P11/SEG15/AN12/EINT12/T2O/PWM2O Figure 3.1 MC96F6432L 48LQFP-0707 Pin Assignment NOTE) 1. On On-Chip Debugging, ISP uses P0[1:0] pin as DSDA, DSCL. 2.

  • Page 21: Figure 3.2 Mc96F6432Q 44Mqfp-1010 Pin Assignment

    MC96F6432 P55/RESETB P04/SEG25/AN2/EINT2/PWM4BA P40/VLC3/RXD0/SCL0/MISO0 P05/SEG24/AN3/EINT3/PWM4BB P41/VLC2/TXD0/SDA0/MOSI0 P06/SEG23/AN4/EINT4/PWM4CA P42/VLC1/SCK0 P07/SEG22/AN5/EINT5/PWM4CB MC96F6432Q P43/VLC0/SS0 P17/SEG21/AN6/EINT6/SS2 P37/COM0 P16/SEG20/AN7/EINT7/SCK2 (44MQFP-1010) P36/COM1 P15/SEG19/AN8/MISO2 P35/COM2/SEG0 P14/SEG18/AN9/MOSI2 P34/COM3/SEG1 P13/SEG17/AN10/EC1/BUZO P33/COM4/SEG2 P12/SEG16/AN11/EINT11/T1O/PWM1O P32/COM5/SEG3 P11/SEG15/AN12/EINT12/T2O/PWM2O Figure 3.2 MC96F6432Q 44MQFP-1010 Pin Assignment NOTE) On On-Chip Debugging, ISP uses P0[1:0] pin as DSDA, DSCL. June 22, 2018 Ver.

  • Page 22: Figure 3.3 Mc96F6332L 32Lqfp Pin Assignment

    MC96F6432 P53/SXIN/T0O/PWM0O P03/SEG26/AN1/EINT1/PWM4AB P54/SXOUT/EINT10 P04/SEG25/AN2/EINT2/PWM4BA P55/RESETB P05/SEG24/AN3/EINT3/PWM4BB P40/VLC3/RXD0/SCL0/MISO0 P06/SEG23/AN4/EINT4/PWM4CA MC96F6332L P41/VLC2/TXD0/SDA0/MOSI0 P07/SEG22/AN5/EINT5/PWM4CB (32-LQFP) P42/VLC1/SCK0 P13/SEG17/AN10/EC1/BUZO P33/COM4/SEG2 P12/SEG16/AN11/EINT11/T1O/PWM1O P32/COM5/SEG3 P11/SEG15/AN12/EINT12/T2O/PWM2O Figure 3.3 MC96F6332L 32LQFP Pin Assignment NOTES) 1. On On-Chip Debugging, ISP uses P0[1:0] pin as DSDA, DSCL. 2. The P14-P17, P23-P25, P34-P37 and P43 pins should be selected as a push-pull output or an input with pull-up resistor by software control when the 32-pin package is used.

  • Page 23: Figure 3.4 Mc96F6332D 32Sop Pin Assignment

    MC96F6432 P50/XOUT P00/EC3/DSDA P51/XIN P01/T3O/DSCL P52/EINT8/EC0/BLNK P02/AN0/AVREF/EINT0/T4O/PWM4AA P53/SXIN/T0O/PWM0O P03/SEG26/AN1/EINT1/PWM4AB P54/SXOUT/EINT10 P04/SEG25/AN2/EINT2/PWM4BA P55/RESETB P05/SEG24/AN3/EINT3/PWM4BB P40/VLC3/RXD0/SCL0/MISO0 P06/SEG23/AN4/EINT4/PWM4CA P41/VLC2/TXD0/SDA0/MOSI0 P07/SEG22/AN5/EINT5/PWM4CB P42/VLC1/SCK0 P13/SEG17/AN10/EC1/BUZO P33/COM4/SEG2 P12/SEG16/AN11/EINT11/T1O/PWM1O P32/COM5/SEG3 P11/SEG15/AN12/EINT12/T2O/PWM2O P31/COM6/SEG4 P10/SEG14/AN13/RXD1/SCL1/MISO1 P30/COM7/SEG5 P20/SEG13/AN14/TXD1/SDA1/MOSI1 P27/SEG6 P21/SEG12/AN15/SCK1 P26/SEG7 P22/SEG11/SS1 Figure 3.4 MC96F6332D 32SOP Pin Assignment NOTES) 1. On On-Chip Debugging, ISP uses P0[1:0] pin as DSDA, DSCL. 2.

  • Page 24: Package Diagram

    MC96F6432 4. Package Diagram Figure 4.1 48-Pin LQFP-0707 Package June 22, 2018 Ver. 2.9...

  • Page 25: Figure 4.2 44-Pin Mqfp Package

    MC96F6432 Figure 4.2 44-Pin MQFP Package June 22, 2018 Ver. 2.9...

  • Page 26: Figure 4.3 32-Pin Lqfp Package

    MC96F6432 Figure 4.3 32-Pin LQFP Package June 22, 2018 Ver. 2.9...

  • Page 27: Figure 4.4 32-Pin Sop Package

    MC96F6432 Figure 4.4 32-Pin SOP Package June 22, 2018 Ver. 2.9...

  • Page 28: Figure 4.5 28-Pin Sop Package

    MC96F6432 Figure 4.5 28-Pin SOP Package June 22, 2018 Ver. 2.9...

  • Page 29: Pin Description

    MC96F6432 5. Pin Description Table 5-1 Normal Pin Description Function @RESET Shared with Name Port 0 is a bit-programmable I/O port which can Input EC3/DSDA be configured as a schmitt-trigger input, a T3O/DSCL push-pull output, or an open-drain output. AN0/AVREF/EINT0/T4O/PWM4AA A pull-up resistor can be specified in 1-bit unit.
  • Page 30 MC96F6432 Table 5-1 Normal Pin Description (Continued) Function @RESET Shared with Name Port 5 is a bit-programmable I/O port which Input XOUT can be configured as a schmitt-trigger input or a push-pull output. EINT8/EC0/BLNK A pull-up resistor can be specified in 1-bit SXIN/T0O/PWM0O unit.
  • Page 31 MC96F6432 Table 5-1 Normal Pin Description (Continued) Function @RESET Shared with Name BUZO Buzzer signal output Input P13/SEG17/AN10/EC1 SCK0 Serial 0 clock input/output Input P42/VLC1 SCK1 Serial 1 clock input/output Input P21/SEG12/AN15 SCK2 Serial 2 clock input/output Input P16/SEG20/AN7/EINT7 MOSI0 SPI 0 master output, slave input Input P41/VLC2/TXD0/SDA0...
  • Page 32 MC96F6432 Table 5-1 Normal Pin Description (Continued) Function @RESET Shared with Name VLC0 LCD bias voltage pins Input P43/SS0 VLC1 P42/SCK0 VLC2 P41/TXD0/SDA0/MOSI0 VLC3 P40/RXD0/SCL0/MISO0 COM0– LCD common signal outputs Input P37–P36 COM1 COM2– P35–P34/SEG0–SEG1 COM3 COM4– P33–P30/SEG2–SEG5 COM7 SEG0– LCD segment signal outputs Input P35–P34/COM2–COM3...
  • Page 33 MC96F6432 Table 5-1 Normal Pin Description (Continued) Function @RESET Shared with Name System reset pin with a pull-up resistor when it Input RESETB is selected as the RESETB by CONFIGURE OPTION (NOTE4,5) DSDA On chip debugger data input/output Input P00/EC3 (NOTE4,5) DSCL On chip debugger clock input...

  • Page 34: Port Structures

    MC96F6432 6. Port Structures 6.1 General Purpose I/O Port Level Shift (1.8V to ExtVDD) Level Shift (ExtVDD to 1.8V) PULL-UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE SUB-FUNC DIRECTION DIRECTION REGISTER CMOS or Schmitt Level Input PORTx INPUT or SUB-FUNC DATA INPUT ANALOG CHANNEL...

  • Page 35: External Interrupt I/O Port

    MC96F6432 6.2 External Interrupt I/O Port Level Shift (1.8V to ExtVDD) Level Shift (ExtVDD to 1.8V) PULL-UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE SUB-FUNC DIRECTION DIRECTION REGISTER EXTERNAL INTERRUPT POLARITY REG. INTERRUPT ENABLE FLAG CMOS or CLEAR Schmitt Level Input...

  • Page 36: Electrical Characteristics

    MC96F6432 7. Electrical Characteristics 7.1 Absolute Maximum Ratings Table 7-1 Absolute Maximum Ratings Parameter Symbol Rating Unit Note – Supply Voltage -0.3 ~ +6.5 -0.3 ~ VDD+0.3 Voltage on any pin with respect to VSS -0.3 ~ VDD+0.3 Maximum current output sourced by (I I/O pin) Normal Voltage Pin ∑...

  • Page 37: A/D Converter Characteristics

    MC96F6432 7.3 A/D Converter Characteristics Table 7-3 A/D Converter Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V) Parameter Symbol Conditions Unit – – –- – Resolution – – Integral Non-Linear ±4 Differential Non- – – ±1 AVREF= 2.7V – 5.5V Linearity fx= 8MHz –...

  • Page 38: Low Voltage Reset And Low Voltage Indicator Characteristics

    MC96F6432 7.5 Low Voltage Reset and Low Voltage Indicator Characteristics Table 7-5 LVR and LVI Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V) Parameter Symbol Conditions Unit – 1.60 1.75 1.85 2.00 2.15 1.95 2.10 2.25 2.05 2.20 2.35 2.17...

  • Page 39: High Internal Rc Oscillator Characteristics

    MC96F6432 7.6 High Internal RC Oscillator Characteristics Table 7-6 High Internal RC Oscillator Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V) Parameter Symbol Conditions Unit = 2.0 – 5.5 V – – Frequency = 0°C to +50°C ±1 –...

  • Page 40: Lcd Voltage Characteristics

    MC96F6432 7.8 LCD Voltage Characteristics Table 7-8 LCD Voltage Characteristics = -40°C ~ +85°C, VDD= 2.0V ~ 5.5V, VSS= 0V) Parameter Symbol Conditions Unit LCD contrast disabled, 1/4 bias Typx0.95 Typx1.05 LCDCCR=00H VDDx16/31 LCDCCR=01H VDDx16/30 LCDCCR=02H VDDx16/29 LCDCCR=03H VDDx16/28 LCDCCR=04H VDDx16/27 LCDCCR=05H VDDx16/26...

  • Page 41: Dc Characteristics

    MC96F6432 7.9 DC Characteristics Table 7-9 DC Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V, f = 12MHz) Parameter Symbol Conditions Unit – P0, P1, P5, RESETB 0.8VDD Input High Voltage – All input pins except V 0.7VDD –...
  • Page 42 MC96F6432 Table 7-9 DC Characteristics (Continued) = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V, f = 12MHz) Parameter Symbol Condition Unit – = 12MHz, VDD= 5V±10% – = 10MHz, VDD= 3V±10% (RUN) – = 16MHz, VDD= 5V±10% – = 12MHz, VDD= 5V±10% –...

  • Page 43: Ac Characteristics

    MC96F6432 7.10 AC Characteristics Table 7-10 AC Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) Parameter Symbol Conditions Unit – – RESETB input low width Input, VDD= 5V – – Interrupt input high, low width All interrupt, VDD= 5V External Counter Input High, ECn, V = 5 V...

  • Page 44: Spi0/1/2 Characteristics

    MC96F6432 7.11 SPI0/1/2 Characteristics Table 7-11 SPI0/1/2 Characteristics = -40°C – +85°C, VDD= 1.8V – 5.5V) Parameter Symbol Conditions Unit – – Output Clock Pulse Period Internal SCK source – – Input Clock Pulse Period External SCK source Output Clock High, Low –...

  • Page 45: Uart0/1 Characteristics

    MC96F6432 7.12 UART0/1 Characteristics Table 7-12 UART0/1 Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, f =11.1MHz) Parameter Symbol Unit Serial port clock cycle time 1250 x 16 1650 – Output data setup to clock rising edge x 13 –...

  • Page 46: I2C0/1 Characteristics

    MC96F6432 7.13 I2C0/1 Characteristics Table 7-13 I2C0/1 Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) Standard Mode High-Speed Mode Parameter Symbol Unit Clock frequency – – Clock High Pulse Width SCLH – – Clock Low Pulse Width SCLL – –...

  • Page 47: Data Retention Voltage In Stop Mode

    MC96F6432 7.14 Data Retention Voltage in Stop Mode Table 7-14 Data Retention Voltage in Stop Mode = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) Parameter Symbol Conditions Unit – – Data retention supply voltage DDDR VDDR= 1.8V, – – Data retention supply current DDDR = 25°C), Stop mode Idle Mode...

  • Page 48: Internal Flash Rom Characteristics

    MC96F6432 7.15 Internal Flash Rom Characteristics Table 7-15 Internal Flash Rom Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V) Parameter Symbol Condition Unit – – Sector Write Time – – Sector Erase Time – – Code Write Protection Time –...

  • Page 49: Main Clock Oscillator Characteristics

    MC96F6432 7.17 Main Clock Oscillator Characteristics Table 7-17 Main Clock Oscillator Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) Oscillator Parameter Condition Unit 1.8V – 5.5V – 2.7V – 5.5V – Crystal Main oscillation frequency 10.0 3.0V – 5.5V –...

  • Page 50: Sub Clock Oscillator Characteristics

    MC96F6432 7.18 Sub Clock Oscillator Characteristics Table 7-18 Sub Clock Oscillator Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) Oscillator Parameter Condition Unit Crystal Sub oscillation frequency 32.768 1.8V – 5.5V – External Clock SXIN input frequency SXIN SXOUT Figure 7.10 Crystal Oscillator SXIN SXOUT...

  • Page 51: Main Oscillation Stabilization Characteristics

    MC96F6432 7.19 Main Oscillation Stabilization Characteristics Table 7-19 Main Oscillation Stabilization Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V) Oscillator Parameter Unit fx > 1MHz – – Crystal Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage –...

  • Page 52: Operating Voltage Range

    MC96F6432 7.21 Operating Voltage Range =0.4 to 12MHz) =32 to 38kHz) 12.0MHz 32.768kHz 10.0MHz 4.2MHz 0.4MHz Supply voltage (V) Supply voltage (V) Figure 7.14 Operating Voltage Range June 22, 2018 Ver. 2.9...

  • Page 53: Recommended Circuit And Layout

    MC96F6432 7.22 Recommended Circuit and Layout This 0.1uF capacitor should be within 1cm from the VDD pin of MCU on the VDD VCC PCB layout. DC Power 0.1uF 0.1uF The MCU power line (VDD and VSS) should be separated from the high- current part at a DC power node on High-Current Part the PCB layout.

  • Page 54: Recommended Circuit And Layout With Smps Power

    MC96F6432 7.23 Recommended Circuit and Layout with SMPS Power SMPS Side MCU Side SMPS 1. The C1 capacitor is to flatten out the voltage of the SMPS power, VCC. √ Recommended C1: 470uF/25V more. 2. The R1 and C2 are the RC filter for VDD and suppress the ripple of VCC. √...

  • Page 55: Typical Characteristics

    MC96F6432 7.24 Typical Characteristics These graphs and tables provided in this section are only for design guidance and are not tested or guaranteed. In graphs or tables some data are out of specified operating range (e.g. out of specified VDD range). This is only for information and devices are guaranteed to operate properly only within the specified range.

  • Page 56: Figure 7.19 Sub Run (Idd3) Current

    MC96F6432 160.0 140.0 120.0 100.0 -40℃ 80.0 +25℃ 60.0 +85℃ 40.0 20.0 2.7V 3.0V 3.3V 4.5V 5.0V 5.5V Figure 7.19 SUB RUN (IDD3) Current 30.00 25.00 20.00 -40℃ 15.00 +25℃ +85℃ 10.00 5.00 0.00 2.7V 3.0V 3.3V 4.5V 5.0V 5.5V Figure 7.20 SUB IDLE (IDD4) Current June 22, 2018 Ver.

  • Page 57: Figure 7.21 Stop (Idd5) Current

    MC96F6432 5.00 4.00 3.00 -40℃ +25℃ 2.00 +85℃ 1.00 0.00 2.7V 3.0V 3.3V 4.5V 5.0V 5.5V Figure 7.21 STOP (IDD5) Current June 22, 2018 Ver. 2.9...

  • Page 58: Memory

    MC96F6432 8. Memory The MC96F6432 addresses two separate address memory stores: Program memory and Data memory. The logical separation of Program and Data memory allows Data memory to be accessed by 8-bit addresses, which makes the 8-bit CPU access the data memory more rapidly. Nevertheless, 16-bit Data memory addresses can also be generated through the DPTR register.

  • Page 59: Figure 8.1 Program Memory

    MC96F6432 FFFFH 7FFFH 32 Kbytes 0000H Figure 8.1 Program Memory 32 Kbytes Including Interrupt Vector Region June 22, 2018 Ver. 2.9...

  • Page 60: Data Memory

    MC96F6432 8.2 Data Memory Figure 8-2 shows the internal data memory space available. Upper 128 Bytes Special Function Registers Internal RAM 128 Bytes (Indirect Addressing) (Direct Addressing) Lower 128 Bytes Internal RAM (Direct or Indirect Addressing) Figure 8.2 Data Memory Map The internal data memory space is divided into three blocks, which are generally referred to as the lower 128 bytes, upper 128 bytes, and SFR space.

  • Page 61: Figure 8.3 Lower 128 Bytes Ram

    MC96F6432 7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70 6F 6E 6D 6C 6B 6A 69 68 67 66 65 64 63 62 61 60 5F 5E 5D 5C 5B 5A 59 58 General Purpose 80 Bytes Register...

  • Page 62: Xram Memory

    MC96F6432 8.3 XRAM Memory MC96F6432 has 768 bytes XRAM. This area has no relation with RAM/FLASH. It can be read and written to through SFR with 8-bit unit. 107FH Extended Special Function Registers 128 Bytes (Indirect Addressing) 1000H Not used 02FFH External RAM 768 Bytes...

  • Page 63: Sfr Map

    MC96F6432 8.4 SFR Map 8.4.1 SFR Map Summary Table 8-1 SFR Map Summary Reserved M8051 compatible 00H/8H 01H/9H 02H/0AH 03H/0BH 04H/0CH 05H/0DH 06H/0EH 07H/0FH – 0F8H FSADRH FSADRM FSADRL FIDR FMCR P5FSR 0F0H USI1ST1 USI1ST2 USI1BD USI1SDHR USI1DR USI1SCLR USI1SCHR 0E8H RSTFR USI1CR1...

  • Page 64: Table 8-2 Sfr Map Summary

    MC96F6432 Table 8-2 SFR Map Summary Reserved 00H/8H 01H/9H 02H/0AH 03H/0BH 04H/0CH 05H/0DH 06H/0EH 07H/0FH – – – – – – – – 1078H – – – – – – – – 1070H – – – – – – – –...

  • Page 65: Table 8-3 Sfr Map

    MC96F6432 8.4.2 SFR Map Table 8-3 SFR Map @Reset Address Function Symbol P0 Data Register Stack Pointer Data Pointer Register Low Data Pointer Register High Data Pointer Register Low 1 DPL1 Data Pointer Register High 1 DPH1 – – Low Voltage Indicator Control Register LVICR –...
  • Page 66 MC96F6432 Table 8-2 SFR Map (Continued) @Reset Address Function Symbol – – – – P4 Data Register P0 Direction Register P0IO – – – – Extended Operation Register – – – – P4 Pull-up Resistor Selection Register P4PU External Interrupt Polarity 0 Low Register EIPOL0L External Interrupt Polarity 0 High Register EIPOL0H...
  • Page 67 MC96F6432 Table 8-2 SFR Map (Continued) @Reset Address Function Symbol External Interrupt Flag 0 Register EIFLAG0 P3 Direction Register P3IO – – Timer 2 Control Low Register T2CRL – – – – Timer 2 Control High Register T2CRH Timer 2 A Data Low Register T2ADRL Timer 2 A Data High Register T2ADRH...
  • Page 68 MC96F6432 Table 8-2 SFR Map (Continued) @Reset Address Function Symbol Accumulator Register – USI0 Status Register 1 USI0ST1 USI0 Status Register 2 USI0ST2 USI0 Baud Rate Generation Register USI0BD USI0 SDA Hold Time Register USI0SHDR USI0 Data Register USI0DR USI0 SCL Low Period Register USI0SCLR USI0 SCL High Period Register USI0SCHR...
  • Page 69 MC96F6432 Table 8-2 SFR Map (Continued) @Reset Address Function Symbol – 1000H Timer 3 Control Register T3CR Timer 3 Counter Register T3CNT 1001H Timer 3 Data Register T3DR Timer 3 Capture Data Register T3CAPR 1002H Timer 4 Control Register T4CR 1003H Timer 4 PWM Control Register 1 T4PCR1...
  • Page 70 MC96F6432 8.4.3 Compiler Compatible SFR ACC (Accumulator Register) : E0H Initial value : 00H Accumulator B (B Register) : F0H Initial value : 00H B Register SP (Stack Pointer) : 81H Initial value : 07H Stack Pointer DPL (Data Pointer Register Low) : 82H Initial value : 00H Data Pointer Low DPH (Data Pointer Register High) : 83H...
  • Page 71 MC96F6432 DPL1 (Data Pointer Register Low 1) : 84H DPL1 Initial value : 00H DPL1 Data Pointer Low 1 DPH1 (Data Pointer Register High 1) : 85H DPH1 Initial value : 00H DPH1 Data Pointer High 1 PSW (Program Status Word Register) : D0H Initial value : 00H Carry Flag Auxiliary Carry Flag...

  • Page 72: I/O Ports

    MC96F6432 9. I/O Ports 9.1 I/O Ports The MC96F6432 has ten groups of I/O ports (P0 ~ P5). Each port can be easily configured by software as I/O pin, internal pull up and open-drain pin to meet various system configurations and design requirements. Also P0 includes function that can generate interrupt according to change of state of the pin.

  • Page 73: Table 9-1 Port Register Map

    MC96F6432 9.2.7 Register Map Table 9-1 Port Register Map Name Address Default Description P0 Data Register P0IO P0 Direction Register P0PU P0 Pull-up Resistor Selection Register P0OD P0 Open-drain Selection Register P0DB P0 Debounce Enable Register P0FSRH P0 Function Selection High Register P0FSRL P0 Function Selection Low Register P1 Data Register...

  • Page 74: P0 Port

    MC96F6432 9.3 P0 Port 9.3.1 P0 Port Description P0 is 8-bit I/O port. P0 control registers consist of P0 data register (P0), P0 direction register (P0IO), debounce enable register (P0DB), P0 pull-up resistor selection register (P0PU), and P0 open-drain selection register (P0OD).
  • Page 75 MC96F6432 P0OD (P0 Open-drain Selection Register) : 91H P07OD P06OD P05OD P04OD P03OD P02OD P01OD P00OD Initial value : 00H P0OD[7:0] Configure Open-drain of P0 Port Push-pull output Open-drain output P0DB (P0 Debounce Enable Register) : DEH DBCLK1 DBCLK0 P07DB P06DB P05DB P04DB...

  • Page 76: P1 Port

    MC96F6432 9.4 P1 Port 9.4.1 P1 Port Description P1 is 8-bit I/O port. P1 control registers consist of P1 data register (P1), P1 direction register (P1IO), debounce enable register (P15DB), P1 pull-up resistor selection register (P1PU), and P1 open-drain selection register (P1OD) .
  • Page 77 MC96F6432 P1OD (P1 Open-drain Selection Register) : 92H P17OD P16OD P15OD P14OD P13OD P12OD P11OD P10OD Initial value : 08H P1OD[7:0] Configure Open-drain of P1 Port Push-pull output Open-drain output P15DB (P1/P5 Debounce Enable Register) : DFH – – P54DB P52DB P17DB P16DB...

  • Page 78: P2 Port

    MC96F6432 9.5 P2 Port 9.5.1 P2 Port Description P2 is 8-bit I/O port. P2 control registers consist of P2 data register (P2), P2 direction register (P2IO), P2 pull-up resistor selection register (P2PU) and P2 open-drain selection register (P2OD). Refer to the port function selection registers for the P2 function selection.
  • Page 79 MC96F6432 P2PU (P2 Pull-up Resistor Selection Register) : AEH P27PU P26PU P25PU P24PU P23PU P22PU P21PU P20PU Initial value : 00H P2PU[7:0] Configure Pull-up Resistor of P2 Port Disable Enable P2OD (P2 Open-drain Selection Register) : 93H P27OD P26OD P25OD P24OD P23OD P22OD...

  • Page 80: P3 Port

    MC96F6432 9.6 P3 Port 9.6.1 P3 Port Description P3 is 8-bit I/O port. P3 control registers consist of P3 data register (P3), P3 direction register (P3IO) and P3 pull-up resistor selection register (P3PU). Refer to the port function selection registers for the P3 function selection.

  • Page 81: P4 Port

    MC96F6432 9.7 P4 Port 9.7.1 P4 Port Description P4 is 4-bit I/O port. P4 control registers consist of P4 data register (P4), P4 direction register (P4IO), P4 pull-up resistor selection register (P4PU) and P4 open-drain selection register (P4OD). Refer to the port function selection registers for the P4 function selection.
  • Page 82 MC96F6432 P4PU (P4 Pull-up Resistor Selection Register) : A3H – – – – P43PU P42PU P41PU P40PU – – – – Initial value : 00H P4PU[3:0] Configure Pull-up Resistor of P4 Port Disable Enable P4OD (P4 Open-drain Selection Register) : 94H –...

  • Page 83: P5 Port

    MC96F6432 9.8 P5 Port 9.8.1 P5 Port Description P5 is 6-bit I/O port. P5 control registers consist of P5 data register (P5), P5 direction register (P5IO) and P5 pull-up resistor selection register (P5PU) . Refer to the port function selection registers for the P5 function selection.

  • Page 84: Port Function

    MC96F6432 9.9 Port Function 9.9.1 Port Function Description Port function control registers consist of Port function selection register 0 ~ 5. (P0FSRH/L ~ P5FSR). 9.9.2 Register description for P0FSRH/L ~ P5FSR P0FSRH (Port 0 Function Selection High Register) : D3H –...
  • Page 85 MC96F6432 P0FSRL (Port 0 Function Selection Low Register) : D2H – P0FSRL6 P0FSRL5 P0FSRL4 P0FSRL3 P0FSRL2 P0FSRL1 P0FSRL0 – Initial value : 00H P0FSRL[6:5] P04 Function Select P0FSRL6 P0FSRL5 Description I/O Port (EINT2 function possible when input) SEG25 Function AN2 Function PWM4BA Function P0FSRL[4:3] P03 Function Select...
  • Page 86 MC96F6432 P1FSRH (Port 1 Function Selection High Register) : D5H P1FSRH7 P1FSRH6 P1FSRH5 P1FSRH4 P1FSRH3 P1FSRH2 P1FSRH1 P1FSRH0 Initial value : 00H P1FSRH[7:6] P17 Function Select P1FSRH7 P1FSRH6 Description I/O Port (EINT6/SS2 function possible when input) SEG21 Function AN6 Function Not used P1FSRH[5:4] P16 Function Select...
  • Page 87 MC96F6432 P1FSRL (Port 1 Function Selection Low Register) : D4H P1FSRL7 P1FSRL6 P1FSRL5 P1FSRL4 P1FSRL3 P1FSRL2 P1FSRL1 P1FSRL0 Initial value : 00H P1FSRL[7:6] P13 Function Select P1FSRL7 P1FSRL6 Description I/O Port (EC1 function possible when input) SEG17 Function AN10 Function BUZO Function P1FSRL[5:4] P12Function Select...
  • Page 88 MC96F6432 P2FSRH (Port 2 Function Selection High Register) : D7H – – – – P2FSRH3 P2FSRH2 P2FSRH1 P2FSRH0 – – – – Initial value : 00H P2FSRH3 P27 Function select I/O Port SEG6 Function P2FSRH2 P26 Function Select I/O Port SEG7 Function P2FSRH1 P25 Function select...
  • Page 89 MC96F6432 P2FSRL (Port 2 Function Selection Low Register) : D6H – – P2FSRL5 P2FSRL4 P2FSRL3 P2FSRL2 P2FSRL1 P2FSRL0 – – Initial value : 00H P2FSRL5 P23 Function Select I/O Port SEG10 Function P2FSRL4 P22Function Select I/O Port (SS1 function possible when input) SEG11 Function P2FSRL[3:2] P21 Function Select...
  • Page 90 MC96F6432 P3FSR (Port 3 Function Selection Register) : EEH P3FSR7 P3FSR6 P3FSR5 P3FSR4 P3FSR3 P3FSR2 P3FSR1 P3FSR0 Initial value : 00H P3FSR7 P37 Function select I/O Port COM0 Function P3FSR6 P36 Function Select I/O Port COM1 Function P3FSR5 P35 Function select I/O Port COM2/SEG0 Function P3FSR4...
  • Page 91 MC96F6432 P4FSR (Port 4 Function Selection Register) : EFH – P4FSR6 P4FSR5 P4FSR4 P4FSR3 P4FSR2 P4FSR1 P4FSR0 – Initial value : 00H P4FSR6 P43 Function Select I/O Port (SS0 function possible when input) VLC0 Function P4FSR[5:4] P42 Function Select P4FSR5 P4FSR4 Description I/O Port VLC1 Function SCK0 Function...
  • Page 92 MC96F6432 P5FSR (Port 5 Function Selection Register) : FFH – – P5FSR5 P5FSR4 P5FSR3 P5FSR2 P5FSR1 P5FSR0 – – Initial value : 00H P5FSR5 P54 Function Select I/O Port (EINT10 function possible when input) SXOUT Function P5FSR[4:3] P53 Function Select P5FSR4 P5FSR3 Description I/O Port SXIN Function...

  • Page 93: Interrupt Controller

    MC96F6432 10. Interrupt Controller 10.1 Overview The MC96F6432 supports up to 23 interrupt sources. The interrupts have separate enable register bits associated with them, allowing software control. They can also have four levels of priority assigned to them. The non-maskable interrupt source is always enabled with a higher priority than any other interrupt source, and is not controllable by software.

  • Page 94: External Interrupt

    MC96F6432 10.2 External Interrupt The external interrupt on INT0, INT1, INT5, INT6 and INT11 pins receive various interrupt request depending on the external interrupt polarity 0 high/low register (EIPOL0H/L) and external interrupt polarity 1 register (EIPOL1) as shown in Figure 10.1. Also each external interrupt source has enable/disable bits. The External interrupt flag 0 register (EIFLAG0) and external interrupt flag 1 register 1 (EIFLAG1) provides the status of external interrupts.

  • Page 95: Block Diagram

    MC96F6432 10.3 Block Diagram EIPOL1 EIFLAG1.1 EINT10 FLAG10 EIFLAG1.2 EINT11 Priority High FLAG11 USI1 I2C I2C1IFR USI1 Rx USI1 Tx EIPOL0H/L EIFLAG0.0 EINT0 FLAG0 EIFLAG0.1 EINT1 FLAG1 EIFLAG0.2 EINT2 FLAG2 EIFLAG0.3 EINT3 FLAG3 EIFLAG0.4 EINT4 FLAG4 EIFLAG0.5 EINT5 FLAG5 EIFLAG0.6 EINT6 FLAG6 EIFLAG0.7...

  • Page 96: Interrupt Vector Table

    MC96F6432 10.4 Interrupt Vector Table The interrupt controller supports 24 interrupt sources as shown in the Table 10-2. When interrupt is served, long call instruction (LCALL) is executed and program counter jumps to the vector address. All interrupt requests have their own priority order. Table 10-2 Interrupt Vector Address Table Interrupt Interrupt Source...

  • Page 97: Figure 10.3 Interrupt Sequence Flow

    MC96F6432 IE.EA Flag  0 Program Counter low Byte SP  SP + 1 M(SP)  (PCL) Saves PC value in order to continue process again after executing ISR Program Counter high Byte SP  SP + 1 M(SP)  (PCH) Interrupt Vector Address occurrence (Interrupt Vector Address) ISR(Interrupt Service Routine) move,...

  • Page 98: Effective Timing After Controlling Interrupt Bit

    MC96F6432 10.6 Effective Timing after Controlling Interrupt Bit Case a) Control Interrupt Enable Register (IE, IE1, IE2, IE3) Interrupt Enable Register command After executing IE set/clear, enable register is effective. Next Instruction Next Instruction Figure 10.4 Effective Timing of Interrupt Enable Register Case b) Interrupt flag Register Interrupt Flag Register Command...

  • Page 99: Multi Interrupt

    MC96F6432 10.7 Multi Interrupt If two requests of different priority levels are received simultaneously, the request of higher priority level is served first. If more than one interrupt request are received, the interrupt polling sequence determines which request is served first by hardware. However, for special features, multi-interrupt processing can be executed by software.

  • Page 100: Interrupt Enable Accept Timing

    MC96F6432 10.8 Interrupt Enable Accept Timing Max. 4 Machine Cycle 4 Machine Cycle System Clock Interrupt goes Active Interrupt Interrupt Processing Latched Interrupt Routine : LCALL & LJMP Figure 10.7 Interrupt Response Timing Diagram 10.9 Interrupt Service Routine Address Basic Interval Timer Basic Interval Timer Vector Table Address Service Routine Address...

  • Page 101: Interrupt Timing

    MC96F6432 10.11 Interrupt Timing Interrupt sampled here CLP2 CLP1 CLP2 C1P1 C1P2 C2P1 C2P2 SCLK INT_SRC INTR_ACK LAST_CYC INTR_LCALL 8-Bit interrupt Vector INT_VEC {8’h00, INT_VEC} PROGA Figure 10.10 Timing Chart of Interrupt Acceptance and Interrupt Return Instruction Interrupt sources are sampled at the last cycle of a command. If an interrupt source is detected the lower 8-bit of interrupt vector (INT_VEC) is decided.
  • Page 102 MC96F6432 10.12.3 External Interrupt Flag Register (EIFLAG0, EIFLAG1) The external interrupt flag 0 register (EIFLAG0) and external interrupt flag 1 register (EIFLAG1) are set to ‘1’ when the external interrupt generating condition is satisfied. The flag is cleared when the interrupt service routine is executed.

  • Page 103: Table 10-3 Interrupt Register Map

    MC96F6432 10.12.5 Register Map Table 10-3 Interrupt Register Map Name Address Default Description Interrupt Enable Register Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Enable Register 3 Interrupt Priority Register Interrupt Priority Register 1 EIFLAG0 External Interrupt Flag 0 Register EIPOL0L External Interrupt Polarity 0 Low Register EIPOL0H...
  • Page 104 MC96F6432 10.12.7 Register Description for Interrupt IE (Interrupt Enable Register) : A8H – INT5E INT4E INT3E INT2E INT1E INT0E – Initial value : 00H Enable or Disable All Interrupt bits All Interrupt disable All Interrupt enable INT5E Enable or Disable External Interrupt 0 ~ 7 (EINT0 ~ EINT7) Disable Enable INT4E...
  • Page 105 MC96F6432 IE1 (Interrupt Enable Register 1): A9H – – – INT11E INT10E INT9E INT8E INT6E – – – Initial value: 00H INT11E Enable or Disable External Interrupt 12 (EINT12) Disable Enable INT10E Enable or Disable USI0 Tx Interrupt Disable Enable INT9E Enable or Disable USI0 Rx Interrupt Disable...
  • Page 106 MC96F6432 IE2 (Interrupt Enable Register 2) : AAH –- – INT17E INT16E INT15E INT14E INT13E INT12E – – Initial value : 00H INT17E Enable or Disable Timer 4 Interrupt Disable Enable INT16E Enable or Disable Timer 3 Match Interrupt Disable Enable INT15E Enable or Disable Timer 2 Match Interrupt...
  • Page 107 MC96F6432 IP (Interrupt Priority Register) : B8H – – – – Initial value : 00H IP1 (Interrupt Priority Register 1) : F8H – – IP15 IP14 IP13 IP12 IP11 IP10 – – Initial value : 00H IP[5:0], IP1[5:0] Select Interrupt Group Priority IP1x Description level 0 (lowest)
  • Page 108 MC96F6432 EIFLAG0 (External Interrupt Flag 0 Register) : C0H FLAG7 FLAG6 FLAG5 FLAG4 FLAG3 FLAG2 FLAG1 FLAG0 Initial value : 00H When an External Interrupt 0-7 is occurred, the flag becomes ‘1’. EIFLAG0[7:0] The flag is cleared only by writing ‘0’ to the bit. So, the flag should be cleared by software.
  • Page 109 MC96F6432 EIFLAG1 (External Interrupt Flag 1 Register) : A6H – T0OVIFR T0IFR T3IFR FLAG12 FLAG11 FLAG10 FLAG8 – Initial value : 00H When T0 overflow interrupt occurs, this bit becomes ‘1’. For clearing T0OVIFR bit, write ‘0’ to this bit or automatically clear by INT_ACK signal. Writing “1”...

  • Page 110: Peripheral Hardware

    MC96F6432 11. Peripheral Hardware 11.1 Clock Generator 11.1.1 Overview As shown in Figure 11.1, the clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and the peripheral hardware. It contains main/sub-frequency clock oscillator. The main/sub clock operation can be easily obtained by attaching a crystal between the XIN/SXIN and XOUT/SXOUT pin, respectively.

  • Page 111: Table 11-1 Clock Generator Register Map

    MC96F6432 11.1.3 Register Map Table 11-1 Clock Generator Register Map Name Address Default Description SCCR System and Clock Control Register OSCCR Oscillator Control Register 11.1.4 Clock Generator Register Description The clock generator register uses clock control for system operation. The clock generation consists of System and clock control register and oscillator control register.
  • Page 112 MC96F6432 OSCCR (Oscillator Control Register) : C8H – – IRCS2 IRCS1 IRCS0 IRCE XCLKE SCLKE – – Initial value : 08H IRCS[2:0] Internal RC Oscillator Post-divider Selection IRCS2 IRCS1 IRCS0 Description INT-RC/32 (0.5MHz) INT-RC/16 (1MHz) INT-RC/8 (2MHz) INT-RC/4 (4MHz) INT-RC/2 (8MHz) INT-RC/1 (16MHz) Other values Not used...

  • Page 113: Basic Interval Timer

    MC96F6432 11.2 Basic Interval Timer 11.2.1 Overview The MC96F6432 has one 8-bit basic interval timer that is free-run and can’t stop. Block diagram is shown in Figure 11.2. In addition, the basic interval timer generates the time base for watchdog timer counting. It also provides a basic interval timer interrupt (BITIFR).

  • Page 114: Table 11-2 Basic Interval Timer Register Map

    MC96F6432 11.2.3 Register Map Table 11-2 Basic Interval Timer Register Map Name Address Default Description BITCNT Basic Interval Timer Counter Register BITCR Basic Interval Timer Control Register 11.2.4 Basic Interval Timer Register Description The basic interval timer register consists of basic interval timer counter register (BITCNT) and basic interval timer control register (BITCR).
  • Page 115 MC96F6432 BITCR (Basic Interval Timer Control Register) : 8BH – BITIFR BITCK1 BITCK0 BCLR BCK2 BCK1 BCK0 – Initial value : 01H When BIT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ BITIFR to this bit or auto clear by INT_ACK signal. Writing “1” has no effect. BIT interrupt no generation BIT interrupt generation BITCK[1:0]...

  • Page 116: Watch Dog Timer

    MC96F6432 11.3 Watch Dog Timer 11.3.1 Overview The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or something like that, and resumes the CPU to the normal state. The watchdog timer signal for malfunction detection can be used as either a CPU reset or an interrupt request.

  • Page 117: Figure 11.4 Watch Dog Timer Block Diagram

    MC96F6432 11.3.3 Block Diagram clear WDT Clock To RESET WDTCNT Circuit WDTEN To interrupt WDTIFR block clear WDTDR INT_ACK WDTCL WDTRSON WDTCR Figure 11.4 Watch Dog Timer Block Diagram 11.3.4 Register Map Table 11-3 Watch Dog Timer Register Map Name Address Default Description...
  • Page 118 MC96F6432 11.3.6 Register Description for Watch Dog Timer WDTCNT (Watch Dog Timer Counter Register: Read Case) : 8EH WDTCNT 7 WDTCNT 6 WDTCNT 5 WDTCNT 4 WDTCNT3 WDTCNT 2 WDTCNT 1 WDTCNT 0 Initial value : 00H WDTCNT[7:0] WDT Counter WDTDR (Watch Dog Timer Data Register: Write Case) : 8EH WDTDR7 WDTDR 6...

  • Page 119: Watch Timer

    MC96F6432 11.4 Watch Timer 11.4.1 Overview The watch timer has the function for RTC (Real Time Clock) operation. It is generally used for RTC design. The internal structure of the watch timer consists of the clock source select circuit, timer counter circuit, output select circuit, and watch timer control register.

  • Page 120: Table 11-4 Watch Timer Register Map

    MC96F6432 11.4.3 Register Map Table 11-4 Watch Timer Register Map Name Address Default Description WTCNT Watch Timer Counter Register WTDR Watch Timer Data Register WTCR Watch Timer Control Register 11.4.4 Watch Timer Register Description The watch timer register consists of watch timer counter register (WTCNT), watch timer data register (WTDR), and watch timer control register (WTCR).
  • Page 121 MC96F6432 WTCR (Watch Timer Control Register) : 96H – – WTEN WTIFR WTIN1 WTIN0 WTCK1 WTCK0 – – Initial value : 00H WTEN Control Watch Timer Disable Enable When WT Interrupt occurs, this bit becomes ‘1’. For clearing bit, WTIFR write ‘0’...

  • Page 122: Timer 0

    MC96F6432 11.5 Timer 0 11.5.1 Overview The 8-bit timer 0 consists of multiplexer, timer 0 counter register, timer 0 data register, timer 0 capture data register and timer 0 control register (T0CNT, T0DR, T0CDR, T0CR). It has three operating modes: 8-bit timer/counter mode 8-bit PWM output mode 8-bit capture mode...

  • Page 123: Figure 11.6 8-Bit Timer/Counter Mode For Timer 0

    MC96F6432 11.5.2 8-Bit Timer/Counter Mode The 8-bit timer/counter mode is selected by control register as shown in Figure 11.6. The 8-bit timer have counter and data register. The counter register is increased by internal or external clock input. Timer 0 can use the input clock with one of 2, 4, 8, 32, 128, 512 and 2048 prescaler division rates (T0CK[2:0]).

  • Page 124: Figure 11.8 8-Bit Pwm Mode For Timer 0

    MC96F6432 11.5.3 8-Bit PWM Mode The timer 0 has a high speed PWM (Pulse Width Modulation) function. In PWM mode, T0O/PWM0O pin outputs up to 8-bit resolution PWM output. This pin should be configured as a PWM output by setting the T0O/PWM0O function by P5FSR[4:3] bits.

  • Page 125: Figure 11.9 Pwm Output Waveforms In Pwm Mode For Timer 0

    MC96F6432 PWM Mode(T0MS = 01b) Set T0EN Timer 0 clock T0CNT T0DR T0 Overflow Interrupt 1. T0DR = 4AH T0PWM T0 Match Interrupt 2. T0DR = 00H T0PWM T0 Match Interrupt 3. T0DR = FFH T0PWM T0 Match Interrupt Figure 11.9 PWM Output Waveforms in PWM Mode for Timer 0 June 22, 2018 Ver.

  • Page 126: Figure 11.10 8-Bit Capture Mode For Timer 0

    MC96F6432 11.5.4 8-Bit Capture Mode The timer 0 capture mode is set by T0MS[1:0] as ‘1x’. The clock source can use the internal/external clock. Basically, it has the same function as the 8-bit timer/counter mode and the interrupt occurs when T0CNT is equal to T0DR.

  • Page 127: Figure 11.11 Input Capture Mode Operation For Timer 0

    MC96F6432 T0CDR Load T0CNT Value Count Pulse Period Up-count TIME Ext. EINT10 PIN Interrupt Request (FLAG10) Interrupt Interval Period Figure 11.11 Input Capture Mode Operation for Timer 0 T0CNT Interrupt Request (T0IFR) Ext. EINT10 PIN Interrupt Request (FLAG10) Interrupt Interval Period = FF Figure 11.12 Express Timer Overflow in Capture Mode June 22, 2018 Ver.

  • Page 128: Figure 11.13 8-Bit Timer 0 Block Diagram

    MC96F6432 11.5.5 Block Diagram INT_ACK Clear To interrupt T0OVIFR block fx/2 fx/4 8-bit Timer 0 Counter Match signal fx/8 Clear INT_ACK T0CNT (8Bit) fx/32 T0CC Clear fx/128 Clear fx/512 Match To interrupt T0EN T0IFR block fx/2048 Comparator T0DR (8Bit) T0MS[1:0] T0CK[2:0] 8-bit Timer 0 Data Register EIPOL1[1:0]...

  • Page 129: Table 11-6 Timer 0 Register Map

    MC96F6432 11.5.6 Register Map Table 11-6 Timer 0 Register Map Name Address Default Description T0CNT Timer 0 Counter Register T0DR Timer 0 Data Register T0CDR Timer 0 Capture Data Register T0CR Timer 0 Control Register 11.5.6.1 Timer/Counter 0 Register Description The timer/counter 0 register consists of timer 0 counter register (T0CNT), timer 0 data register (T0DR), timer 0 capture data register (T0CDR), and timer 0 control register (T0CR).
  • Page 130 MC96F6432 T0CR (Timer 0 Control Register) : B2H – T0EN T0MS1 T0MS0 T0CK2 T0CK1 T0CK0 T0CC – Initial value : 00H T0EN Control Timer 0 Timer 0 disable Timer 0 enable T0MS[1:0] Control Timer 0 Operation Mode T0MS1 T0MS0 Description Timer/counter mode PWM mode Capture mode...

  • Page 131: Timer 1

    MC96F6432 11.6 Timer 1 11.6.1 Overview The 16-bit timer 1 consists of multiplexer, timer 1 A data register high/low, timer 1 B data register high/low and timer 1 control register high/low (T1ADRH, T1ADRL, T1BDRH, T1BDRL, T1CRH, T1CRL). It has four operating modes: 16-bit timer/counter mode 16-bit capture mode 16-bit PPG output mode (one-shot mode)

  • Page 132: Figure 11.14 16-Bit Timer/Counter Mode For Timer 1

    MC96F6432 ADDRESS:BBH – – – – T1EN T1MS1 T1MS0 T1CC T1CRH INITIAL VALUE : 0000_0000B – – – – ADDRESS:BAH – T1CK2 T1CK1 T1CK0 T1IFR T1POL T1ECE T1CNTR T1CRL INITIAL VALUE : 0000_0000B – 16-bit A Data Register T1ADRH/T1ADRL A Match Reload T1CC T1EN...

  • Page 133: Figure 11.16 16-Bit Capture Mode For Timer 1

    MC96F6432 11.6.3 16-Bit Capture Mode The 16-bit timer 1 capture mode is set by T1MS[1:0] as ‘01’. The clock source can use the internal/external clock. Basically, it has the same function as the 16-bit timer/counter mode and the interrupt occurs when T1CNTH/T1CNTL is equal to T1ADRH/T1ADRL.

  • Page 134: Figure 11.17 Input Capture Mode Operation For Timer 1

    MC96F6432 T1BDRH/L Load T1CNTH/L Value Count Pulse Period Up-count TIME Ext. EINT11 PIN Interrupt Request (FLAG11) Interrupt Interval Period Figure 11.17 Input Capture Mode Operation for Timer 1 FFFF FFFF T1CNTH/L Interrupt Request (T1IFR) Ext. EINT11 PIN Interrupt Request (FLAG11) Interrupt Interval Period = FFFF +FFFF Figure 11.18 Express Timer Overflow in Capture Mode...

  • Page 135: Figure 11.19 16-Bit Ppg Mode For Timer 1

    MC96F6432 11.6.4 16-Bit PPG Mode The timer 1 has a PPG (Programmable Pulse Generation) function. In PPG mode, T1O/PWM1O pin outputs up to 16-bit resolution PWM output. This pin should be configured as a PWM output by setting P1FSRL[5:4] to ‘11’...

  • Page 136: Figure 11.20 16-Bit Ppg Mode Timming Chart For Timer 1

    MC96F6432 Repeat Mode(T1MS = 11b) and "Start High"(T1POL = 0b). Clear and Start Set T1EN Timer 1 clock Counter T1ADRH/L T1 Interrupt 1. T1BDRH/L(5) < T1ADRH/L PWM1O B Match A Match 2. T1BDRH/L >= T1ADRH/L PWM1O A Match 3. T1BDRH/L = "0000H" PWM1O A Match Low Level...

  • Page 137: Figure 11.21 16-Bit Timer 1 Block Diagram

    MC96F6432 11.6.5 Block Diagram 16-bit A Data Register T1ADRH/T1ADRL A Match Reload T1CC T1EN To Timer 2 T1CK[2:0] block T1ECE INT_ACK Buffer Register A Clear Edge A Match To interrupt Detector T1IFR block T1EN fx/1 Comparator fx/2 A Match Clear fx/4 16-bit Counter T1CC...
  • Page 138 MC96F6432 11.6.6.1 Timer/Counter 1 Register Description The timer/counter 1 register consists of timer 1 A data high register (T1ADRH), timer 1 A data low register (T1ADRL), timer 1 B data high register (T1BDRH), timer 1 B data low register (T1BDRL), timer 1 control High register (T1CRH) and timer 1 control low register (T1CRL).
  • Page 139 MC96F6432 T1CRH (Timer 1 Control High Register) : BBH – – – – T1EN T1MS1 T1MS0 T1CC – – – – Initial value : 00H T1EN Control Timer 1 Timer 1 disable Timer 1 enable (Counter clear and start) T1MS[1:0] Control Timer 1 Operation Mode T1MS1 T1MS0 Description...
  • Page 140 MC96F6432 T1CRL (Timer 1 Control Low Register) : BAH – T1CK2 T1CK1 T1CK0 T1IFR T1POL T1ECE T1CNTR – Initial value : 00H T1CK[2:0] Select Timer 1 clock source. fx is main system clock frequency T1CK2 T1CK1 T1CK0 Description fx/2048 fx/512 fx/64 fx/8 fx/4...

  • Page 141: Timer 2

    MC96F6432 11.7 Timer 2 11.7.1 Overview The 16-bit timer 2 consists of multiplexer, timer 2 A data high/low register, timer 2 B data high/low register and timer 2 control high/low register (T2ADRH, T2ADRL, T2BDRH, T2BDRL, T2CRH, T2CRL). It has four operating modes: 16-bit timer/counter mode 16-bit capture mode 16-bit PPG output mode (one-shot mode)

  • Page 142: Figure 11.22 16-Bit Timer/Counter Mode For Timer 2

    MC96F6432 11.7.2 16-Bit Timer/Counter Mode The 16-bit timer/counter mode is selected by control register as shown in Figure 11.22. The 16-bit timer have counter and data register. The counter register is increased by internal or timer 1 A match clock input. Timer 2 can use the input clock with one of 1, 2, 4, 8, 32, 128, 512 and T1 A Match prescaler division rates (T2CK[2:0]).

  • Page 143: Figure 11.23 16-Bit Timer/Counter 2 Example

    MC96F6432 Match with T2ADRH/L T2CNTH/L Value Count Pulse Period Up-count TIME Interrupt Period x (n+1) Timer 2 (T2IFR) Occur Occur Occur Interrupt Interrupt Interrupt Interrupt Figure 11.23 16-Bit Timer/Counter 2 Example June 22, 2018 Ver. 2.9...

  • Page 144: Figure 11.24 16-Bit Capture Mode For Timer 2

    MC96F6432 11.7.3 16-Bit Capture Mode The timer 2 capture mode is set by T2MS[1:0] as ‘01’. The clock source can use the internal clock. Basically, it has the same function as the 16-bit timer/counter mode and the interrupt occurs when T2CNTH/T2CNTL is equal to T2ADRH/T2ADRL.

  • Page 145: Figure 11.25 Input Capture Mode Operation For Timer 2

    MC96F6432 T2BDRH/L Load T2CNTH/L Value Count Pulse Period Up-count TIME Ext. EINT12 PIN Interrupt Request (FLAG12) Interrupt Interval Period Figure 11.25 Input Capture Mode Operation for Timer 2 FFFF FFFF T2CNTH/L Interrupt Request (T2IFR) Ext. EINT12 PIN Interrupt Request (FLAG12) Interrupt Interval Period = FFFF +FFFF Figure 11.26 Express Timer Overflow in Capture Mode...

  • Page 146: Figure 11.27 16-Bit Ppg Mode For Timer 2

    MC96F6432 11.7.4 16-Bit PPG Mode The timer 2 has a PPG (Programmable Pulse Generation) function. In PPG mode, the T2O/PWM2O pin outputs up to 16-bit resolution PWM output. This pin should be configured as a PWM output by set P1FSRL[3:2] to ‘11’...

  • Page 147: Figure 11.28 16-Bit Ppg Mode Timming Chart For Timer 2

    MC96F6432 Repeat Mode(T2MS = 11b) and "Start High"(T2POL = 0b). Clear and Start Set T2EN Timer 2 clock Counter T2ADRH/L T2 Interrupt 1. T2BDRH/L(5) < T2ADRH/L PWM2O B Match A Match 2. T2BDRH/L >= T2ADRH/L PWM2O A Match 3. T2BDRH/L = "0000H" PWM2O A Match Low Level...

  • Page 148: Figure 11.29 16-Bit Timer 2 Block Diagram

    MC96F6432 11.7.5 Block Diagram 16-bit A Data Register T2ADRH/T2ADRL A Match Reload T2CC T2CK[2:0] T2EN INT_ACK Buffer Register A Clear T1 A Match A Match To interrupt T2IFR block T2EN fx/1 Comparator fx/2 A Match Clear fx/4 16-bit Counter T2CC T2CNTH/T2CNTL fx/8 T2EN...
  • Page 149 MC96F6432 11.7.6.1 Timer/Counter 2 Register Description The timer/counter 2 register consists of timer 2 A data high register (T2ADRH), timer 2 A data low register (T2ADRL), timer 2 B data high register (T2BDRH), timer 2 B data low register (T2BDRL), timer 2 control High register (T2CRH) and timer 2 control low register (T2CRL).
  • Page 150 MC96F6432 T2CRH (Timer 2 Control High Register) : C3H – – – – T2EN T2MS1 T2MS0 T2CC – – – – Initial value : 00H T2EN Control Timer 2 Timer 2 disable Timer 2 enable (Counter clear and start) T2MS[1:0] Control Timer 2 Operation Mode T2MS1 T2MS0 Description...
  • Page 151 MC96F6432 T2CRL (Timer 2 Control Low Register) : CAH – – T2CK2 T2CK1 T2CK0 T2IFR T2POL T2CNTR – – Initial value : 00H T2CK[2:0] Select Timer 2 clock source. fx is main system clock frequency T2CK2 T2CK1 T2CK0 Description fx/512 fx/128 fx/32 fx/8...

  • Page 152: Timer 3, 4

    MC96F6432 11.8 Timer 3, 4 11.8.1 Overview Timer 3 and timer 4 can be used either two 8-bit timer/counter or one 16-bit timer/counter with combine them. Each 8-bit timer/event counter module has multiplexer, comparator, 8-bit timer data register, 8-bit counter register, control register and capture data register (T3CNT, T3DR, T3CAPR, T3CR, T4CNT, T4DR, T4CAPR, T4CR).

  • Page 153: Figure 11.30 8-Bit Timer/Counter Mode For Timer 3, 4

    MC96F6432 11.8.2 8-Bit Timer/Counter 3, 4 Mode The 8-bit timer/counter mode is selected by control register as shown in Figure 11.30. The two 8-bit timers have each counter and data register. The counter register is increased by internal or external clock input. Timer 3 can use the input clock with one of 2, 4, 8, 32, 128, 512, 2048 and EC3 prescaler division rates (T3CK[2:0]).

  • Page 154: Figure 11.31 16-Bit Timer/Counter Mode For Timer 3

    MC96F6432 11.8.3 16-Bit Timer/Counter 3 Mode The 16-bit timer/counter mode is selected by control register as shown in Figure 11.31. The 16-bit timer have counter and data register. The counter register is increased by internal or external clock input. Timer 3 can use the input clock with one of 2, 4, 8, 32, 128, 512 and 2048 prescaler division rates (T3CK[2:0]).
  • Page 155 MC96F6432 11.8.4 8-Bit Timer 3, 4 Capture Mode The 8-bit Capture 3 and 4 mode is selected by control register as shown in Figure 11.32. The timer 3, 4 capture mode is set by T3MS, T4MS as ‘1’. The clock source can use the internal/external clock. Basically, it has the same function as the 8-bit timer/counter mode and the interrupt occurs when T3CNT, T4CNT is equal to T3DR, T4DR.

  • Page 156: Figure 11.32 8-Bit Capture Mode For Timer 3, 4

    MC96F6432 ADDRESS:1000H (ESFR) – T3EN T3MS T3CK2 T3CK1 T3CK0 T3CN T3ST T3CR INITIAL VALUE : 0000_0000B – ADDRESS:1002H (ESFR) 16BIT T4MS T4CN T4ST T4CK3 T4CK2 T4CK1 T4CK0 T4CR INITIAL VALUE : 0000_0000B FLAG0 To interrupt (EIFLAG0.1) block T4MS Clear 8-bit Timer 4 Capture Register EINT1 T4CAPR (8Bit) EIPOL0L[3:2]...

  • Page 157: Figure 11.33 16-Bit Capture Mode For Timer 3

    MC96F6432 11.8.5 16-Bit Timer 3 Capture Mode The 16-bit Capture mode is selected by control register as shown in Figure 11.33. The 16-bit capture mode is the same operation as 8-bit capture mode, except that the timer register uses 16 bits. The 16-bit timer 3 capture mode is set by T3MS, T4MS as ‘1’.

  • Page 158: Table 11-12 Pwm Frequency Vs. Resolution At 8 Mhz

    MC96F6432 11.8.6 10-Bit Timer 4 PWM Mode The timer 4 has a high speed PWM (Pulse Width Modulation) function. In PWM mode, the 6-channel pins output up to 10-bit resolution PWM output. This pin should be configured as a PWM output by set PWM4E to ‘1’. When the value of 2bit +T4CNT and T4PPRH/L are identical in timer 4, a period match signal is generated and the interrupt of timer 4 occurs.

  • Page 159: Figure 11.34 10-Bit Pwm Mode (Force 6-Ch)

    MC96F6432 ADDRESS:1002H (ESFR) 16BIT T4MS T4CN T4ST T4CK3 T4CK2 T4CK1 T4CK0 T4CR INITIAL VALUE : 0000_0000B ADDRESS:1003H (ESFR) PWM4E ESYNC BMOD PHLT UPDT UALL NOPS1 NOPS0 T4PCR1 INITIAL VALUE : 0000_0000B ADDRESS:1004H (ESFR) – FORCA PAAOE PABOE PBAOE PBBOE PCAOE PCBOE T4PCR2 INITIAL VALUE : 0000_0000B –...

  • Page 160: Figure 11.35 10-Bit Pwm Mode (Force All-Ch)

    MC96F6432 ADDRESS:1002H (ESFR) 16BIT T4MS T4CN T4ST T4CK3 T4CK2 T4CK1 T4CK0 T4CR INITIAL VALUE : 0000_0000B ADDRESS:1003H (ESFR) PWM4E ESYNC BMOD PHLT UPDT UALL NOPS1 NOPS0 T4PCR1 INITIAL VALUE : 0000_0000B ADDRESS:1004H (ESFR) – FORCA PAAOE PABOE PBAOE PBBOE PCAOE PCBOE T4PCR2 INITIAL VALUE : 0000_0000B –...

  • Page 161: Figure 11.36 Example Of Pwm At 4 Mhz

    MC96F6432 Source Clock T4CNT P02/PWM4AA POLAA = 1 P02/PWM4AA POLAA = 0 Duty Cycle(1+80 )X250ns = 32.25us )X250ns = 256us  3.9kHz Period Cycle(1+3FF T4PPRH(2 Bit) T4PPRL(8 Bit) T4CR = 00 T4PPRH = 03 T4PPRL = FF T4ADRH = 00 T4ADRH(2 Bit) T4ADRL(8 Bit) T4ADRL = 80...

  • Page 162: Figure 11.38 Example Of Pwm Output Waveform

    MC96F6432 Phase correction & Frequency correction On operating PWM, it is possible that it is changed the phase and the frequency by using BMOD bit (back-to- back mode) in T4PCR1 register. (Figure 1.38, Figure 11.39, Figure 11.40 referred) In the back-to-back mode, the counter of PWM repeats up/down count. In fact, the effective duty and period becomes twofold of the register set values.

  • Page 163: Figure 11.40 Example Of Phase Correction And Frequency Correction Of Pwm

    MC96F6432 Duty, Period Update T4CNT Back-to-Back mode Duty1 Duty2 Duty3 Output Period1 Period2 Period3 Interrupt Timing Overflow INT. Overflow INT. Bottom INT. Overflow INT. Figure 11.40 Example of Phase Correction and Frequency correction of PWM External Sync If using ESYNC bit of T4PCR1 register, it is possible to synchronize the output of PWM from external signal. If ESYNC bit sets to ‘1’, the external signal moves to PWM module through the BLNK pin.

  • Page 164: Figure 11.42 Example Of Force Drive All Channel With A-Ch

    MC96F6432 FORCE Drive ALL Channel with A-ch mode If FORCA bit sets to ‘1’, it is possible to enable or disable all PWM output pins through PWM outputs which occur from A-ch duty counter. It is noted that the inversion outputs of A, B, C channel have the same A-ch output waveform.

  • Page 165: Figure 11.43 Example Of Force Drive 6-Ch Mode

    MC96F6432 FORCE 6-Ch Drive If FORCA bit sets to ‘0’, it is possible to enable or disable PWM output pin and inversion output pin generated through the duty counter of each channel. The inversion output is the reverse phase of the PWM output. A AA/AB output of the A-channel duty register, a BA/BB output of the B-channel duty register, a CA/CB output of the C- channel duty register are controlled respectively.
  • Page 166 MC96F6432 PWM output Delay If using the T4DLYA, T4DLYB, T4DLYC register, it can delay PWM output based on the rising edge. At that time, it does not change the falling edge, so the duty is reduced as the time delay. In POLAA/BA/CA setting to ‘0’, the delay is applied to the falling edge.

  • Page 167: Figure 11.44 Example Of Pwm Delay

    MC96F6432 ADDRESS : 1004H (ESFR) T4PCR2 FORCA PAAOE PABOE PBAOE PBBOE PCAOE PCBOE INITIAL VALUE : 0-00_0000B ADDRESS : 1005H (ESFR) T4PCR3 HZCLR POLBO POLAA POLAB POLBA POLBB POLCA POLCB INITIAL VALUE : 0000_0000B ADDRESS : 1010H (ESFR) T4DLYA T4DLYAA3 T4DLYAA2 T4DLYAA1 T4DLYAA0...

  • Page 168: Figure 11.45 Two 8-Bit Timer 3, 4 Block Diagram

    MC96F6432 11.8.7 Block Diagram FLAG0 To interrupt (EIFLAG0.1) block T4MS Clear 8-bit Timer 4 Capture Register INT_ACK EINT1 T4CAPR (8Bit) EIPOL0L[3:2] 8-bit Timer 4 Data Register T4CK[3:0] T4DR (8Bit) Comparator fx/1 To interrupt fx/2 T4CN block Match fx/4 Clear fx/8 T4CNT (8Bit) Clear 8-bit Timer 4 Counter...

  • Page 169: Figure 11.46 16-Bit Timer 3 Block Diagram

    MC96F6432 T3ST fx/2 fx/4 16-bit Timer 3 Counter fx/8 Clear T4CNT/T3CNT (16Bit) INT_ACK fx/32 Clear fx/128 Clear fx/512 Match To interrupt T3CN T3IFR block fx/2048 Comparator T4DR/T3DR (16Bit) T3CK[2:0] 16-bit Timer 3 Data Register EIPOL0L[1:0] T4CAPR/T3CAPR (16Bit) EINT0 INT_ACK 16-bit Timer 3 Capture Register Clear T3MS FLAG0...

  • Page 170: Table 11-14 Timer 3, 4 Register Map

    MC96F6432 11.8.8 Register Map Table 11-14 Timer 3, 4 Register Map Name Address Default Description T3CNT 1001H (ESFR) Timer 3 Counter Register T3DR 1001H (ESFR) Timer 3 Data Register T3CAPR 1001H (ESFR) Timer 3 Capture Data Register T3CR 1000H (ESFR) Timer 3 Control Register T4PPRH 1009H (ESFR)
  • Page 171 MC96F6432 11.8.8.1 Timer/Counter 3 Register Description The timer/counter 3 register consists of timer 3 counter register (T3CNT), timer 3 data register (T3DR), timer 3 capture data register (T3CAPR) and timer 3 control register (T3CR). 11.8.8.2 Register Description for Timer/Counter 3 T3CNT (Timer 3 Counter Register: Read Case, Timer mode only) : 1001H (ESFR) T3CNT7 T3CNT6...
  • Page 172 MC96F6432 T3CR (Timer 3 Control Register) : 1000H (ESFR) – T3EN T3MS T3CK2 T3CK1 T3CK0 T3CN T3ST – Initial value : 00H T3EN Control Timer 3 Timer 3 disable Timer 3 enable T3MS Control Timer 3 Operation Mode Timer/counter mode (T3O: toggle at match) Capture mode (the match interrupt can occur) T3CK[2:0] Select Timer 3 clock source.
  • Page 173 MC96F6432 11.8.8.3 Timer/Counter 4 Register Description The timer/counter 4 register consists of timer 4 PWM period high/low register (T4PPRH/L), timer 4 PWM A duty high/low register (T4ADRH/L), timer 4 PWM B duty high/low register (T4BDRH/L), timer 4 PWM C duty high/low register (T4CDRH/L), timer 4 PWM A delay register (T4DLYA), timer 4 PWM B delay register (T4DLYB), timer 4 PWM C delay register (T4DLYC), timer 4 data register (T4DR), timer 4 capture data register (T4CAPR), timer 4 counter register (T4CNT), timer 4 control register (T4CR), timer 4 PWM control register 1 (T4PCR1), timer 4...
  • Page 174 MC96F6432 T4BDRH (Timer 4 PWM B Duty High Register : 6-ch PWM mode only) : 100DH (ESFR) – – – – – – T4BDRH1 T4BDRH0 – – – – – – Initial value : 00H T4BDRH[1:0] T4 PWM B Duty Data High Byte T4BDRL (Timer 4 PWM B Duty Low Register : 6-ch PWM mode only) : 100CH (ESFR) T4BDRL7 T4BDRL6...
  • Page 175 MC96F6432 T4DLYC (Timer 4 PWM C Delay Register : 6-ch PWM mode only) : 1012H (ESFR) T4DLYCA3 T4DLYCA2 T4DLYCA1 T4DLYCA0 T4DLYCB3 T4DLYCB2 T4DLYCB1 T4DLYCB0 Initial value : 00H T4DLYCA[3:0] PWM4CA Delay Data (Rising edge only) T4DLYCB[3:0] PWM4CB Delay Data (Rising edge only) T4DR (Timer 4 Data Register: Timer and Capture mode only) : 1013H (ESFR) T4DR7 T4DR6...
  • Page 176 MC96F6432 T4CR (Timer 4 Control Register) : 1002H (ESFR) 16BIT T4MS T4CN T4ST T4CK3 T4CK2 T4CK1 T4CK0 Initial value : 00H 16BIT Select Two 8-bit or 16-bit Mode for Timer 3/4 Two 8-bit Timer 3/4 16-bit Timer 3 T4MS Control Timer 4 Operation Mode Timer/counter mode (T4O: toggle at match) Capture mode (the match interrupt can occur) T4CN...
  • Page 177 MC96F6432 T4PCR1 (Timer 4 PWM Control Register 1) : 1003H (ESFR) PWM4E ESYNC BMOD PHLT UPDT UALL NOPS1 NOPS0 Initial value : 00H PWM4E Control Timer 4 Mode Select timer/counter or capture mode of Timer 4 Select 10-bit PWM mode of Timer 4 ESYNC Select the Operation of External Sync with the BLNK pin Disable external sync operation...
  • Page 178 MC96F6432 T4PCR2 (Timer 4 PWM Control Register 2) : 1004H (ESFR) – FORCA PAAOE PABOE PBAOE PBBOE PCAOE PCBOE – Initial value : 00H FORCA Control The PWM outputs Mode 6-channel mode (The PWM4xA/PWM4xB pins are output according to the T4xDR registers, respectively.
  • Page 179 MC96F6432 T4PCR3 (Timer 4 PWM Control Register 3) : 1005H (ESFR) HZCLR POLBO POLAA POLAB POLBA POLBB POLCA POLCB Initial value : 00H HZCLR High-Impedance Output Clear Bit No effect Clear high-impedance output (The PWM4xA/PWM4xB pins are back to output and this bit is automatically cleared to logic ‘0’.
  • Page 180 MC96F6432 T4ISR (Timer 4 Interrupt Status Register) : 1006H (ESFR) – – – IOVR IBTM ICMA ICMB ICMC – – – Initial value : 00H Timer 4 Overflow Interrupt Status, Write ‘0’ to this bit for clear IOVR Overflow no occurrence Overflow occurrence Timer 4 Bottom Interrupt Status, Write ‘0’...

  • Page 181: Buzzer Driver

    MC96F6432 11.9 Buzzer Driver 11.9.1 Overview The Buzzer consists of 8 bit counter, buzzer data register (BUZDR), and buzzer control register (BUZCR). The Square Wave (61.035Hz~125.0 kHz @8MHz) is outputted through P13/SEG17/AN10/EC1/BUZO pin. The buzzer data register (BUZDR) controls the buzzer frequency (look at the following expression). In buzzer control register (BUZCR), BUCK[1:0] selects source clock divided by prescaler.

  • Page 182: Table 11-16 Buzzer Driver Register Map

    MC96F6432 11.9.3 Register Map Table 11-16 Buzzer Driver Register Map Name Address Default Description BUZDR Buzzer Data Register BUZCR Buzzer Control Register 11.9.4 Buzzer Driver Register Description Buzzer driver consists of buzzer data register (BUZDR) and buzzer control register (BUZCR). 11.9.5 Register Description for Buzzer Driver BUZDR (Buzzer Data Register) : 8FH BUZDR7...

  • Page 183: Spi 2

    MC96F6432 11.10 SPI 2 11.10.1 Overview There is serial peripheral interface (SPI 2) one channel in MC96F6432. The SPI 2 allows synchronous serial data transfer between the external serial devices. It can do Full-duplex communication by 4-wire (MOSI2, MISO2, SCK2, SS2), support master/slave mode, can select serial clock (SCK2) polarity, phase and whether LSB first data transfer or MSB first data transfer.
  • Page 184 MC96F6432 11.10.3 Data Transmit / Receive Operation User can use SPI 2 for serial data communication by following step 1. Select SPI 2 operation mode(master/slave, polarity, phase) by control register SPICR. 2. When the SPI 2 is configured as a Master, it selects a Slave by SS2 signal (active low). When the SPI 2 is configured as a Slave, it is selected by SS2 signal incoming from Master 3.

  • Page 185: Figure 11.50 Spi 2 Transmit/Receive Timing Diagram At Cpha = 0

    MC96F6432 11.10.5 SPI 2 Timing Diagram SCK2 (CPOL = 0) SCK2 (CPOL = 1) MISO2/MOSI2 (Output) MOSI2/MISO2 (Input) SPIIFR SPI 2 Transmit/Receive Timing Diagram at CPHA = 0 Figure 11.50 SCK2 (CPOL = 0) SCK2 (CPOL = 1) MISO2/MOSI2 (Output) MOSI2/MISO2 (Input) SPIIFR...

  • Page 186: Table 11-17 Spi 2 Register Map

    MC96F6432 11.10.6 Register Map Table 11-17 SPI 2 Register Map Name Address Default Description SPISR SPI 2 Status Register SPIDR SPI 2 Data Register SPICR SPI 2 Control Register 11.10.7 SPI 2 Register Description The SPI 2 register consists of SPI 2 control register (SPICR), SPI 2 status register (SPISR) and SPI 2 data register (SPIDR) 11.10.8 Register Description for SPI 2 SPIDR (SPI 2 Data Register) : B6H...
  • Page 187 MC96F6432 SPISR (SPI 2 Status Register) : B7H – – – SPIIFR WCOL SS_HIGH FXCH SSENA – – – Initial value : 00H When SPI 2 Interrupt occurs, this bit becomes ‘1’. IF SPI 2 interrupt is SPIIFR enable, this bit is auto cleared by INT_ACK signal. And if SPI 2 Interrupt is disable, this bit is cleared when the status register SPISR is read, and then access (read/write) the data register SPIDR.
  • Page 188 MC96F6432 SPICR (SPI 2 Control Register) : B5H SPIEN FLSB CPOL CPHA DSCR SCR1 SCR0 Initial value : 00H SPIEN This bit controls the SPI 2 operation Disable SPI 2 operation Enable SPI 2 operation FLSB This bit selects the data transmission sequence MSB first LSB first This bit selects whether Master or Slave mode...

  • Page 189: 12-Bit A/D Converter

    MC96F6432 11.11 12-Bit A/D Converter 11.11.1 Overview The analog-to-digital converter (A/D) allows conversion of an analog input signal to corresponding 12-bit digital value. The A/D module has eight analog inputs. The output of the multiplexer is the input into the converter which generates the result through successive approximation.

  • Page 190: Figure 11.52 12-Bit Adc Block Diagram

    MC96F6432 11.11.3 Block Diagram TRIG[2:0] ADST T1 A match signal T4 overflow event signal T4 A match event signal ADSEL[3:0] Start T4 B match event signal (Select one input pin T4 C match event signal of the assigned pins) Clock ADCLK Selector Clear...

  • Page 191: Figure 11.55 Adc Operation For Align Bit

    MC96F6432 11.11.4 ADC Operation Align bit set “0” ADCO11 ADCO10 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0 ADCDRH7 ADCDRH6 ADCDRH5 ADCDRH4 ADCDRH3 ADCDRH2 ADCDRH1 ADCDRH0 ADCDRL7 ADCDRL6 ADCDRL5 ADCDRL4 ADCDRH[7:0] ADCDRL[7:4] ADCDRL[3:0] bits are “0” Align bit set “1” ADCO11 ADCO10 ADCO9...

  • Page 192: Figure 11.56 A/D Converter Operation Flow

    MC96F6432 SET ADCCRH Select ADC Clock and Data Align Bit. SET ADCCRL ADC enable & Select AN Input Channel. Converting START Start ADC Conversion. If Conversion is completed, AFLAG is set “1” and ADC AFLAG = 1? interrupt is occurred. After Conversion is completed, read ADCDRH and ADCDRL.
  • Page 193 MC96F6432 11.11.7 Register Description for ADC ADCDRH (A/D Converter Data High Register) : 9FH ADDM11 ADDM10 ADDM9 ADDM8 ADDM7 ADDM6 ADDM5 ADDM4 ADDL11 ADDL10 ADDL9 ADDL8 Initial value : xxH ADDM[11:4] MSB align, A/D Converter High Data (8-bit) ADDL[11:8] LSB align, A/D Converter High Data (4-bit) ADCDRL (A/D Converter Data Low Register) : 9EH ADDM3 ADDM2...
  • Page 194 MC96F6432 ADCCRL (A/D Converter Control Low Register) : 9CH STBY ADST REFSEL AFLAG ADSEL3 ADSEL2 ADSEL1 ADSEL0 Initial value : 00H STBY Control Operation of A/D (The ADC module is automatically disabled at stop mode) ADC module disable ADC module enable ADST Control A/D Conversion stop/start.

  • Page 195: Usi0 (Uart + Spi + I2C)

    MC96F6432 11.12 USI0 (UART + SPI + I2C) 11.12.1 Overview The USI0 consists of USI0 control register1/2/3/4, USI0 status register 1/2, USI0 baud-rate generation register, USI0 data register, USI0 SDA hold time register, USI0 SCL high period register, USI0 SCL low period register, and USI0 slave address register (USI0CR1, USI0CR2, USI0CR3, USI0CR4, USI0ST1, USI0ST2, USI0BD, USI0DR, USI0SDHR, USI0SCHR, USI0SCLR, USI0SAR).
  • Page 196 MC96F6432 11.12.2 USI0 UART Mode The universal synchronous and asynchronous serial receiver and transmitter (UART) is a highly flexible serial communication device. The main features are listed below. - Full Duplex Operation (Independent Serial Receive and Transmit Registers) - Asynchronous or Synchronous Operation - Baud Rate Generator - Supports Serial Frames with 5,6,7,8, or 9 Data Bits and 1 or 2 Stop Bits - Odd or Even Parity Generation and Parity Check Supported by Hardware...

  • Page 197: Figure 11.57 Usi0 Uart Block Diagram

    MC96F6432 11.12.3 USI0 UART Block Diagram Master SCK0 Control USI0MS[1:0] SCLK USI0BD (fx: System clock) To interrupt block Baud Rate Generator DBLS0 WAKEIE0 RXCIE0 Clock Sync Logic At Stop mode WAKE0 Low level RXC0 detector RXD0 Clock Recovery Control USI0S[2:0] RXE0 LOOPS0 Data...

  • Page 198: Figure 11.58 Clock Generation Block Diagram (Usi0)

    MC96F6432 11.12.4 USI0 Clock Generation USI0BD DBLS0 SCLK (USI0BD+1) Prescaling Up-Counter txclk SCLK MASTER0 Edge Sync Register USI0MS[1:0] Detector CPOL0 SCK0 rxclk Figure 11.58 Clock Generation Block Diagram (USI0) The clock generation logic generates the base clock for the transmitter and receiver. The USI0 supports four modes of clock operation and those are normal asynchronous, double speed asynchronous, master synchronous and slave synchronous mode.

  • Page 199: Figure 11.59 Synchronous Mode Sck0 Timing (Usi0)

    MC96F6432 11.12.5 USI0 External Clock (SCK0) External clocking is used in the synchronous mode of operation. External clock input from the SCK0 pin is sampled by a synchronization logic to remove meta-stability. The output from the synchronization logic must be passed through an edge detector before it is used by the transmitter and receiver.

  • Page 200: Figure 11.60 Frame Format (Usi0)

    MC96F6432 11.12.7 USI0 UART Data format A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error detection. The UART supports all 30 combinations of the following as valid frame formats. - 1 start bit - 5, 6, 7, 8 or 9 data bits - no, even or odd parity bit...
  • Page 201 MC96F6432 11.12.9 USI0 UART Transmitter The UART transmitter is enabled by setting the TXE0 bit in USI0CR2 register. When the Transmitter is enabled, the TXD0 pin should be set to TXD0 function for the serial output pin of UART by the P4FSR[3:2]. The baud-rate, operation mode and frame format must be setup once before doing any transmission.
  • Page 202 MC96F6432 11.12.9.3 USI0 UART Parity Generator The parity generator calculates the parity bit for the serial frame data to be sent. When parity bit is enabled (USI0PM1=1), the transmitter control logic inserts the parity bit between the MSB and the first stop bit of the frame to be sent.
  • Page 203 MC96F6432 11.12.10.2 USI0 UART Receiver Flag and Interrupt The UART receiver has one flag that indicates the receiver state. The receive complete (RXC0) flag indicates whether there are unread data in the receive buffer. This flag is set when there are unread data in the receive buffer and cleared when the receive buffer is empty. If the receiver is disabled (RXE0=0), the receiver buffer is flushed and the RXC0 flag is cleared.

  • Page 204: Figure 11.61 Asynchronous Start Bit Sampling (Usi0)

    MC96F6432 11.12.10.5 USI0 Asynchronous Data Reception To receive asynchronous data frame, the UART includes a clock and data recovery unit. The clock recovery logic is used for synchronizing the internally generated baud-rate clock to the incoming asynchronous serial frame on the RXD0 pin. The data recovery logic samples and low pass filters the incoming bits, and this removes the noise of RXD0 pin.

  • Page 205: Figure 11.63 Stop Bit Sampling And Next Start Bit Sampling (Usi0)

    MC96F6432 The process for detecting stop bit is like clock and data recovery process. That is, if 2 or more samples of 3 center values have high level, correct stop bit is detected, else a frame error (FE0) flag is set. After deciding whether the first stop bit is valid or not, the Receiver goes to idle state and monitors the RXD0 line to check a valid high to low transition is detected (start bit detection).

  • Page 206: Table 11-20 Cpol0 Functionality

    MC96F6432 11.12.11 USI0 SPI Mode The USI0 can be set to operate in industrial standard SPI compliant mode. The SPI mode has the following features. - Full Duplex, Three-wire synchronous data transfer - Mater and Slave Operation - Supports all four SPI0 modes of operation (mode 0, 1, 2, and 3) - Selectable LSB first or MSB first data transfer - Double buffered transmit and receive - Programmable transmit bit rate...

  • Page 207: Figure 11.64 Usi0 Spi Clock Formats When Cpha0=0

    MC96F6432 SCK0 (CPOL0=0) SCK0 (CPOL0=1) SAMPLE MOSI0 MSB First … BIT7 BIT6 BIT2 BIT1 BIT0 LSB First … BIT0 BIT1 BIT5 BIT6 BIT7 MISO0 /SS0 OUT (MASTER) /SS0 IN (SLAVE) Figure 11.64 USI0 SPI Clock Formats when CPHA0=0 When CPHA0=0, the slave begins to drive its MISO0 output with the first data bit value when SS0 goes to active low.

  • Page 208: Figure 11.65 Usi0 Spi Clock Formats When Cpha0=1

    MC96F6432 SCK0 (CPOL0=0) SCK0 (CPOL0=1) SAMPLE MOSI0 … MSB First BIT7 BIT6 BIT2 BIT1 BIT0 … LSB First BIT0 BIT1 BIT5 BIT6 BIT7 MISO0 /SS0 OUT (MASTER) /SS0 IN (SLAVE) Figure 11.65 USI0 SPI Clock Formats when CPHA0=1 When CPHA0=1, the slave begins to drive its MISO0 output when SS0 goes active low, but the data is not defined until the first SCK0 edge.

  • Page 209: Figure 11.66 Usi0 Spi Block Diagram

    MC96F6432 11.12.13 USI0 SPI Block Diagram USI0BD Control SCLK Baud Rate Generator (fx: System clock) MASTER0 USI0SSEN Edge Detector SCK0 Control Controller FXCH0 RXE0 CPOL0 CPHA0 MISO0 Data Receive Shift Register Rx Control Recovery (RXSR) RXC0 RXCIE0 DOR0 Checker USI0DR[0], (Rx) LOOPS0 USI0DR[1], (Rx) To interrupt...

  • Page 210: Figure 11.67 Bit Transfer On The I2C-Bus (Usi0)

    MC96F6432 11.12.14 USI0 I2C Mode The USI0 can be set to operate in industrial standard serial communication protocols mode. The I2C mode uses 2 bus lines serial data line (SDA0) and serial clock line (SCL0) to exchange data. Because both SDA0 and SCL0 lines are open-drain output, each line needs pull-up resistor.

  • Page 211: Figure 11.68 Start And Stop Condition (Usi0)

    MC96F6432 11.12.16 USI0 I2C Start / Repeated Start / Stop One master can issue a START (S) condition to notice other devices connected to the SCL0, SDA0 lines that it will use the bus. A STOP (P) condition is generated by the master to release the bus lines so that other devices can use it.

  • Page 212: Figure 11.70 Acknowledge On The I2C-Bus (Usi0)

    MC96F6432 11.12.18 USI0 I2C Acknowledge The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA0 line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA0 line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse. When a slave is addressed by a master (Address Packet), and if it is unable to receive or transmit because it’s performing some real time function, the data line must be left HIGH by the slave.

  • Page 213: Figure 11.71 Clock Synchronization During Arbitration Procedure (Usi0)

    MC96F6432 Wait High Start High Counting Counting Fast Device SCLOUT High Counter Reset Slow Device SCLOUT SCL0 Figure 11.71 Clock Synchronization during Arbitration Procedure (USI0) Arbitration Process Device 1 loses Device1 outputs not adaped Arbitration High Device1 DataOut Device2 DataOut SDA0 on BUS SCL0 on BUS Figure 11.72 Arbitration Procedure of Two Masters (USI0)
  • Page 214 MC96F6432 Load SLA0+W into the USI0DR where SLA0 is address of slave device and W is transfer direction from the viewpoint of the master. For master transmitter, W is ‘0’. Note that USI0DR is used for both address and data. Configure baud rate by writing desired value to both USI0SCLR and USI0SCHR for the Low and High period of SCL0 line.

  • Page 215: Figure 11.73 Formats And States In The Master Transmitter Mode (Usi0)

    MC96F6432 Master S or Sr SLA+R Receiver SLA+W 0x86 0x22 STOP 0x0E 0x87 LOST DATA STOP LOST LOST& Slave Receiver (0x1D) 0x0F 0x1D 0x1F or Transmitter (0x1F) 0x46 0x22 STOP 0x0E Other master continues LOST Lost? Cont? From master to slave / 0x0F 0x47 Master command or Data Write...
  • Page 216 MC96F6432 11.12.20.2 USI0 I2C Master Receiver To operate I2C in master receiver, follow the recommended steps below. Enable I2C by setting USI0MS[1:0] bits in USI0CR1 and USI0EN bit in USI0CR2. This provides main clock to the peripheral. Load SLA0+R into the USI0DR where SLA is address of slave device and R is transfer direction from the viewpoint of the master.

  • Page 217: Figure 11.74 Formats And States In The Master Receiver Mode (Usi0)

    MC96F6432 This is the final step for master receiver function of I2C, handling STOP interrupt. The STOP bit indicates that data transfer between master and slave is over. To clear USI0ST2, write “0” to USI0ST2. After this, I2C enters idle state. The processes described above for master receiver operation of I2C can be depicted as the following figure.
  • Page 218 MC96F6432 11.12.20.3 USI0 I2C Slave Transmitter To operate I2C in slave transmitter, follow the recommended steps below. If the main operating clock (SCLK) of the system is slower than that of SCL0, load value 0x00 into USI0SDHR to make SDA0 change within one system clock period from the falling edge of SCL0. Note that the hold time of SDA0 is calculated by SDAH x period of SCLK where SDAH is multiple of number of SCLK coming from USI0SDHR.

  • Page 219: Figure 11.75 Formats And States In The Slave Transmitter Mode (Usi0)

    MC96F6432 The next figure shows flow chart for handling slave transmitter function of I2C. IDLE S or Sr SLA+R GCALL 0x97 0x1F LOST& 0x17 DATA 0x22 STOP 0x47 0x46 IDLE From master to slave / Interrupt, SCL0 line is held low Master command or Data Write From slave to master Interrupt after stop command...
  • Page 220 MC96F6432 11.12.20.4 USI0 I2C Slave Receiver To operate I2C in slave receiver, follow the recommended steps below. 1. If the main operating clock (SCLK) of the system is slower than that of SCL0, load value 0x00 into USI0SDHR to make SDA0 change within one system clock period from the falling edge of SCL0. Note that the hold time of SDA0 is calculated by SDAH x period of SCLK where SDAH is multiple of number of SCLK coming from USI0SDHR.

  • Page 221: Figure 11.76 Formats And States In The Slave Receiver Mode (Usi0)

    MC96F6432 The process can be depicted as following figure when I2C operates in slave receiver mode. IDLE S or Sr SLA+W GCALL 0x95 0x1D LOST& 0x15 DATA 0x20 STOP 0x44 0x45 IDLE From master to slave / Interrupt, SCL0 line is held low Master command or Data Write From slave to master Interrupt after stop command...

  • Page 222: Figure 11.77 Usi0 I2C Block Diagram

    MC96F6432 11.12.21 USI0 I2C Block Diagram IIC0IFR To interrupt block Slave Address Register USI0SAR RXACK0, GCALL0, Interrupt IIC0IE Generator TEND0, STOPD0, SSEL0, MLOST0, General Call And USI0GCE BUSY0, TMODE0 Address Detector Receive Shift Register SDA0 USI0DR, (Rx) (RXSR) SDA0 In/Out ACK Signal N-ch Controller...

  • Page 223: Table 11-21 Usi0 Register Map

    MC96F6432 11.12.22 Register Map Table 11-21 USI0 Register Map Name Address Default Description USI0BD USI0 Baud Rate Generation Register USI0DR USI0 Data Register USI0SDHR USI0 SDA Hold Time Register USI0SCHR USI0 SCL High Period Register USI0SCLR USI0 SCL Low Period Register USI0SAR USI0 Slave Address Register USI0CR1...
  • Page 224 MC96F6432 USI0DR (USI0 Data Register: For UART, SPI, and I2C mode) : E5H USI0DR7 USI0DR 6 USI0DR 5 USI0DR 4 USI0DR 3 USI0DR 2 USI0DR 1 USI0DR 0 Initial value : 00H USI0DR[7:0] The USI0 transmit buffer and receive buffer share the same I/O address with this DATA register.
  • Page 225 MC96F6432 USI0SCLR (USI0 SCL Low Period Register: For I2C mode) : E6H USI0SCLR7 USI0SCLR6 USI0SCLR5 USI0SCLR 4 USI0SCLR 3 USI0SCLR 2 USI0SCLR 1 USI0SCLR 0 Initial value : 3FH USI0SCLR[7:0] This register defines the high period of SCL0 when it operates in I2C master mode.
  • Page 226 MC96F6432 USI0CR1 (USI0 Control Register 1: For UART, SPI, and I2C mode) : D9H USI0S1 USI0S0 USI0MS1 USI0MS0 USI0PM1 USI0PM0 USI0S2 CPOL0 ORD0 CPHA0 Initial value : 00H USI0MS[1:0] Selects operation mode of USI0 USI0MS1 USI0MS0 Operation mode Asynchronous Mode (UART) Synchronous Mode I2C mode SPI mode...
  • Page 227 MC96F6432 USI0CR2 (USI0 Control Register 2: For UART, SPI, and I2C mode) : DAH DRIE0 TXCIE0 RXCIE0 WAKEIE0 TXE0 RXE0 USI0EN DBLS0 Initial value : 00H DRIE0 Interrupt enable bit for data register empty (only UART and SPI mode). Interrupt from DRE0 is inhibited (use polling) When DRE0 is set, request an interrupt TXCIE0 Interrupt enable bit for transmit complete (only UART and SPI mode).
  • Page 228 MC96F6432 USI0CR3 (USI0 Control Register 3: For UART, SPI, and I2C mode) : DBH MASTER0 LOOPS0 DISSCK0 USI0SSEN FXCH0 USI0SB USI0TX8 USI0RX8 Initial value : 00H MASTER0 Selects master or slave in SPI and synchronous mode operation and controls the direction of SCK0 pin Slave mode operation (External clock for SCK0).
  • Page 229 MC96F6432 USI0CR4 (USI0 Control Register 4: For I2C mode) : DCH – IIC0IFR TXDLYENB0 IIC0IE ACK0EN IMASTER0 STOPC0 STARTC0 – Initial value : 00H IIC0IFR This is an interrupt flag bit for I2C mode. When an interrupt occurs, this bit becomes ‘1’. This bit is cleared when all interrupt source bits in the USI0ST2 register are cleared to “0b”.
  • Page 230 MC96F6432 USI0ST1 (USI0 Status Register 1: For UART and SPI mode) : E1H DRE0 TXC0 RXC0 WAKE0 USI0RST DOR0 Initial value : 80H DRE0 The DRE0 flag indicates if the transmit buffer (USI0DR) is ready to receive new data. If DRE0 is ‘1’, the buffer is empty and ready to be written.
  • Page 231 MC96F6432 USI0ST2 (USI0 Status Register 2: For I2C mode) : E2H GCALL0 TEND0 STOPD0 SSEL0 MLOST0 BUSY0 TMODE0 RXACK0 Initial value : 00H (NOTE) GCALL0 This bit has different meaning depending on whether I2C is master or slave. When I2C is a master, this bit represents whether it received AACK (address ACK) from slave.

  • Page 232: Usi1 (Uart + Spi + I2C)

    MC96F6432 11.13 USI1 (UART + SPI + I2C) 11.13.1 Overview The USI1 consists of USI1 control register1/2/3/4, USI1 status register 1/2, USI1 baud-rate generation register, USI1 data register, USI1 SDA hold time register, USI1 SCL high period register, USI1 SCL low period register, and USI1 slave address register (USI1CR1, USI1CR2, USI1CR3, USI1CR4, USI1ST1, USI1ST2, USI1BD, USI1DR, USI1SDHR, USI1SCHR, USI1SCLR, USI1SAR).
  • Page 233 MC96F6432 11.13.2 USI1 UART Mode The universal synchronous and asynchronous serial receiver and transmitter (UART) is a highly flexible serial communication device. The main features are listed below. - Full Duplex Operation (Independent Serial Receive and Transmit Registers) - Asynchronous or Synchronous Operation - Baud Rate Generator - Supports Serial Frames with 5,6,7,8, or 9 Data Bits and 1 or 2 Stop Bits - Odd or Even Parity Generation and Parity Check Supported by Hardware...

  • Page 234: Figure 11.78 Usi1 Uart Block Diagram

    MC96F6432 11.13.3 USI1 UART Block Diagram Master SCK1 Control USI1MS[1:0] SCLK USI1BD (fx: System clock) To interrupt block Baud Rate Generator DBLS1 WAKEIE1 RXCIE1 Clock Sync Logic At Stop mode WAKE1 Low level RXC1 detector RXD1 Clock Recovery Control USI1S[2:0] RXE1 LOOPS1 Data...

  • Page 235: Figure 11.79 Clock Generation Block Diagram (Usi1)

    MC96F6432 11.13.4 USI1 Clock Generation USI1BD DBLS1 SCLK (USI1BD+1) Prescaling Up-Counter txclk SCLK MASTER1 Edge Sync Register USI1MS[1:0] Detector CPOL1 SCK1 rxclk Figure 11.79 Clock Generation Block Diagram (USI1) The clock generation logic generates the base clock for the transmitter and receiver. The USI1 supports four modes of clock operation and those are normal asynchronous, double speed asynchronous, master synchronous and slave synchronous mode.

  • Page 236: Figure 11.80 Synchronous Mode Sck1 Timing (Usi1)

    MC96F6432 11.13.5 USI1 External Clock (SCK1) External clocking is used in the synchronous mode of operation. External clock input from the SCK1 pin is sampled by a synchronization logic to remove meta-stability. The output from the synchronization logic must be passed through an edge detector before it is used by the transmitter and receiver.

  • Page 237: Figure 11.81 Frame Format (Usi1)

    MC96F6432 11.13.7 USI1 UART Data format A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error detection. The UART supports all 30 combinations of the following as valid frame formats. - 1 start bit - 5, 6, 7, 8 or 9 data bits - no, even or odd parity bit...
  • Page 238 MC96F6432 11.13.9 USI1 UART Transmitter The UART transmitter is enabled by setting the TXE1 bit in USI1CR2 register. When the Transmitter is enabled, the TXD1 pin should be set to TXD1 function for the serial output pin of UART by the P2FSR[1:0]. The baud-rate, operation mode and frame format must be setup once before doing any transmission.
  • Page 239 MC96F6432 11.13.9.3 USI1 UART Parity Generator The parity generator calculates the parity bit for the serial frame data to be sent. When parity bit is enabled (USI1PM1=1), the transmitter control logic inserts the parity bit between the MSB and the first stop bit of the frame to be sent.
  • Page 240 MC96F6432 11.13.10.2 USI1 UART Receiver Flag and Interrupt The UART receiver has one flag that indicates the receiver state. The receive complete (RXC1) flag indicates whether there are unread data in the receive buffer. This flag is set when there are unread data in the receive buffer and cleared when the receive buffer is empty. If the receiver is disabled (RXE1=1), the receiver buffer is flushed and the RXC1 flag is cleared.

  • Page 241: Figure 11.82 Asynchronous Start Bit Sampling (Usi1)

    MC96F6432 11.13.10.5 USI1 Asynchronous Data Reception To receive asynchronous data frame, the UART includes a clock and data recovery unit. The clock recovery logic is used for synchronizing the internally generated baud-rate clock to the incoming asynchronous serial frame on the RXD1 pin. The data recovery logic samples and low pass filters the incoming bits, and this removes the noise of RXD1 pin.

  • Page 242: Figure 11.84 Stop Bit Sampling And Next Start Bit Sampling (Usi1)

    MC96F6432 The process for detecting stop bit is like clock and data recovery process. That is, if 2 or more samples of 3 center values have high level, correct stop bit is detected, else a frame error (FE1) flag is set. After deciding whether the first stop bit is valid or not, the Receiver goes to idle state and monitors the RXD1 line to check a valid high to low transition is detected (start bit detection).

  • Page 243: Table 11-23 Cpol1 Functionality

    MC96F6432 11.13.11 USI1 SPI Mode The USI1 can be set to operate in industrial standard SPI compliant mode. The SPI mode has the following features. - Full Duplex, Three-wire synchronous data transfer - Mater and Slave Operation - Supports all four SPI0 modes of operation (mode 0, 1, 2, and 3) - Selectable LSB first or MSB first data transfer - Double buffered transmit and receive - Programmable transmit bit rate...

  • Page 244: Figure 11.85 Usi1 Spi Clock Formats When Cpha1=0

    MC96F6432 SCK1 (CPOL1=0) SCK1 (CPOL1=1) SAMPLE MOSI1 MSB First … BIT7 BIT6 BIT2 BIT1 BIT0 LSB First … BIT0 BIT1 BIT5 BIT6 BIT7 MISO1 /SS0 OUT (MASTER) /SS1 IN (SLAVE) Figure 11.85 USI1 SPI Clock Formats when CPHA1=0 When CPHA1=0, the slave begins to drive its MISO1 output with the first data bit value when SS1 goes to active low.

  • Page 245: Figure 11.86 Usi1 Spi Clock Formats When Cpha1=1

    MC96F6432 SCK1 (CPOL1=0) SCK1 (CPOL1=1) SAMPLE MOSI1 … MSB First BIT7 BIT6 BIT2 BIT1 BIT0 … LSB First BIT0 BIT1 BIT5 BIT6 BIT7 MISO1 /SS0 OUT (MASTER) /SS0 IN (SLAVE) Figure 11.86 USI1 SPI Clock Formats when CPHA1=1 When CPHA1=1, the slave begins to drive its MISO1 output when SS1 goes active low, but the data is not defined until the first SCK1 edge.

  • Page 246: Figure 11.87 Usi1 Spi Block Diagram

    MC96F6432 11.13.13 USI1 SPI Block Diagram USI1BD Control SCLK Baud Rate Generator (fx: System clock) MASTER1 USI1SSEN Edge Detector SCK1 Control Controller FXCH1 RXE1 CPOL1 CPHA1 MISO1 Data Receive Shift Register Rx Control Recovery (RXSR) RXC1 RXCIE1 DOR1 Checker USI1DR[0], (Rx) LOOPS1 USI1DR[1], (Rx) To interrupt...

  • Page 247: Figure 11.88 Bit Transfer On The I2C-Bus (Usi1)

    MC96F6432 11.13.14 USI1 I2C Mode The USI1 can be set to operate in industrial standard serial communication protocols mode. The I2C mode uses 2 bus lines serial data line (SDA1) and serial clock line (SCL1) to exchange data. Because both SDA1 and SCL1 lines are open-drain output, each line needs pull-up resistor.

  • Page 248: Figure 11.89 Start And Stop Condition (Usi1)

    MC96F6432 11.13.16 USI1 I2C Start / Repeated Start / Stop One master can issue a START (S) condition to notice other devices connected to the SCL1, SDA1 lines that it will use the bus. A STOP (P) condition is generated by the master to release the bus lines so that other devices can use it.

  • Page 249: Figure 11.91 Acknowledge On The I2C-Bus (Usi1)

    MC96F6432 11.13.18 USI1 I2C Acknowledge The acknowledge related clock pulse is generated by the master. The transmitter releases the SDA1 line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA1 line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse. When a slave is addressed by a master (Address Packet), and if it is unable to receive or transmit because it’s performing some real time function, the data line must be left HIGH by the slave.

  • Page 250: Figure 11.92 Clock Synchronization During Arbitration Procedure (Usi1)

    MC96F6432 Wait High Start High Counting Counting Fast Device SCLOUT High Counter Reset Slow Device SCLOUT SCL1 Figure 11.92 Clock Synchronization during Arbitration Procedure (USI1) Arbitration Process Device 1 loses Device1 outputs not adaped Arbitration High Device1 DataOut Device2 DataOut SDA1 on BUS SCL1 on BUS Figure 11.93 Arbitration Procedure of Two Masters (USI1)
  • Page 251 MC96F6432 Load SLA1+W into the USI1DR where SLA1 is address of slave device and W is transfer direction from the viewpoint of the master. For master transmitter, W is ‘0’. Note that USI1DR is used for both address and data. Configure baud rate by writing desired value to both USI1SCLR and USI1SCHR for the Low and High period of SCL1 line.

  • Page 252: Figure 11.94 Formats And States In The Master Transmitter Mode (Usi1)

    MC96F6432 Master S or Sr SLA+R Receiver SLA+W 0x86 0x22 STOP 0x0E 0x87 LOST DATA STOP LOST LOST& Slave Receiver (0x1D) 0x0F 0x1D 0x1F or Transmitter (0x1F) 0x46 0x22 STOP 0x0E Other master continues LOST Lost? Cont? From master to slave / 0x0F 0x47 Master command or Data Write...
  • Page 253 MC96F6432 11.13.20.2 USI1 I2C Master Receiver To operate I2C in master receiver, follow the recommended steps below. Enable I2C by setting USI1MS[1:0] bits in USI1CR1 and USI1EN bit in USI1CR2. This provides main clock to the peripheral. Load SLA1+R into the USI1DR where SLA is address of slave device and R is transfer direction from the viewpoint of the master.

  • Page 254: Figure 11.95 Formats And States In The Master Receiver Mode (Usi1)

    MC96F6432 This is the final step for master receiver function of I2C, handling STOP interrupt. The STOP bit indicates that data transfer between master and slave is over. To clear USI1ST2, write “0” to USI1ST2. After this, I2C enters idle state. The processes described above for master receiver operation of I2C can be depicted as the following figure.
  • Page 255 MC96F6432 11.13.20.3 USI1 I2C Slave Transmitter To operate I2C in slave transmitter, follow the recommended steps below. If the main operating clock (SCLK) of the system is slower than that of SCL1, load value 0x00 into USI1SDHR to make SDA1 change within one system clock period from the falling edge of SCL1. Note that the hold time of SDA1 is calculated by SDAH x period of SCLK where SDAH is multiple of number of SCLK coming from USI1SDHR.

  • Page 256: Figure 11.96 Formats And States In The Slave Transmitter Mode (Usi1)

    MC96F6432 The next figure shows flow chart for handling slave transmitter function of I2C. IDLE S or Sr SLA+R GCALL 0x97 0x1F LOST& 0x17 DATA 0x22 STOP 0x47 0x46 IDLE From master to slave / Interrupt, SCL1 line is held low Master command or Data Write From slave to master Interrupt after stop command...
  • Page 257 MC96F6432 11.13.20.4 USI1 I2C Slave Receiver To operate I2C in slave receiver, follow the recommended steps below. If the main operating clock (SCLK) of the system is slower than that of SCL1, load value 0x00 into USI1SDHR to make SDA1 change within one system clock period from the falling edge of SCL1. Note that the hold time of SDA1 is calculated by SDAH x period of SCLK where SDAH is multiple of number of SCLK coming from USI1SDHR.

  • Page 258: Figure 11.97 Formats And States In The Slave Receiver Mode (Usi1)

    MC96F6432 The process can be depicted as following figure when I2C operates in slave receiver mode. IDLE S or Sr SLA+W GCALL 0x95 0x1D LOST& 0x15 DATA 0x20 STOP 0x44 0x45 IDLE From master to slave / Interrupt, SCL1 line is held low Master command or Data Write From slave to master Interrupt after stop command...

  • Page 259: Figure 11.98 Usi1 I2C Block Diagram

    MC96F6432 11.13.21 USI1 I2C Block Diagram IIC1IFR To interrupt block Slave Address Register USI1SAR RXACK1, GCALL1, Interrupt IIC1IE Generator TEND1, STOPD1, SSEL1, MLOST1, General Call And USI1GCE BUSY1, TMODE1 Address Detector Receive Shift Register SDA1 USI1DR, (Rx) (RXSR) SDA1 In/Out ACK Signal N-ch Controller...

  • Page 260: Table 11-24 Usi1 Register Map

    MC96F6432 11.13.22 Register Map Table 11-24 USI1 Register Map Name Address Default Description USI1BD USI1 Baud Rate Generation Register USI1DR USI1 Data Register USI1SDHR USI1 SDA Hold Time Register USI1SCHR USI1 SCL High Period Register USI1SCLR USI1 SCL Low Period Register USI1SAR USI1 Slave Address Register USI1CR1...
  • Page 261 MC96F6432 USI1DR (USI1 Data Register: For UART, SPI, and I2C mode) : F5H USI1DR7 USI1DR 6 USI1DR 5 USI1DR 4 USI1DR 3 USI1DR 2 USI1DR 1 USI1DR 0 Initial value : 00H USI1DR[7:0] The USI1 transmit buffer and receive buffer share the same I/O address with this DATA register.
  • Page 262 MC96F6432 USI1SCLR (USI1 SCL Low Period Register: For I2C mode) : F6H USI1SCLR7 USI1SCLR6 USI1SCLR5 USI1SCLR 4 USI1SCLR 3 USI1SCLR 2 USI1SCLR 1 USI1SCLR 0 Initial value : 3FH USI1SCLR[7:0] This register defines the high period of SCL1 when it operates in I2C master mode.
  • Page 263 MC96F6432 USI1CR1 (USI1 Control Register 1: For UART, SPI, and I2C mode) : E9H USI1S1 USI1S0 USI1MS1 USI1MS0 USI1PM1 USI1PM0 USI1S2 CPOL1 ORD1 CPHA1 Initial value : 00H USI1MS[1:0] Selects operation mode of USI1 USI1MS1 USI1MS0 Operation mode Asynchronous Mode (UART) Synchronous Mode I2C mode SPI mode...
  • Page 264 MC96F6432 USI1CR2 (USI1 Control Register 2: For UART, SPI, and I2C mode) : EAH DRIE1 TXCIE1 RXCIE1 WAKEIE1 TXE1 RXE1 USI1EN DBLS1 Initial value : 00H DRIE1 Interrupt enable bit for data register empty (only UART and SPI mode). Interrupt from DRE1 is inhibited (use polling) When DRE1 is set, request an interrupt TXCIE1 Interrupt enable bit for transmit complete (only UART and SPI mode).
  • Page 265 MC96F6432 USI1CR3 (USI1 Control Register 3: For UART, SPI, and I2C mode) : EBH MASTER1 LOOPS1 DISSCK1 USI1SSEN FXCH1 USI1SB USI1TX8 USI1RX8 Initial value : 00H MASTER1 Selects master or slave in SPI and synchronous mode operation and controls the direction of SCK1 pin Slave mode operation (External clock for SCK1).
  • Page 266 MC96F6432 USI1CR4 (USI1 Control Register 4: For I2C mode) : ECH – IIC1IFR TXDLYENB1 IIC1IE ACK1EN IMASTER1 STOPC1 STARTC1 – Initial value : 00H IIC1IFR This is an interrupt flag bit for I2C mode. When an interrupt occurs, this bit becomes ‘1’. This bit is cleared when all interrupt source bits in the USI1ST2 register are cleared to “0b”.
  • Page 267 MC96F6432 USI1ST1 (USI1 Status Register 1: For UART and SPI mode) : F1H DRE1 TXC1 RXC1 WAKE1 USI1RST DOR1 Initial value : 80H DRE1 The DRE1 flag indicates if the transmit buffer (USI1DR) is ready to receive new data. If DRE1 is ‘1’, the buffer is empty and ready to be written.
  • Page 268 MC96F6432 USI1ST2 (USI1 Status Register 2: For I2C mode) : F2H GCALL1 TEND1 STOPD1 SSEL1 MLOST1 BUSY1 TMODE1 RXACK1 Initial value : 00H (NOTE) GCALL1 This bit has different meaning depending on whether I2C is master or slave. When I2C is a master, this bit represents whether it received AACK (address ACK) from slave.

  • Page 269: Table 11-25 Examples Of Usi0Bd And Usi1Bd Settings For Commonly Used Oscillator Frequencies

    MC96F6432 11.13.25 Baud Rate setting (example) Table 11-25 Examples of USI0BD and USI1BD Settings for Commonly Used Oscillator Frequencies fx=1.00MHz fx=1.8432MHz fx=2.00MHz Baud Rate USI0BD/USI1BD ERROR USI0BD/USI1BD ERROR USI0BD/USI1BD ERROR 2400 0.2% 0.0% 0.2% 4800 0.2% 0.0% 0.2% 9600 -7.0% 0.0% 0.2% 14.4k...

  • Page 270: Lcd Driver

    MC96F6432 11.14 LCD Driver 11.14.1 Overview The LCD driver is controlled by the LCD Control Register (LCDCRH/L). The LCLK[1:0] determines the frequency of COM signal scanning of each segment output. A RESET clears the LCD control register LCDCRH and LCDCRL values to logic ‘0’. The LCD display can continue operating during IDLE and STOP modes if a sub-frequency clock is used as LCD clock source.

  • Page 271: Figure 11.99 Lcd Circuit Block Diagram

    MC96F6432 11.14.2 LCD Display RAM Organization Display data are stored to the display data area in the external data memory. The display data which stored to the display external data area (address 0000H-001AH) are read automatically and sent to the LCD driver by the hardware. The LCD driver generates the segment signals and common signals in accordance with the display data and drive method.

  • Page 272: Figure 11.100 Lcd Signal Waveforms (1/2Duty, 1/2Bias)

    MC96F6432 11.14.3 LCD Signal Waveform COM0 SEG0 1 Frame COM1 VLC0 COM0 VLC2(VLC1, VLC3) SEG3 SEG1 SEG2 VLC0 COM1 VLC2(VLC1, VLC3) VLC0 VLC2(VLC1, VLC3) SEG0 VLC0 SEG1 VLC2(VLC1, VLC3) +VLC0 +VLC2(VLC1, VLC3) COM0-SEG0 -VLC2(VLC1, VLC3) -VLC0 Figure 11.100 LCD Signal Waveforms (1/2Duty, 1/2Bias) June 22, 2018 Ver.

  • Page 273: Figure 11.101 Lcd Signal Waveforms (1/3Duty, 1/3Bias)

    MC96F6432 SEG1 SEG3 SEG2 COM0 1 Frame VLC0 VLC1 COM1 COM0 VLC2(VLC3) COM2 VLC0 VLC1 COM1 VLC2(VLC3) VLC0 VLC1 COM2 VLC2(VLC3) VLC0 VLC1 SEG1 VLC2(VLC3) VLC0 VLC1 SEG2 VLC2(VLC3) +VLC0 +VLC1 +VLC2(VLC3) COM0-SEG1 -VLC2(VLC3) -VLC1 -VLC0 Figure 11.101 LCD Signal Waveforms (1/3Duty, 1/3Bias) June 22, 2018 Ver.

  • Page 274: Figure 11.102 Lcd Signal Waveforms (1/4Duty, 1/3Bias)

    MC96F6432 SEG3 SEG2 COM0 1 Frame COM1 VLC0 VLC1 COM2 COM0 VLC2(VLC3) COM3 VLC0 VLC1 COM1 VLC2(VLC3) VLC0 VLC1 COM2 VLC2(VLC3) VLC0 VLC1 SEG2 VLC2(VLC3) VLC0 VLC1 SEG3 VLC2(VLC3) +VLC0 +VLC1 +VLC2(VLC3) COM0-SEG2 -VLC2(VLC3) -VLC1 -VLC0 Figure 11.102 LCD Signal Waveforms (1/4Duty, 1/3Bias) June 22, 2018 Ver.

  • Page 275: Figure 11.103 Lcd Signal Waveforms (1/8Duty, 1/4Bias)

    MC96F6432 COM0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 COM1 COM2 COM3 COM4 1 Frame COM5 COM6 VLC0 COM7 VLC1 COM0 VLC2 VLC3 VLC0 VLC1 COM1 VLC2 VLC3 VLC0 VLC1 VLC2 COM2 VLC3 VLC0 VLC1...

  • Page 276: Figure 11.104 Internal Resistor Bias Connection

    MC96F6432 11.14.4 LCD Voltage Dividing Resistor Connection (1/ 2 Bias, 160K ohm) (1/ 2 Bias, 80K ohm ) VLCD VLCD VLC0 VLC1 VLC2 VLC3 VLC0 VLC1 VLC2 VLC3 DISP DISP LCTEN LCTEN VLC0 VLC1 VLC2 VLC3 VLC0 VLC1 VLC2 VLC3 (1/ 3 BIAS) (1/ 4 BIAS) VLCD...

  • Page 277: Figure 11.105 External Resistor Bias Connection

    MC96F6432 (1/ 2 BIAS) VLCD DISP LCTEN VLC0 VLC1 VLC2 VLC3 R’ R’ (1/ 3 BIAS) (1/ 4 BIAS) VLCD VLCD DISP DISP LCTEN LCTEN VLC0 VLC1 VLC2 VLC3 VLC0 VLC1 VLC2 VLC3 R’ R’ R’ R’ R’ R’ R’ NOTES) 1.

  • Page 278: Figure 11.106 Lcd Circuit Block Diagram

    MC96F6432 11.14.5 Block Diagram Port Latch SEG/Port Driver Display COM/Port Driver fLCD Timing LCDCRL Controller LCDCRH VLC0 LCD Bias VLC1 Voltage VLC2 Generator Contrast LCDCCR Controller VLC3 Figure 11.106 LCD Circuit Block Diagram 11.14.6 Register Map Table 11-26 LCD Register Map Name Address Default...
  • Page 279 MC96F6432 11.14.8 Register Description for LCD Driver LCDCRH (LCD Driver Control High Register) : 9AH – – – – – COMCHG LCDDR DISP – – – – – Initial value : 00H COMCHG Common Signal Output Port Change Control COM0 – COM3 signals are outputted through the P37-P34 COM0 –...

  • Page 280: Table 11-27 Lcd Frame Frequency

    MC96F6432 LCDCRL (LCD Driver Control Low Register) : 99H – – DBS3 DBS2 DBS1 DBS0 LCLK1 LCK0 – – R./W Initial value : 00H DBS[3:0] LCD Duty and Bias Select (NOTE) DBS3 DBS2 DBS1 DBS0 Description 1/8Duty, 1/4Bias (60k ohm) 1/6Duty, 1/4Bias (60k ohm) 1/5Duty, 1/3Bias (60k ohm) 1/4Duty, 1/3Bias (60k ohm)
  • Page 281 MC96F6432 LCDCCR (LCD Driver Contrast Control Low Register) : 9BH – – – LCTEN VLCD3 VLCD VLCD1 VLCD0 – – – Initial value : 00H LCTEN Control LCD Driver Contrast LCD Driver Contrast disable LCD Driver Contrast enable VLCD[3:0] VLC0 Voltage Control when the contrast is enabled VLCD3 VLCD 2 VLCD 1 VLCD 0...

  • Page 282: Power Down Operation

    MC96F6432 12. Power Down Operation 12.1 Overview The MC96F6432 has two power-down modes to minimize the power consumption of the device. In power down mode, power consumption is reduced considerably. The device provides three kinds of power saving functions, Main-IDLE, Sub-IDLE and STOP mode. In three modes, program is stopped. 12.2 Peripheral Operation in IDLE/STOP Mode Table 12-1 Peripheral Operation during Power Down Mode Peripheral...

  • Page 283: Idle Mode

    MC96F6432 12.3 IDLE Mode The power control register is set to ‘01h’ to enter the IDLE Mode. In this mode, the internal oscillation circuits remain active. Oscillation continues and peripherals are operated normally but CPU stops. It is released by reset or interrupt.

  • Page 284: Stop Mode

    MC96F6432 12.4 STOP Mode The power control register is set to ‘03H’ to enter the STOP Mode. In the stop mode, the selected oscillator, system clock and peripheral clock is stopped, but watch timer can be continued to operate with sub clock. With the clock frozen, all functions are stopped, but the on-chip RAM and control registers are held.

  • Page 285: Release Operation Of Stop Mode

    MC96F6432 12.5 Release Operation of STOP Mode After STOP mode is released, the operation begins according to content of related interrupt register just before STOP mode start (Figure 12.3). If the global interrupt Enable Flag (IE.EA) is set to `1`, the STOP mode is released by the interrupt which each interrupt enable flag = `1` and the CPU jumps to the relevant interrupt service routine.

  • Page 286: Table 12-2 Power Down Operation Register Map

    MC96F6432 12.5.1 Register Map Table 12-2 Power Down Operation Register Map Name Address Default Description PCON Power Control Register 12.5.2 Power Down Operation Register Description The power down operation register consists of the power control register (PCON). 12.5.3 Register Description for Power Down Operation PCON (Power Control Register) : 87H –...

  • Page 287: Reset

    MC96F6432 13. RESET 13.1 Overview The following is the hardware setting value. Table 13-1 Reset State On Chip Hardware Initial Value Program Counter (PC) 0000h Accumulator Stack Pointer (SP) Peripheral Clock Control Register Refer to the Peripheral Registers 13.2 Reset Source The MC96F6432 has five types of reset sources.

  • Page 288: Reset Noise Canceller

    MC96F6432 13.4 RESET Noise Canceller The Figure 13.2 is the noise canceller diagram for noise cancellation of RESET. It has the noise cancellation value of about 2us (@V =5V) to the low input of system reset. t < T t < T t >...

  • Page 289: Figure 13.5 Configuration Timing When Power-On

    MC96F6432 Counting for config read start after POR is released Internal nPOR PAD RESETB “H” LVR_RESETB .. 27 28 BIT (for Config) 00 01 02 03 BIT (for Reset) 1us X 256 X 28h = about 10ms Config Read 1us X 4096 X 4h = about 16ms RESET_SYSB INT-OSC (8MHz) INT-OSC 8MHz/8...

  • Page 290: Table 13-2 Boot Process Description

    MC96F6432 Table 13-2 Boot Process Description Process Description Remarks ① -No Operation ② -1st POR level Detection -about 1.4V - (INT-OSC 8MHz/8)x256x28h Delay section (=10ms) ③ -Slew Rate >= 0.05V/ms -VDD input voltage must rise over than flash operating voltage for Config read -about 1.5V ~ 1.6V ④...

  • Page 291: External Resetb Input

    MC96F6432 13.6 External RESETB Input The External RESETB is the input to a Schmitt trigger. If RESETB pin is held with low for at least 10us over within the operating voltage range and stable oscillation, it is applied and the internal state is initialized. After reset state becomes ‘1’, it needs the stabilization time with 16ms and after the stable state, the internal RESET becomes ‘1’.

  • Page 292: Brown Out Detector Processor

    MC96F6432 13.7 Brown Out Detector Processor The MC96F6432 has an On-chip brown-out detection circuit (BOD) for monitoring the VDD level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by LVRVS[3:0] bit to be 1.60V, 2.00V, 2.10V, 2.20V,2.32V, 2.44V, 2.59V, 2.75V, 2.93V, 3.14V, 3.38V, 3.67V, 4.00V, 4.40V.

  • Page 293: Lvi Block Diagram

    MC96F6432 “H” “H” Internal nPOR “H” PAD RESETB LVR_RESETB ..27 28 BIT (for Config) 00 01 02 BIT (for Reset) 1us X 256 X 28h = about 10ms Config Read 1us X 4096 X 4h = about 16ms RESET_SYSB Main OSC Off INT-OSC (8MHz)

  • Page 294: Register Map

    MC96F6432 13.9 Register Map Table 13-3 Reset Operation Register Map Name Address Default Description RSTFR Reset Flag Register LVRCR Low Voltage Reset Control Register LVICR Low Voltage Indicator Control Register 13.10 Reset Operation Register Description The reset control register consists of the reset flag register (RSTFR), low voltage reset control register (LVRCR), and low voltage indicator control register (LVICR).
  • Page 295 MC96F6432 LVRCR (Low Voltage Reset Control Register) : D8H – – LVRST LVRVS3 LVRVS2 LVRVS1 LVRVS0 LVREN – – Initial value : 00H LVRST LVR Enable when Stop Release Not effect at stop release LVR enable at stop release NOTES) When this bit is ‘1’, the LVREN bit is cleared to ‘0’...
  • Page 296 MC96F6432 LVICR (Low Voltage Indicator Control Register) : 86H – – LVIF LVIEN LVILS3 LVILS2 LVILS1 LVILS0 – – Initial value : 00H LVIF Low Voltage Indicator Flag Bit No detection Detection LVIEN LVI Enable/Disable Disable Enable LVILS[3:0] LVI Level Select LVILS3 LVILS2 LVILS1 LVILS0...

  • Page 297: On-Chip Debug System

    MC96F6432 14. On-chip Debug System 14.1 Overview 14.1.1 Description On-chip debug system (OCD) of MC96F6432 can be used for programming the non-volatile memories and on- chip debugging. Detail descriptions for programming via the OCD interface can be found in the following chapter. Figure 14.1 shows a block diagram of the OCD interface and the On-chip Debug system.

  • Page 298: Two-Pin External Interface

    MC96F6432 14.2 Two-Pin External Interface 14.2.1 Basic Transmission Packet • 10-bit packet transmission using two-pin interface. • 1-packet consists of 8-bit data, 1-bit parity and 1-bit acknowledge. • Parity is even of ‘1’ for 8-bit data in transmitter. • Receiver generates acknowledge bit as ‘0’ when transmission for 8-bit data and its parity has no error. •...

  • Page 299: Figure 14.3 Data Transfer On The Twin Bus

    MC96F6432 14.2.2 Packet Transmission Timing 14.2.2.1 Data Transfer DSDA acknowledgement acknowledgement signal from receiver signal from receiver DSCL START STOP Figure 14.3 Data Transfer on the Twin Bus 14.2.2.2 Bit Transfer DSDA DSCL data line change stable: of data data valid allowed except Start and Stop Figure 14.4 Bit Transfer on the Serial Bus...

  • Page 300: Figure 14.5 Start And Stop Condition

    MC96F6432 14.2.2.3 Start and Stop Condition DSDA DSDA DSCL DSCL START condition STOP condition Figure 14.5 Start and Stop Condition 14.2.2.4 Acknowledge Bit Data output by transmitter no acknowledge Data output By receiver acknowledge DSCL from master clock pulse for acknowledgement Figure 14.6 Acknowledge on the Serial Bus June 22, 2018 Ver.

  • Page 301: Figure 14.7 Clock Synchronization During Wait Procedure

    MC96F6432 Acknowledge bit Acknowledge bit transmission transmission Minimum wait HIGH start HIGH 500ns Host PC DSCL OUT Start wait Target Device DSCL OUT minimum 1 T SCLK for next byte Maximum 5 T SCLK transmission DSCL Internal Operation Figure 14.7 Clock Synchronization during Wait Procedure June 22, 2018 Ver.

  • Page 302: Figure 14.8 Connection Of Transmission

    MC96F6432 14.2.3 Connection of Transmission Two-pin interface connection uses open-drain (wire-AND bidirectional I/O). pull resistors DSDA(Debugger Serial Data Line) DSCL(Debugger Serial Clock Line) DSCL DSDA DSCL DSDA DSDA DSDA DSCL DSCL Target Device(Slave) Host Machine(Master) Current source for DSCL to fast 0 to 1 transition in high speed mode Figure 14.8 Connection of Transmission June 22, 2018 Ver.

  • Page 303: Flash Memory

    MC96F6432 15. Flash Memory 15.1 Overview 15.1.1 Description MC96F6432 incorporates flash memory to which a program can be written, erased, and overwritten while mounted on the board. The flash memory can be read by ‘MOVC’ instruction and it can be programmed in OCD, serial ISP mode or user program mode.

  • Page 304: Figure 15.1 Flash Program Rom Structure

    MC96F6432 15.1.2 Flash Program ROM Structure 07FFFH Sector 511 07FC0H 07FC0H 07FBFH Sector 510 07F80H 07F80H 07F7FH Sector 509 07F40H 07F40H 07F3FH Sector 508 Flash Sector Address Address Sector 2 00080H 00080H 0007FH Sector 1 00040H 00040H 0003FH Sector 0 00000H 00000H 64bytes...

  • Page 305: Table 15-1Flash Memory Register Map

    MC96F6432 15.1.3 Register Map Table 15-1Flash Memory Register Map Name Address Default Description FSADRH Flash Sector Address High Register FSADRM Flash Sector Address Middle Register FSADRL Flash Sector Address Low Register FIDR Flash Identification Register FMCR Flash Mode Control Register 15.1.4 Register Description for Flash Memory Control and Status Flash control register consists of the flash sector address high register (FSADRH), flash sector address middle register (FSADRM), flash sector address low register (FSADRL), flash identification register (FIDR), and flash...
  • Page 306 MC96F6432 15.1.5 Register Description for Flash FSADRH (Flash Sector Address High Register) : FAH – – – – FSADRH3 FSADRH 2 FSADRH1 FSADRH0 – – – – Initial value : 00H FSADRH[3:0] Flash Sector Address High FSADRM (Flash Sector Address Middle Register) : FBH FSADRM7 FSADRM6 FSADRM5...
  • Page 307 MC96F6432 FMCR (Flash Mode Control Register) : FEH – – – – FMBUSY FMCR2 FMCR1 FMCR0 – – – – Initial value : 00H FMBUSY Flash Mode Busy Bit. This bit will be used for only debugger. No effect when “1” is written Busy FMCR[2:0] Flash Mode Control Bits.
  • Page 308 MC96F6432 15.1.6 Serial In-System Program (ISP) Mode Serial in-system program uses the interface of debugger which uses two wires. Refer to chapter 14 in details about debugger 15.1.7 Protection Area (User program mode) MC96F6432 can program its own flash memory (protection area). The protection area can not be erased or programmed.
  • Page 309 MC96F6432 15.1.8 Erase Mode The sector erase program procedure in user program mode 1. Page buffer clear (FMCR=0x01) 2. Write ‘0’ to page buffer 3. Set flash sector address register (FSADRH/FSADRM/FSADRL). 4. Set flash identification register (FIDR). (Note) 5. Check the UserID for to prevent the invalid work 6.
  • Page 310 MC96F6432 The Byte erase program procedure in user program mode 1. Page buffer clear (FMCR=0x01) 2. Write ‘0’ to page buffer 3. Set flash sector address register (FSADRH/FSADRM/FSADRL). 4. Set flash identification register (FIDR). (Note) 5. Check the UserID for to prevent the invalid work 6.
  • Page 311 MC96F6432 15.1.9 Write Mode The sector Write program procedure in user program mode 1. Page buffer clear (FMCR=0x01) 2. Write data to page buffer 3. Set flash sector address register (FSADRH/FSADRM/FSADRL). 4. Set flash identification register (FIDR). (Note1) 5. Check the UserID for to prevent the invalid work 6.
  • Page 312 MC96F6432 The Byte Write program procedure in user program mode 1. Page buffer clear (FMCR=0x01) 2. Write data to page buffer 3. Set flash sector address register (FSADRH/FSADRM/FSADRL). 4. Set flash identification register (FIDR). (Note1). 5. Check the UserID for to prevent the invalid work 6.
  • Page 313 MC96F6432 15.1.10 Protection for Invalid Erase/Write It should be taken care to the flash erase/write programming in code. You must make preparations for invalid jump to the flash erase/write code by malfunction, noise, and power off. Note) For more information, please refer to the appendix “Flash Protection for Invalid Erase/Write”. 1.
  • Page 314 MC96F6432 3. The flash sector address (FSADRH/FSADRM/FSADRL) should always keep the address of the flash which is used for data area. For example, The FSADRH/FSADRM is always 0x00/0x7f” if 0x7f00 to 0x7fff is used for data. 4. Overview of main CALL Work1 CALL...

  • Page 315: Figure 15.2 Flow Of Protection For Invalid Erase/Write

    MC96F6432 15.1.10.1 Flow of Protection for Invalid Erase/Write Start Work1 Decide to write/erase on Set Flags flash Work2 Match Check the flag for UserID Write UserID1/2/3 Work3 Check the UserID for Match Write/Erase Flash write/erase flash Clear the Flag Clear UserID1/2/3 Note) This method is helpful to reduce the case for flash memory to be erased by malfunction, noise and power off.
  • Page 316 MC96F6432 15.1.11 Read Mode The Reading program procedure in user program mode 1. Load receive data from flash memory on MOVC instruction by indirectly addressing mode. Program Tip – reading A,#0 DPH,#0x7F DPL,#0x40 ;flash memory address MOVC A,@A+DPTR ;read data from flash memory 15.1.12 Code Write Protection Mode The Code Write Protection program procedure in user program mode 1.

  • Page 317: Configure Option

    MC96F6432 16. Configure Option 16.1 Configure Option Control The data for configure option should be written in the configure option area (003EH – 003FH) by programmer (Writer tools). CONFIGURE OPTION 1 : ROM Address 003FH – – – – – RSTS Initial value : 00H Code Read Protection...

  • Page 318: Appendix

    MC96F6432 17. APPENDIX A. Instruction Table Instructions are either 1, 2 or 3 bytes long as listed in the ‘Bytes’ column below. Each instruction takes either 1, 2 or 4 machine cycles to execute as listed in the following table. 1 machine cycle comprises 2 system clock cycles.
  • Page 319 MC96F6432 XRL A,#data Exclusive-OR immediate to A XRL dir,A Exclusive-OR A to direct byte XRL dir,#data Exclusive-OR immediate to direct byte CLR A Clear A CPL A Complement A SWAP A Swap Nibbles of A RL A Rotate A left RLC A Rotate A left through carry RR A...
  • Page 320 MC96F6432 ORL C,bit OR direct bit to carry ORL C,/bit OR direct bit inverse to carry MOV C,bit Move direct bit to carry MOV bit,C Move carry to direct bit BRANCHING Mnemonic Description Bytes Cycles Hex code ACALL addr 11 Absolute jump to subroutine 11→F1 LCALL addr 16...
  • Page 321 MC96F6432 B. Instructions on how to use the input port.  Error occur status  Using compare jump instructions with input port, it could cause error due to the timing conflict inside the MCU.  Compare jump Instructions which cause potential error used with input port condition: bit, rel ;...
  • Page 322 MC96F6432  If you use input bit port for compare jump instruction, you have to copy the input port as internal paramet er or carry bit and then use compare jump instruction. zzz: C,080.0 ; input port use internal parameter bit tt;...
  • Page 323 MC96F6432 C. Flash Protection for Invalid Erase/Write  Overview This is example to prevent changing code or data in flash by abnormal operation(noise, unstable power, malfunction, etc…).  How to protect the flash • Divide into decision and execution to Erase/Write in flash. Check the program sequence from decision to execution in order of precedence about Erase/Write.
  • Page 324 MC96F6432  Flowchart Start Initial ① Set LVR/LVI more than 2.0V Start Main Loop Working ③ Write Flash? Set User_ID1 ② Working ③ Check User_ID1? Set User_ID2 Working Check User_ID2? Set User_ID3 ③ Working Write Flash Set FSADDRH/M/L ④ Set FIDR ⑤...
  • Page 325 • ⑥ Initialize Flags Initialize User_ID1/2/3 Set Flash Sector Address to Dummy Address • Sample Source Refer to the ABOV homepage. It is created based on the MC97F2664. Each product should be modified according to the Page Buffer Size and Flash Size ...
  • Page 326 MC96F6432 D. ESD Test Method ESD Test Description ESD Testing was perform on Zapmaster system using the Human-Body-Model (H.B.M) and Machine-Model (M.M) according JESD22-A114F and EIA/JESD22-A115-A respectively. Human-Body-Model stresses devices by sudden application of a high voltage supplied by a 100pF capacitor through 1.5k Ohms resistance. Machine- Model stresses devices by sudden application of a high voltage supplied by a 200pF capacitor through very low (0 Ohm) resistance.
  • Page 327 MC96F6432 ESD Test Method : I/O (Pin-to-Pin) Mode I/O pins are zapped, pin by pin. I/O pins which are not zapped are grounded. All power pins (VDD and VSS) are floated. ESD Class HBM (Human-Body-Model) : 2 M.M. (Machine-Model) : B June 22, 2018 Ver.

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