MC97F60128 ABOV Semiconductor Co., Ltd. Revision history Version Date Revision list 2013.12.24 Published this book. 2014.09.02 Added Note at LCD Block Diagram. Modify contents of Buzzer 2014.09.19 Added Note about the timer clock Modify contents of T7/8 PWM Modify contents of Buzzer 2014.09.22...
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The information, diagrams and other data in this manual are correct and reliable; However, ABOV Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
ABOV Semiconductor does not provide compiler. It is recommended that you consult a compier provider. The MC97F60128 core is Mentor 8051 and the ROM size is smaller than 128 Kbytes.Therefore, developer can use the standard 8051 compiler from other providers.
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MC97F60128 ABOV Semiconductor Co., Ltd. OCD emulator : OCD-II It can write code to MCU device too, because OCD debugger supports ISP (In System Programming).It does not require additional H/W, except developer’s target system. Gang programmer : E-GANG4 and E-GANG6 It can run PC controlled mode.
ABOV Semiconductor Co., Ltd. MTP programming 1.4.1 Overview The program memory of MC97F60128 is MTP Type. This flash is accessed by serial data format. There are five pins(DSCL, DSDA, RUNFLAG, VDD, VSS) for programming/reading the flash. During programming Main chip...
MC97F60128 ABOV Semiconductor Co., Ltd. 1.4.3 Circuit Design Guide At the FLASH programming, the programming tool needs 5 signal lines that are DSCL, DSDA, RUNFLAG, VDD and VSS. When you design the PCB circuits, you should consider the usage of these signal lines for the on-board programming.
MC97F60128 ABOV Semiconductor Co., Ltd. 5. Pin Description Function @RESET Shared with Name AN0/EINT0/BLNK AN1/EINT1 Port 0 is a bit-programmable I/O port which can be AN2/EINT2 configured as a schmitt-trigger input, a push-pull AN3/EINT3 output or an open-drain output. Input A pull-up resistor can be specified in 1-bit unit.
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MC97F60128 ABOV Semiconductor Co., Ltd. Function @RESET Shared with Name SEG18/RXD4 SEG19/TXD4 SEG20/RXD3 Port 5 is a bit-programmable I/O port which can be SEG21/TXD3 configured as a schmitt-trigger input, a push-pull Input output or an open-drain output. SEG22/SS1 A pull-up resistor can be specified in 1-bit unit.
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MC97F60128 ABOV Semiconductor Co., Ltd. Function @RESET Shared with Name Port B is a bit-programmable I/O port which can be SEG26 configured as an input, a push-pull output or an SEG27 open-drain output.. Input A pull-up resistor can be specified in 1-bit unit.
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MC97F60128 ABOV Semiconductor Co., Ltd. PIN Name Function @RESET Shared with – RESETB System reset pin with a pull-up resistor Input (Note 4) DSDA On chip debugger data input/output Input P15/SEG63/EINT9/EC6 (Note 4) DSCL On chip debugger clock input Input...
MC97F60128 ABOV Semiconductor Co., Ltd. 6. Port Structures General Purpose I/O Port Level Shift (1.8V to ExtVDD) Level Shift (ExtVDD to 1.8V) PULL-UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE SUB-FUNC DIRECTION DIRECTION REGISTER CMOS or...
MC97F60128 ABOV Semiconductor Co., Ltd. External Interrupt I/O Port Level Shift (1.8V to ExtVDD) Level Shift (ExtVDD to 1.8V) PULL-UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB-FUNC DATA OUTPUT SUB-FUNC ENABLE SUB-FUNC DIRECTION DIRECTION REGISTER EXTERNAL INTERRUPT POLARITY REG. INTERRUPT...
MC97F60128 ABOV Semiconductor Co., Ltd. 7. Electrical Characteristics Absolute Maximum Ratings Note Parameter Symbol Rating Unit – Supply Voltage -0.3~+6.5 -0.3~VDD+0.3 Voltage on any pin with respect to VSS -0.3~VDD+0.3 Maximum current output sourced by (I per I/O pin) Normal Voltage Pin Maximum current ( ∑...
MC97F60128 ABOV Semiconductor Co., Ltd. 7.11 DC Characteristics = -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V, f = 12MHz) Parameter Symbol Conditions Unit – P0–P6, P9, PA, RESETB 0.8VDD – All input pins except VIH1 0.7VDD Input High Voltage P20, P33, P34, P37;...
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MC97F60128 ABOV Semiconductor Co., Ltd. All supply current items don’t include the current of an internal watch-dog timer RC (WDTRC) oscillator and a peripheral block. All supply current items include the current of the power-on reset (POR) block.
MC97F60128 ABOV Semiconductor Co., Ltd. 7.14 UART0/1/2/3/4 Characteristics =-40°C ~ +85°C, VDD=1.8V ~ 5.5V, f =11.1MHz) Parameter Symbol Unit Serial port clock cycle time 1250 x 16 1650 – Output data setup to clock rising edge x 13 – –...
MC97F60128 ABOV Semiconductor Co., Ltd. 7.16 Data Retention Voltage in Stop Mode =-40°C ~ +85°C, VDD=1.8V ~ 5.5V) Parameter Symbol Conditions Unit – – Data retention supply voltage DDDR VDDR= 1.8V, – – Data retention supply current DDDR = 25°C), Stop mode...
MC97F60128 ABOV Semiconductor Co., Ltd. 7.23 Operating Voltage Range =0.4 to 10MHz) =0.4 to 10MHz) 12.0MHz 12.0MHz 4.2MHz 4.2MHz 0.4MHz 0.4MHz Supply voltage for Ceramic (V) Supply voltage for Crystal (V) Figure 7.14 Operating Voltage Range (MAIN OSC) =32 to 38KHz) 32.768KHz...
MC97F60128 ABOV Semiconductor Co., Ltd. 7.24 Recommended Circuit and Layout This 0.1uF capacitor should be within 1cm from the VDD pin of MCU on the VDD VCC PCB layout. VDD1 DC Power 0.1uF 0.1uF VSS1 The MCU power line (VDD and VSS)
MC97F60128 ABOV Semiconductor Co., Ltd. 7.25 Recommended Circuit and Layout with SMPS Power SMPS Side MCU Side SMPS Option 1. The C1 capacitor is to flatten out the voltage of the SMPS power, VCC. √ Recommended C1: 470uF/25V more. 2. The R1 and C2 are the RC filter for VDD and suppress the ripple of VCC.
MC97F60128 ABOV Semiconductor Co., Ltd. 7.26 Typical Characteristics These graphs and tables provided in this section are only for design guidance and are not tested or guaranteed. In graphs or tables some data are out of specified operating range (e.g. out of specified VDD range). This is only for information and devices are guaranteed to operate properly only within the specified range.
DPTR register. Program Memory can be up to 64K bytes of Program memory in a bank. MC97F60128 provides on-chip 128 Kbytes of the ISP type flash program memory, which can be read and written to. Internal data memory (IRAM) is 256 bytes and it includes the stack area.
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MC97F60128 ABOV Semiconductor Co., Ltd. FFFFH FFFFH Total 64K Bytes 128k Bytes 64K Bytes Bank 1 0000H Bank 0 Figure 8.1 Program Memory NOTE) 128 Kbytes Including Interrupt Vector Region...
MC97F60128 ABOV Semiconductor Co., Ltd. External Data Memory MC97F60128 has 8,192 bytes XRAM and XSFR. This area has no relation with RAM/FLASH. It can be read and written to through SFR with 8-bit unit. 40CFH Extended Special Function Registers 208 Bytes...
MC97F60128 ABOV Semiconductor Co., Ltd. 8.4.2 SFR Map @Reset Address Function Symbol P0 Data Register Stack Pointer Data Pointer Register Low Data Pointer Register High Data Pointer Register Low 1 DPL1 Data Pointer Register High 1 DPH1 – – Low Voltage Indicator Control Register LVICR –...
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MC97F60128 ABOV Semiconductor Co., Ltd. @Reset Address Function Symbol P4 Data Register – – – P9 Data Register – – – – Extended Operation Register – – – PA Data Register – – – – – PB Data Register –...
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MC97F60128 ABOV Semiconductor Co., Ltd. @Reset Address Function Symbol P7 Data Register – – P6 Direction Register P6IO External Interrupt Polarity 0 Low Register EIPOL0L External Interrupt Polarity 0 High Register EIPOL0H External Interrupt Polarity 2 Low Register EIPOL2L External Interrupt Polarity 2 High Register...
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MC97F60128 ABOV Semiconductor Co., Ltd. @Reset Address Function Symbol Accumulator A Register – – – PA Direction Register PAIO – – Timer 3 Control Low Register T3CRL – – – Timer 3 Control High Register T3CRH Timer 3 A Data Low Register...
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MC97F60128 ABOV Semiconductor Co., Ltd. @Reset Address Function Symbol 4000H A/D Converter Data Low Register ADCDRL 4001H A/D Converter Data High Register ADCDRH – 4002H A/D Converter Control Low Register ADCCRL – 4003H A/D Converter Control High Register ADCCRH –...
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MC97F60128 ABOV Semiconductor Co., Ltd. @Reset Address Function Symbol 4020H P2 Function Selection Low Register P2FSRL – – – 4021H P2 Function Selection High Register P2FSRH 4022H P3 Function Selection Low Register P3FSRL 4023H P3 Function Selection High Register P3FSRH –...
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MC97F60128 ABOV Semiconductor Co., Ltd. @Reset Address Function Symbol 4040H USI1 Control Register 1 USI1CR1 4041H USI1 Control Register 2 USI1CR2 4042H USI1 Control Register 3 USI1CR3 – 4043H USI1 Control Register 4 USI1CR4 – – – – – –...
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MC97F60128 ABOV Semiconductor Co., Ltd. @Reset Address Function Symbol – – – 4060H UART2 Control Register 1 UART2CR1 4061H UART2 Control Register 2 UART2CR2 – – – – 4062H UART2 Control Register 3 UART2CR3 4063H UART2 Status Register UART2ST 4064H...
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MC97F60128 ABOV Semiconductor Co., Ltd. @Reset Address Function Symbol – – 4080H Timer 5 Control Low Register T5CRL – – – 4081H Timer 5 Control High Register T5CRH 4082H Timer 5 A Data Low Register T5ADRL 4083H Timer 5 A Data High Register...
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MC97F60128 ABOV Semiconductor Co., Ltd. @Reset Address Function Symbol T8DLYA 40A0H Timer 8 PWM A Delay Register T8DLYB 40A1H Timer 8 PWM B Delay Register 40A2H Timer 8 PWM C Delay Register T8DLYC 40A3H Timer 8 Data Register T8DR 40A4H...
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MC97F60128 ABOV Semiconductor Co., Ltd. @Reset Address Function Symbol 40C0H D/A Converter Control Register DACCR – – – – 40C1H Programmable Gain Selection Register PGSR 40C2H D/A Converter Data Low Register DACDRL 40C3H D/A Converter Data High Register DACDRH 40C4H...
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MC97F60128 ABOV Semiconductor Co., Ltd. SINTCR (System Interrupt Control Register) : F7H – – – – – – SPOVIE SPOVIFR – – – – – – Initial value : 00H SPOVIE Stack Pointer Overflow Interrupt Disable Enable When SPOVF Interrupt occurs, this bit becomes ‘1’. The flag SPOVIFR is cleared only by writing a ‘0’...
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MC97F60128 ABOV Semiconductor Co., Ltd. MEX1 (Memory Extension Register 1) :94H CB19 CB18 CB17 CB16 NB19 NB18 NB17 NB16 Initial value : 00H CB[19:16] Current Bank NB[19:16] Next Bank NOTE) This register records the “current” and “next” memory bank numbers for program code.
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MC97F60128 ABOV Semiconductor Co., Ltd. MEXSP (Memory Extension Register Stack Pointer) :97H – MEXSP6 MEXSP5 MEXSP4 MEXSP3 MEXSP2 MEXSP1 MEXSP0 – Initial value : 00H MEXSP[6:0] Memory Extension Stack Pointer NOTE) This register is the memory extension stack pointer. It provides for a stack depth of up to 128 bytes (Bit 7 is always 0).
9. I/O Ports I/O Ports The MC97F60128 has thirteen groups of I/O ports (P0 ~ PB/PD). Each port can be easily configured by software as I/O pin, internal pull-up and open-drain pin to meet various system configurations and design requirements. Also P0 ,P1, P4, P6, P9 and PA includes function that can generate interrupt according to change of state of the pin.
MC97F60128 ABOV Semiconductor Co., Ltd. 9.2.6 Port Function Selection Register (PxFSR) These registers define alternative functions of ports. Please remember that these registers should be set properly for alternative port function. A reset clears the PxFSR register to ‘00H’, which makes all pins to normal I/O ports.
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MC97F60128 ABOV Semiconductor Co., Ltd. Name Address Direction Default Description P5 Data Register P5IO P5 Direction Register P5OD 4015H (XSFR) P5 Open-drain Selection Register P5PU P5 Pull-up Resistor Selection Register P5FSRH 4027H (XSFR) P5 Function Selection High Register P5FSRL 4026H (XSFR)
MC97F60128 ABOV Semiconductor Co., Ltd. P1 Port 9.4.1 P1 Port Description P1 is 8-bit I/O port. P1 control registers consist of P1 data register (P1), P1 direction register (P1IO), debounce enable register (P1DB), P1 pull-up resistor selection register (P1PU) and P1 open-drain selection register (P1OD) . Refer to the port function selection registers for the P1 function selection.
MC97F60128 ABOV Semiconductor Co., Ltd. P2 Port 9.5.1 P2 Port Description P2 is 8-bit I/O port. P2 control registers consist of P2 data register (P2), P2 direction register (P2IO), P2 pull-up resistor selection register (P2PU) and P2 open-drain selection register (P2OD).Refer to the port function selection registers for the P2 function selection.
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MC97F60128 ABOV Semiconductor Co., Ltd. P2FSRH (Port 2 Function Selection High Register):4021H (XSFR) – – – P2FSRH4 P2FSRH3 P2FSRH2 P2FSRH1 P2FSRH0 – – – Initial value: 00H P2FSRH4 P27 Function select I/O Port (EXTSP1 function possible when input) COM7/SEG52 Function...
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MC97F60128 ABOV Semiconductor Co., Ltd. P2FSRL (Port 2 Function Selection Low Register): 4020H (XSFR) SPI3_3V P2FSRL6 P2FSRL5 P2FSRL4 P2FSRL3 P2FSRL2 P2FSRL1 P2FSRL0 Initial value: 00H SPI3_3V SPI3 Input Signal (MOSI3 or MISO3) 3V Interface Selection Normal voltage interface mode for SPI3 3V interface input mode for SPI3 (When VDD >= 3V)
MC97F60128 ABOV Semiconductor Co., Ltd. P3 Port 9.6.1 P3 Port Description P3 is 8-bit I/O port. P3 control registers consist of P3 data register (P3), P3 direction register (P3IO), P3 pull-up resistor selection register (P3PU) and open-drain selection register (P2OD). Refer to the port function selection registers for the P3 function selection.
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MC97F60128 ABOV Semiconductor Co., Ltd. P3FSRH (Port 3 Function Selection High Register): 4023H (XSFR) SPI2_3V P3FSRH6 P3FSRH5 P3FSRH4 P3FSRH3 P3FSRH2 P3FSRH1 P3FSRH0 Initial value: 00H SPI2_3V SPI2 Input Signal (MOSI2 or MISO2) 3V Interface Selection Normal voltage interface mode for SPI2 3V interface input mode for SPI2 (When VDD >= 3V)
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MC97F60128 ABOV Semiconductor Co., Ltd. P3FSRL (Port 3 Function Selection Low Register): 4022H (XSFR) P3FSRL7 P3FSRL6 P3FSRL5 P3FSRL4 P3FSRL3 P3FSRL2 P3FSRL1 P3FSRL0 Initial value: 00H P3FSRL[7:6] P33 Function Select P3FSRL7 P3FSRL6 Description I/O Port SEG40 Function MISO2 Function Not used...
MC97F60128 ABOV Semiconductor Co., Ltd. P4 Port 9.7.1 P4 Port Description P4 is 8-bit I/O port. P4 control registers consist of P4 data register (P4), P4 direction register (P4IO), debounce enable register (P46DB), P4 pull-up resistor selection register (P4PU) and P4 open-drain selection register (P4OD).Refer to the port function selection registers for the P4 function selection.
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MC97F60128 ABOV Semiconductor Co., Ltd. P4FSRH(Port 4 Function Selection High Register): 4025H (XSFR) – P4FSRH6 P4FSRH5 P4FSRH4 P4FSRH3 P4FSRH2 P4FSRH1 P4FSRH0 – Initial value: 00H P4FSRH6 P47 Function Select I/O Port (SS0 function possible when input) SEG36 Function P4FSRH[5:4] P46 Function Select...
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MC97F60128 ABOV Semiconductor Co., Ltd. P4FSRL(Port 4 Function Selection Low Register): 4024H (XSFR) – – – P4FSRL4 P4FSRL3 P4FSRL2 P4FSRL1 P4FSRL0 – – – Initial value: 00H P4FSRL[4:3] P43 Function Select P4FSRL4 P4FSRL3 Description I/O Port (EINT10 function possible when input)
MC97F60128 ABOV Semiconductor Co., Ltd. P5 Port 9.8.1 P5 Port Description P5 is 8-bit I/O port. P5 control registers consist of P5 data register (P5), P5 direction register (P5IO), P5 pull-up resistor selection register (P5PU) and P5 open-drain selection register (P5OD) . Refer to the port function selection registers for the P5 function selection.
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MC97F60128 ABOV Semiconductor Co., Ltd. P5FSRH (Port 5 Function Selection High Register): 4027H (XSFR) – P5FSRH6 P5FSRH5 P5FSRH4 P5FSRH3 P5FSRH2 P5FSRH1 P5FSRH0 – Initial value: 00H P5FSRH[6:5] P57 Function Select P5FSRH6 P5FSRH5 Description I/O Port SEG25 Function RXD1/SCL1/MISO1 Function Not used...
MC97F60128 ABOV Semiconductor Co., Ltd. P6 Port 9.9.1 P6 Port Description P6 is 6-bit I/O port. P6 control registers consist of P6 data register (P6), P6 direction register (P6IO), P6 pull-up resistor selection register (P6PU) and P6 open-drain selection register (P6OD) . Refer to the port function selection registers for the P6 function selection.
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MC97F60128 ABOV Semiconductor Co., Ltd. P6FSRH (Port 6 Function Selection High Register): 4029H (XSFR) – – – – – P6FSRH2 P6FSRH1 P6FSRH0 – – – – – Initial value: 00H P6FSRH2 P65 Function Select I/O Port (RXD2 function possible when input)
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MC97F60128 ABOV Semiconductor Co., Ltd. P6FSRL (Port 6 Function Selection Low Register): 4028H (XSFR) P6FSRL7 P6FSRL6 P6FSRL5 P6FSRL4 P6FSRL3 P6FSRL2 P6FSRL1 P6FSRL0 Initial value: 00H P6FSRL[7:6] P63 Function Select P6FSRL7 P6FSRL6 Description I/O Port (EC7 function possible when input) AN9 Function...
MC97F60128 ABOV Semiconductor Co., Ltd. 9.10 P7 Port 9.10.1 P7 Port Description P7 is 8-bit I/O port. P7 control registers consist of P7 data register (P7), P7 direction register (P7IO), P7 pull-up resistor selection register (P7PU) and P7 open-drain selection register (P7OD) . Refer to the port function selection registers for the P7 function selection.
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MC97F60128 ABOV Semiconductor Co., Ltd. P7FSRH (Port 7 Function Selection High Register): 402BH (XSFR) – – – – P7FSRH3 P7FSRH2 P7FSRH1 P7FSRH0 – – – – Initial value: 00H P7FSRH3 P77 Function Select I/O Port COM0 Function P7FSRH2 P76 Function Select...
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MC97F60128 ABOV Semiconductor Co., Ltd. P7FSRL (Port 7 Function Selection Low Register): 402AH (XSFR) P7FSRL7 P7FSRL6 P7FSRL5 P7FSRL4 P7FSRL3 P7FSRL2 P7FSRL1 P7FSRL0 Initial value: 00H P7FSRL[7:6] P73 Function Select P7FSRL7 P7FSRL6 Description I/O Port VLC0 Function PWM8CB Function SEG4 Function...
MC97F60128 ABOV Semiconductor Co., Ltd. 9.11 P8 Port 9.11.1 P8 Port Description P8 is 8-bit I/O port. P8 control registers consist of P8 data register (P8), P8 direction register (P8IO), P8 pull-up resistor selection register (P8PU) and P8 open-drain selection register (P8OD) . Refer to the port function selection registers for the P8 function selection.
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MC97F60128 ABOV Semiconductor Co., Ltd. P8FSR (Port 8 Function Selection Register): 402CH (XSFR) P8FSR7 P8FSR6 P8FSR5 P8FSR4 P8FSR3 P8FSR2 P8FSR1 P8FSR0 Initial value: 00H P8FSR7 P87 Function Select I/O Port SEG17 Function P8FSR6 P86 Function Select I/O Port SEG16 Function...
MC97F60128 ABOV Semiconductor Co., Ltd. 9.13 PA Port 9.13.1 PA Port Description PA is 5-bit I/O port. PA control registers consist of PA data register (PA), PA direction register (PAIO), debounce enable register (PADB), PA pull-up resistor selection register (PAPU) and PA open-drain selection register (PAOD).
MC97F60128 ABOV Semiconductor Co., Ltd. 9.14 PB Port 9.14.1 PB Port Description PB is 3-bit I/O port. PB control registers consist of PB data register (PB), PB direction register (PBIO), PB pull-up resistor selection register (PBPU) and PB open-drain selection register (PBOD). Refer to the port function selection registers for the PB function selection.
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MC97F60128 ABOV Semiconductor Co., Ltd. PBFSR (Port B Function Selection Register): 402FH (XSFR) – – – – – PBFSR2 PBFSR1 PBFSR0 – – – – – Initial value: 00H PBFSR2 PB2 Function Select I/O Port SEG28 Function PBFSR1 PB1 Function Select...
MC97F60128 ABOV Semiconductor Co., Ltd. 9.15 PD Port 9.15.1 PD Port Description PD is 5-bit I/O port. PD control registers consist of PD data register (PD), PD direction register (PDIO), PD pull-up resistor selection register (PDPU) and PD open-drain selection register (PDOD). Refer to the port function selection registers for the PD function selection.
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MC97F60128 ABOV Semiconductor Co., Ltd. PDFSR (Port A Function Selection Register): 4037H (XSFR) – – – PDFSR4 PDFSR3 PDFSR2 PDFSR1 PDFSR0 – – – Initial value: 00H PDFSR4 PD4 Function Select I/O Port SEG9 Function PDFSR3 PD3 Function Select I/O Port...
10.1 Overview The MC97F60128 supports up to 24 interrupt sources. The interrupts have separate enable register bits associated with them, allowing software control. They can also have four levels of priority assigned to them. The non-maskable interrupt source is always enabled with a higher priority than any other interrupt source and is not controllable by software.
MC97F60128 ABOV Semiconductor Co., Ltd. 10.2 External Interrupt The external interrupt on INT5, INT16, INT21 and INT23 pins receive various interrupt request depending on the external interrupt polarity 0/2/3/4 high/low register (EIPOLxH/L) and external interrupt polarity 1 register (EIPOL1) as shown in Figure 10.1.
MC97F60128 ABOV Semiconductor Co., Ltd. An interrupt request is delayed during data are written to IE, IE1, IE2, IE3, IP0L/H, IP1L/H, IP2L/H, IP3L/H and PCON register. 10.4 Interrupt Vector Table The interrupt controller supports 24 interrupt sources as shown in the Table 11-1. When interrupt is served, long call instruction (LCALL) is executed and program counter jumps to the vector address.
MC97F60128 ABOV Semiconductor Co., Ltd. 10.5 Interrupt Sequence An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to ‘0’ by a reset or an instruction. Interrupt acceptance always generates at last cycle of the instruction. So instead of fetching the current instruction, CPU executes internally LCALL instruction and saves the PC at stack.
MC97F60128 ABOV Semiconductor Co., Ltd. 10.6 Effective Timing after Controlling Interrupt Bit Case a) Control Interrupt Enable Register (IE, IE1, IE2, IE3) Interrupt Enable Register command After executing IE set/clear, enable register is effective. Next Instruction Next Instruction Figure 10.4...
MC97F60128 ABOV Semiconductor Co., Ltd. 10.7 Multi Interrupt If two requests of different priority levels are received simultaneously, the request of higher priority level is served first. If more than one interrupt request are received, the interrupt polling sequence determines which request is served first by hardware.
MC97F60128 ABOV Semiconductor Co., Ltd. 10.12.3 External Interrupt Flag Register (EIFLAG0, EIFLAG1) The external interrupt flag 0 register (EIFLAG0) and external interrupt flag 1 register (EIFLAG1) areset to ‘1’ when the external interrupt generating condition is satisfied. The flag is cleared when the interrupt service routine is executed.
MC97F60128 ABOV Semiconductor Co., Ltd. 10.13 Interrupt Register Description The interrupt register is used for controlling interrupt functions. Also it has external interrupt control registers. The interrupt register consists of interrupt enable register (IE), interrupt enable register 1 (IE1), interrupt enable register 2 (IE2) and interrupt enable register 3 (IE3).
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MC97F60128 ABOV Semiconductor Co., Ltd. EIFLAG0 (External Interrupt Flag 0 Register): BAH FLAG7 FLAG6 FLAG5 FLAG4 FLAG3 FLAG2 FLAG1 FLAG0 Initial value :00H When an External Interrupt 0-7 is occurred, the flag becomes ‘1’.The flag is cleared EIFLAG0[7:0] only by writing ‘0’ to the bit. So, the flag should be cleared by software. Writing “1”...
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MC97F60128 ABOV Semiconductor Co., Ltd. EIFLAG1 (External Interrupt Flag 1 Register): BBH T7IFR T6IFR T5IFR T4IFR T3IFR FLAG18 FLAG9 FLAG8 Initial value: 00H When T7 interrupt occurs, this bit becomes ‘1’. The flag is cleared only by writing a ‘0’...
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MC97F60128 ABOV Semiconductor Co., Ltd. EIFLAG2 (External Interrupt Flag 2 Register): BCH FLAG17 FLAG16 FLAG15 FLAG14 FLAG13 FLAG12 FLAG11 FLAG10 Initial value :00H When an External Interrupt 10-17 is occurred, the flag becomes ‘1’.The flag is cleared EIFLAG2[7:0] only by writing ‘0’ to the bit. So, the flag should be cleared by software. Writing “1”...
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MC97F60128 ABOV Semiconductor Co., Ltd. EIFLAG3 (External Interrupt Flag 3 Register): BDH – – – FLAGE FLAGD FLAGC FLAGB FLAGA – – – Initial value :00H When an External Interrupt A-E is occurred, the flag becomes ‘1’.The flag is cleared EIFLAG3[5:0] only by writing ‘0’...
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MC97F60128 ABOV Semiconductor Co., Ltd. EIFLAG4 (External Interrupt Flag 4 Register): BEH – – – FLAGJ FLAGI FLAGH FLAGG FLAGF – – – Initial value :00H When an External Interrupt F-J is occurred, the flag becomes ‘1’.The flag is cleared EIFLAG4[5:0] only by writing ‘0’...
MC97F60128 ABOV Semiconductor Co., Ltd. Peripheral Hardware 11.1 Clock Generator 11.1.1 Overview As shown in Figure 11.1, the clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and the peripheral hardware. It contains main/sub-frequency clock oscillator. The main/sub clock operation can be easily obtained by attaching a crystal between the XIN/SXIN and XOUT/SXOUT pin, respectively.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.1.4 Register Map Name Address Default Description SCCR System and Clock Control Register OSCCR Oscillator Control Register PLLCR Phase Locked-Loop Control Register Table 11-1 Clock Generator Register Map 11.1.5 Clock Generator Register Description The clock generator register uses clock control for system operation. The clock generation consists of system and clock control register, oscillator control register and phase locked-loop control register.
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MC97F60128 ABOV Semiconductor Co., Ltd. PLLCR (Phase Locked-Loop Control Register) : D6H – – PLLSTA P1DIV1 P1DIV0 P2DIV1 P2DIV0 PLLEN – – Initial value : 00H PLLSTA PLL Locked/Unlocked Status Bit PLL currently in unlocked state PLL currently in locked state P1DIV[1:0] PLL Post 1-Divider Selection Bits (49.152MHz)
11.2.1 Overview The MC97F60128 has one 8-bit basic interval timer that is free-run and can’t stop. Block diagram is shown in Figure 11.3. In addition, the basic interval timer generates the time base for watchdog timer counting. It also provides a basic interval timer interrupt (BITIFR).
MC97F60128 ABOV Semiconductor Co., Ltd. 11.2.3 Register Map Name Address Default Description BITCNT Basic Interval Timer Counter Register BITCR Basic Interval Timer Control Register Table 11-2 Basic Interval Timer Register Map 11.2.4 Basic Interval Timer Register Description The basic interval timer register consists of basic interval timer counter register (BITCNT) and basic interval timer control register (BITCR).
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MC97F60128 ABOV Semiconductor Co., Ltd. BITCR (Basic Interval Timer Control Register) : 8BH BITIFR BITCK1 BITCK0 BITIE BCLR BCK2 BCK1 BCK0 Initial value : 01H When BIT Interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit. So, BITIFR Writing “1”...
MC97F60128 ABOV Semiconductor Co., Ltd. 11.3 Watch Dog Timer 11.3.1 Overview The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or something like that and resumes the CPU to the normal state. The watchdog timer signal for malfunction detection can be used as either a CPU reset or an interrupt request.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.4 Watch Timer 11.4.1 Overview The watch timer has the function for RTC (Real Time Clock) operation. It is generally used for RTC design. The internal structure of the watch timer consists of the clock source select circuit, timer counter circuit, output select circuit and watch timer control register.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.5 Timer 0/1/2 11.5.1 Overview The 8-bit timer 0/1/2 consists of multiplexer, timer 0/1/2 counter register, timer 0/1/2 data register, timer 0/1/2 capture data register and timer 0/1/2 control register (TnCNT, TnDR, TnCDR, TnCR). It has three operating modes: −...
MC97F60128 ABOV Semiconductor Co., Ltd. 11.5.2 8-Bit Timer/Counter Mode The 8-bit timer/counter mode is selected by control register as shown in Figure 11.7. The 8-bit timer have counter and data register. The counter register is increased by internal or external clock input.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.5.3 8-Bit PWM Mode The timer 0/1/2 has a high speed PWM (Pulse Width Modulation) function. In PWM mode, TnO/PWMnO pin outputs up to 8-bit resolution PWM output. This pin should be configured as a PWM output by setting the T0O/PWM0O, T1O/PWM1O and T2O/PWM2O function by P4FSRL[4:3], P4FSRH[1:0] and P4FSRH[3:2] bits.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.5.4 8-Bit Capture Mode The timer 0/1/2 capture mode is set by TnMS[1:0] as ‘1x’. The clock source can use the internal/external clock. Basically, it has the same function as the 8-bit timer/counter mode and the interrupt occurs when TnCNT is equal to TnDR.
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MC97F60128 ABOV Semiconductor Co., Ltd. TnCDR Load TnCNT Value Count Pulse Period Up-count TIME Ext. EINT1n PIN Interrupt Request (FLAG1n) Interrupt Interval Period Figure 11.12 Input Capture Mode Operation for Timer 0/1/2 (Where n = 0, 1 and 2) TnCNT...
MC97F60128 ABOV Semiconductor Co., Ltd. 11.5.6 Register Map Name Address Default Description TnCR D2H/DAH/DDH Timer n Control Register TnCNT D3H/DBH/DEH Timer n Counter Register TnDR D4H/DCH/DFH Timer n Data Register TnCDR D4H/DCH/DFH Timer n Capture Data Register TINTCR 4004H (XSFR)
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MC97F60128 ABOV Semiconductor Co., Ltd. TnCR (Timer n Control Register) : D2H/DAH/DDH, Where n = 0, 1 and 2 – TnEN TnMS1 TnMS0 TnCK2 TnCK1 TnCK0 TnCC – Initial value : 00H TnEN Control Timer n Timer n disable Timer n enable...
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MC97F60128 ABOV Semiconductor Co., Ltd. TINTCR(Timer Interrupt Control Register) : 4004H (XSFR) – – T2MIE T1MIE T0MIE T2OVIE T1OVIE T0OVIE – – Initial value : 00H T2MIE Enable or Disable Timer 2 Match Interrupt Disable Enable T1MIE Enable or Disable Timer 1 Match Interrupt...
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MC97F60128 ABOV Semiconductor Co., Ltd. TIFLAG(Timer Interrupt Flag Register) : D5H – – T2OVIFR T2IFR T1OVIFR T1IFR T0OVIFR T0IFR – – Initial value : 00H When T2 overflow interrupt occurs, this bit becomes ‘1’. The flag is cleared only by T2OVIFR writing a ‘0’...
MC97F60128 ABOV Semiconductor Co., Ltd. 11.6.3 16-Bit Capture Mode The 16-bit Timer 3/4/5/6 capture mode is set by TnMS[1:0] as ‘01’. The clock source can use the internal/external clock. Basically, it has the same function as the 16-bit timer/counter mode and the interrupt occurs when TnCNTH/TnCNTL is equal to TnADRH/TnADRL.
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MC97F60128 ABOV Semiconductor Co., Ltd. TnBDRH/L Load TnCNTH/L Value Count Pulse Period Up-count TIME Ext. EINT1n PIN Interrupt Request (FLAG1n) Interrupt Interval Period Figure 11.18 Input Capture Mode Operation for Timer 3/4/5/6 (where n = 3,4,5 and 6) FFFF FFFF...
MC97F60128 ABOV Semiconductor Co., Ltd. 11.6.4 16-Bit PPG Mode The Timer 3/4/5/6 has a PPG (Programmable Pulse Generation) function. In PPG mode, T3O/PWM3O, T4O/PWM4O, T5O/PWM5O and T6O/PWM6O pin outputs up to 16-bit resolution PWM output. This pin should be configured as a PWM output by setting P1FSR[1:0] to ‘01’, P1FSR[2] to ‘1’, P1FSR[3] to ‘1’...
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MC97F60128 ABOV Semiconductor Co., Ltd. Repeat Mode(TnMS = 11b) and "Start High"(TnPOL = 0b). Clear and Start Set TnEN Timer n clock Counter TnADRH/L Tn Interrupt 1. TnBDRH/L(5) < TnADRH/L PWMnO B Match A Match 2. TnBDRH/L >= TnADRH/L PWMnO A Match 3.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.6.5 Block Diagram 16- bit A Data Register TnADRH / TnADRL A Match Reload TnCC TnEN TnECE TnCK[2:0] TnMIE Buffer Register A To other block Clear Edge To interrupt Detector A Match block TnIFR fx/1...
MC97F60128 ABOV Semiconductor Co., Ltd. 11.6.6 Register Map Name Address Default Description TnCRH E3H/4079H/4081H/4089H Timer n Control High Register TnCRL E2H/4078H/4080H/4088H Timer n Control Low Register TnADRH E5H/407BH/4083H/408BH Timer n A Data High Register TnADRL E4H/407AH/4082H/408AH Timer n A Data Low Register...
MC97F60128 ABOV Semiconductor Co., Ltd. 11.6.8 Register Description for Timer/Counter 3/4/5/6 TnADRH (Timer n A data High Register) : E5H/407BH/4083H/408BH (where n = 3,4,5 and 6) TnADRH7 TnADRH6 TnADRH5 TnADRH4 TnADRH3 TnADRH2 TnADRH1 TnADRH0 Initial value : FFH TnADRH[7:0] Tn A Data High Byte...
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MC97F60128 ABOV Semiconductor Co., Ltd. TnCRH (Timer n Control High Register) : E3H/4079H/4081H/4089H (where n = 3,4,5 and 6) – – – TnEN TnMIE TnMS1 TnMS0 TnCC – – – Initial value : 00H TnEN Control Timer n Timer n disable...
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MC97F60128 ABOV Semiconductor Co., Ltd. TnCRL (Timer n Control Low Register) : E2H/4078H/4080H/4088H (where n = 3,4,5 and 6) – – TnCK2 TnCK1 TnCK0 TnPOL TnECE TnCNTR – – Initial value : 00H TnCK[2:0] Select Timer n clock source. fx is main system clock frequency...
MC97F60128 ABOV Semiconductor Co., Ltd. 11.7 Timer 7/8 11.7.1 Overview Timer 7 and timer 8 can be used either two 8-bit timer/counter or one 16-bit timer/counter with combine them. Each 8- bit timer/event counter module has multiplexer, comparator, 8-bit timer data register, 8-bit counter register, control register and capture data register (T7CNT, T7DR, T7CAPR, T7CR, T8CNT, T8DR, T8CAPR, T8CR).
MC97F60128 ABOV Semiconductor Co., Ltd. 11.7.2 8-Bit Timer/Counter 7/8 Mode The 8-bit timer/counter mode is selected by control register as shown in Figure 11.23. The two 8-bit timers have each counter and data register. The counter register is increased by internal or external clock input.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.7.3 16-Bit Timer/Counter 7 Mode The 16-bit timer/counter mode is selected by control register as shown in Figure 11.24. The 16-bit timer have counter and data register. The counter register is increased by internal or external clock input.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.7.4 8-Bit Timer 7/8 Capture Mode The 8-bit Capture 7 and 8 mode is selected by control register as shown in Figure 11.25. The timer 7/8 capture mode is set by T7MS, T8MS as ‘1’. The clock source can use the internal/external clock.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.7.5 16-Bit Timer 7 Capture Mode The 16-bit Capture mode is selected by control register as shown in Figure 11.26. The 16-bit capture mode is the same operation as 8-bit capture mode, except that the timer register uses 16 bits. The 16-bit timer 7 capture mode is set by T7MS, T8MS as ‘1’.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.7.6 10-Bit Timer 8 PWM Mode The timer 8 has a high speed PWM (Pulse Width Modulation) function. In PWM mode, the 6-channel pins output up to 10-bit resolution PWM output. This pin should be configured as a PWM output by set PWM8E to ‘1’. When the value of 2bit +T8CNT and T8PPRH/L are identical in timer 8, a period match signal is generated and the interrupt of timer 8 occurs.
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MC97F60128 ABOV Semiconductor Co., Ltd. Update period & duty register value at once The period and duty of PWM comes to move from temporary registers to T8PPRH/L (PWM Period Register) and T8ADRH/L,T8BDRH/L,T8CDRH/L (PWM Duty Register) when always period match occurs. If you want that the period and duty is immediately changed, the UPDT bit in the T8PCR1 register must set to ‘1’.
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MC97F60128 ABOV Semiconductor Co., Ltd. External Sync If using ESYNC bit of T8PCR1 register, it is possible to synchronize the output of PWM from external signal. If ESYNC bit sets to ‘1’, the external signal moves to PWM module through the BLNK pin. If BLNK signal is on rising edge, immediately PWM output become HIGH-Z.
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MC97F60128 ABOV Semiconductor Co., Ltd. FORCE Drive ALL Channel with A-ch mode If FORCA bit sets to ‘1’, it is possible to enable or disable all PWM output pins through PWM outputs which occur from A-ch duty counter. It is noted that the inversion outputs of A, B, C channel have the same A-ch output waveform.
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MC97F60128 ABOV Semiconductor Co., Ltd. FORCE 6-Ch Drive If FORCA bit sets to ‘0’, it is possible to enable or disable PWM output pin and inversion output pin generated through the duty counter of each channel. The inversion output is the reverse phase of the PWM output. A AA/AB output of the A-channel duty register, a BA/BB output of the B-channel duty register, a CA/CB output of the C-channel duty register are controlled respectively.
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MC97F60128 ABOV Semiconductor Co., Ltd. PWM output Delay If using the T8DLYA, T8DLYB, T8DLYC register, it can delay PWM output based on the rising edge. At that time, it does not change the falling edge, so the duty is reduced as the time delay. In POLAA/BA/CA setting to ‘0’, the delay is applied to the falling edge.
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MC97F60128 ABOV Semiconductor Co., Ltd. T8CR (Timer 8 Control Register) : 4092H (XSFR) 16BIT T8MS T8CN T8ST T8CK3 T8CK2 T8CK1 T8CK0 Initial value : 00H 16BIT Select Two 8-bit or 16-bit Mode for Timer 7/8 Two 8-bit Timer 7/8 16-bit Timer 7...
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MC97F60128 ABOV Semiconductor Co., Ltd. T8PCR1 (Timer 8 PWM Control Register 1) : 4093H (XSFR) PWM8E ESYNC BMOD PHLT UPDT UALL NOPS1 NOPS0 Initial value : 00H PWM8E Control Timer 8 Mode Select timer/counter or capture mode of Timer 8...
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MC97F60128 ABOV Semiconductor Co., Ltd. T8PCR2 (Timer 8 PWM Control Register 2) : 4094H (XSFR) – FORCA PAAOE PABOE PBAOE PBBOE PCAOE PCBOE – Initial value : 00H FORCA Control The PWM outputs Mode 6-channel mode (The PWM8xA/PWM8xB pins are output according to the T8xDR registers, respectively.
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MC97F60128 ABOV Semiconductor Co., Ltd. T8PCR3 (Timer 8 PWM Control Register 3) : 4095H (XSFR) HZCLR POLBO POLAA POLAB POLBA POLBB POLCA POLCB Initial value : 00H HZCLR High-Impedance Output Clear Bit No effect Clear high-impedance output (The PWM8xA/PWM8xB pins are back to output and this bit is automatically cleared to logic ‘0’.
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MC97F60128 ABOV Semiconductor Co., Ltd. T8ISR (Timer 8 Interrupt Status Register) : 4096H (XSFR) – – – IOVR IBTM ICMA ICMB ICMC – – – Initial value : 00H IOVR Timer 8 Compare Match or Timer 8 Overflow Interrupt Status, Write '0' to this bit for clear.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.8.3 10-Bit PWM One-Shot Mode Without Auto-Enable The 10-bit PWM one-shot mode without auto-enable is selected by PWMMD[1:0] bits set to “00b”. A 10-bit counter register is increased by internal clock input on operation. When the PWMCNTH/PWMCNTL is identical to the PWMADRH/PWMADRL, a match signal is generated, the PWMOUT pin is inverted and the counting is continued to “3FFH”.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.8.4 10-Bit PWM One-Shot Mode With Auto-Enable The 10-bit PWM one-shot mode with auto-enable is selected by PWMMD[1:0] bits set to “01b”. The function of the 10- bit PWM one-shot mode with auto-enable is the same as the one of the 10-bit PWM one-shot mode without auto- enable, but the 10-bit PWM generator in the 10-bit PWM one-shot mode with auto-enable is automatically enabled as PWMEN bit set to ‘1’...
MC97F60128 ABOV Semiconductor Co., Ltd. 11.8.5 10-Bit PWM Repeat Mode The 10-bit PWM repeat mode is selected by PWMMD[1:0] bits set to “1xb”. A 10-bit counter register is increased by internal clock input on operation. When the PWMCNTH/PWMCNTL is identical to the PWMADRH/PWMADRL, a match signal is generated, the PWMOUT pin is inverted and the counting is continued to “3FFH”.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.9 Buzzer Driver 11.9.1 Overview The Buzzer consists of 6 bit counter, buzzer data register (BUZDR) and buzzer control register (BUZCR). The Square Wave (122Hz~62.5kHz @fBUZ=1MHz) is outputted through P46/SEG35/BUZO pin. The buzzer data register (BUZDR) BUZDR[5:0] controls the bsuzzer frequency (look at the following expression) and BUZDIV[1:0] selects fBUZ divided by DIV block.
11.10 SPI 2 11.10.1 Overview There is serial peripheral interface with FIFO (SPI 2) one channel in MC97F60128. The SPI 2 allows synchronous serial data transfer between the external serial devices. It can do Full-duplex communication by 4-wire (MOSI2, MISO2, SCK2, SS2), support master/slave mode, can select serial clock (SCK2) polarity, phase and whether LSB first data transfer or MSB first data transfer.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.10.3 Data Transmit / Receive Operation User can use SPI 2 for serial data communication by following step Select SPI 2 operation mode(master/slave, polarity, phase) by control register SPInCRH. When the SPI 2 is configured as a Master, it selects a Slave by SS2 signal (active low).
MC97F60128 ABOV Semiconductor Co., Ltd. 11.10.6 Register Map Name Address Default Description SPI2CRH 408FH (XSFR) SPI2 Control High Register SPI2CRL 408EH (XSFR) SPI2 Control Low Register SPI2DR 407FH (XSFR) SPI2 Data Register SPI2SRH 4087H (XSFR) SPI2 Status High Register SPI2SRL...
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MC97F60128 ABOV Semiconductor Co., Ltd. SPI2SRH (SPI 2 Status High Register) : 4087H (XSFR) – – – WCOL2 SS_HIGH2 FXCH2 SPI2SSEN DOR2 – – – Initial value : 00H WCOL2 This bit is set if any data are written to the data register SPI2DR during transfer in the master mode and during the SPI2 Tx FIFO is full.
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MC97F60128 ABOV Semiconductor Co., Ltd. SPI2SRL (SPI 2 Status Low Register) : 4086H (XSFR) – – – TXFEIFR RXFFIFR SPI2IFR TXFFF RXFEF – – – Initial value : 04H When SPI2 Tx FIFO empty Interrupt occurs, this bit becomes ‘1’. For clearing bit, write TXFEIFR ‘0’...
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MC97F60128 ABOV Semiconductor Co., Ltd. SPI2CRH (SPI 2 Control High Register) : 408FH (XSFR) SPI2EN FLSB2 SPI2MS CPOL2 CPHA2 SPI2DSCR SPI2SCR1 SPI2SCR0 Initial value : 00H SPI2EN This bit controls the SPI 2 operation Disable SPI 2 operation Enable SPI 2 operation...
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MC97F60128 ABOV Semiconductor Co., Ltd. SPI2CRL (SPI 2 Control Low Register) : 408EH (XSFR) – – – – – – FIFOC MSTR2 – – – – – – Initial value : 00H FIFOC SPI2 Tx/Rx FIFO and Pointer Clear Bit No effect Clear all Tx/Rx FIFO, Pointer and Control signal.
11.11 SPI 3 11.11.1 Overview There is serial peripheral interface (SPI 3) one channel in MC97F60128. The SPI 3 allows synchronous serial data transfer between the external serial devices. It can do Full-duplex communication by 4-wire (MOSI3, MISO3, SCK3, SS3), support master/slave mode, can select serial clock (SCK3) polarity, phase and whether LSB first data transfer or MSB first data transfer.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.11.3 Data Transmit / Receive Operation User can use SPI 3 for serial data communication by following step Select SPI 3 operation mode(master/slave, polarity, phase) by control register SPI3CR. When the SPI 3 is configured as a Master, it selects a Slave by SS3 signal (active low).
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MC97F60128 ABOV Semiconductor Co., Ltd. SPI3SR (SPI 3 Status Register) : 400FH (XSFR) – – – SPI3IFR WCOL3 SS_HIGH3 FXCH3 SPI3SSEN – – – Initial value : 00H When SPI 3 Interrupt occurs, this bit becomes ‘1’. IF SPI 3 interrupt is enable, this bit is SPI3IFR auto cleared by INT_ACK signal.
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MC97F60128 ABOV Semiconductor Co., Ltd. SPI3CR (SPI 3 Control Register) : 400DH (XSFR) SPI3EN FLSB3 SPI3MS CPOL3 CPHA3 SPI3DSCR SPI3SCR1 SPI3SCR0 Initial value : 00H SPI3EN This bit controls the SPI 3 operation Disable SPI 3 operation Enable SPI 3 operation...
MC97F60128 ABOV Semiconductor Co., Ltd. 11.12 UART2/3/4 11.12.1 Overview The universal asynchronous serial receiver and transmitter (UART2/3/4) is a highly flexible serial communication device. The main features are listed below. − Full Duplex Operation (Independent Serial Receive and Transmit Registers) −...
MC97F60128 ABOV Semiconductor Co., Ltd. 11.12.4 Data format A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits) and optionally a parity bit for error detection. The UART2/3/4 supports all 30 combinations of the following as valid frame formats.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.12.5 Parity bit The parity bit is calculated by doing an exclusive-OR of all the data bits. If odd parity is used, the result of the exclusive-or is inverted. The parity bit is located between the MSB and first stop bit of a serial frame.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.12.9 Parity Generator The parity generator calculates the parity bit for the serial frame data to be sent. When parity bit is enabled (UnPM[1]=1), the transmitter control logic inserts the parity bit between the MSB and the first stop bit of the frame to be sent.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.12.13 Receiver Flag and Interrupt The UART2/3/4 receiver has one flag that indicates the receiver state. The receive complete (RXCn) flag indicates whether there are unread data in the receive buffer. This flag is set when there are unread data in the receive buffer and cleared when the receive buffer is empty.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.12.16 Asynchronous Data Reception To receive asynchronous data frame, the UART includes a clock and data recovery unit. The clock recovery logic is used for synchronizing the internally generated baud-rate clock to the incoming asynchronous serial frame on the RXDn pin.
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MC97F60128 ABOV Semiconductor Co., Ltd. When the receiver is enabled (RXEn=1), the clock recovery logic tries to find a high-to-low transition on the RXDn line, the start bit condition. After detecting high to low transition on RXDn line, the clock recovery logic uses samples 8,9 and 10 for normal mode to decide if a valid start bit is received.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.12.17 Register Map Name Address Default Description UARTnCR1 4060H/4068H/4070H (XSFR) UARTn Control Register 1 UARTnCR2 4061H/4069H/4071H (XSFR) UARTn Control Register 2 UARTnCR3 4062H/406AH/4072H (XSFR) UARTn Control Register 3 UARTnST 4063H/406BH/4073H (XSFR) UARTn Status Register UARTnBD...
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MC97F60128 ABOV Semiconductor Co., Ltd. UARTnDR (UARTn Data Register) : 4065H/406DH/4075H (XSFR), Where n = 2, 3 and 4 UARTnDR7 UARTnDR6 UARTnDR5 UARTnDR4 UARTnDR3 UARTnDR2 UARTnDR1 UARTnDR0 Initial value : 00H UARTnDR [7:0] The UARTn Transmit Buffer and Receive Buffer share the same I/O address with this DATA register.
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MC97F60128 ABOV Semiconductor Co., Ltd. UARTnCR2 (UARTn Control Register 2) : 4061H/4069H/4071H (XSFR), Where n = 2, 3 and 4 UDRIEn TXCIEn RXCIEn WAKEIEn TXEn RXEn UARTnEN U2Xn Initial value : 00H UDRIEn Interrupt enable bit for UARTn Data Register Empty...
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MC97F60128 ABOV Semiconductor Co., Ltd. UARTnCR3 (UARTn Control Register 3) : 4062H/406AH/4072H (XSFR), Where n = 2, 3 and 4 LOOPSn USBSn UnTX8 UnRX8 Initial value : 00H LOOPSn Controls the Loop Back Mode of UARTn, for test mode Normal operation...
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MC97F60128 ABOV Semiconductor Co., Ltd. UARTnST (UARTn Status Register) : 4063H/406BH/4073H (XSFR), Where n = 2, 3 and 4 UDREn TXCn RXCn WAKEn SOFTRSTn DORn Initial value : 80H UDREn The UDREn flag indicates if the transmit buffer (UARTnDR) is ready to receive new data.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.13.2 USI0/1 UART Mode The universal synchronous and asynchronous serial receiver and transmitter (UART) is a highly flexible serial communication device. The main features are listed below. − Full Duplex Operation (Independent Serial Receive and Transmit Registers) −...
MC97F60128 ABOV Semiconductor Co., Ltd. 11.13.4 USI0/1 Clock Generation USInBD DBLSn SCLK (USInBD+1) Prescaling Up-Counter txclk SCLK MASTERn Edge Sync Register USInMS[1:0] Detector CPOLn SCKn rxclk Figure 11.63 Clock Generation Block Diagram (USIn, where n = 0 and 1) The clock generation logic generates the base clock for the transmitter and receiver. The USI0/1 supports four modes of clock operation and those are normal asynchronous, double speed asynchronous, master synchronous and slave synchronous mode.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.13.5 USI0/1 External Clock (SCKn) External clocking is used in the synchronous mode of operation. External clock input from the SCKn pin is sampled by a synchronization logic to remove meta-stability. The output from the synchronization logic must be passed through an edge detector before it is used by the transmitter and receiver.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.13.7 USI0/1 UART Data format A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits) and optionally a parity bit for error detection. The UART supports all 30 combinations of the following as valid frame formats.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.13.8 USI0/1 UART Parity bit The parity bit is calculated by doing an exclusive-OR of all the data bits. If odd parity is used, the result of the exclusive-O is inverted. The parity bit is located between the MSB and first stop bit of a serial frame.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.13.12 USI0/1 UART Parity Generator The parity generator calculates the parity bit for the serial frame data to be sent. When parity bit is enabled (USInPM1=1), the transmitter control logic inserts the parity bit between the MSB and the first stop bit of the frame to be sent.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.13.16 USI0/1 UART Receiver Flag and Interrupt The UART receiver has one flag that indicates the receiver state. The receive complete (RXCn) flag indicates whether there are unread data in the receive buffer. This flag is set when there are unread data in the receive buffer and cleared when the receive buffer is empty.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.13.19 USI0/1 Asynchronous Data Reception To receive asynchronous data frame, the UART includes a clock and data recovery unit. The clock recovery logic is used for synchronizing the internally generated baud-rate clock to the incoming asynchronous serial frame on the RXDn pin.
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MC97F60128 ABOV Semiconductor Co., Ltd. When the receiver is enabled (RXEn=1), the clock recovery logic tries to find a high-to-low transition on the RXDn line, the start bit condition. After detecting high to low transition on RXDn line, the clock recovery logic uses samples 8, 9 and 10 for normal mode to decide if a valid start bit is received.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.13.20 USI0/1 SPI Mode The USI0/1 can be set to operate in industrial standard SPI compliant mode. The SPI mode has the following features. − Full Duplex, Three-wire synchronous data transfer − Mater and Slave Operation −...
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MC97F60128 ABOV Semiconductor Co., Ltd. SCKn (CPOLn=0) SCKn (CPOLn=1) SAMPLE MOSIn MSB First … BIT7 BIT6 BIT2 BIT1 BIT0 LSB First … BIT0 BIT1 BIT5 BIT6 BIT7 MISOn /SSn OUT (MASTER) /SSn IN (SLAVE) Figure 11.69 USI0/1 SPI Clock Formats when CPHAn=0 (where n = 0 and 1) When CPHAn=0, the slave begins to drive its MISOn output with the first data bit value when SSn goes to active low.
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MC97F60128 ABOV Semiconductor Co., Ltd. SCKn (CPOLn=0) SCKn (CPOLn=1) SAMPLE MOSIn … MSB First BIT7 BIT6 BIT2 BIT1 BIT0 … LSB First BIT0 BIT1 BIT5 BIT6 BIT7 MISOn /SSn OUT (MASTER) /SSn IN (SLAVE) Figure 11.70 USI0/1 SPI Clock Formats when CPHAn=1 (where n = 0 and 1) When CPHAn=1, the slave begins to drive its MISOn output when SSn goes active low, but the data is not defined until the first SCKn edge.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.13.23 USI0/1 I2C Mode The USI0/1 can be set to operate in industrial standard serial communicatin protocols mode. The I2C mode uses 2 bus lines serial data line (SDAn) and serial clock line (SCLn) to exchange data. Because both SDAn and SCLn lines are open-drain output, each line needs pull-up resistor.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.13.25 USI0/1 I2C Start / Repeated Start / Stop One master can issue a START (S) condition to notice other devices connected to the SCLn, SDAn lines that it will use the bus. A STOP (P) condition is generated by the master to release the bus lines so that other devices can use it.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.13.27 USI0/1 I2C Acknowledge The acknowledge related clock pulse is generated by the master. The transmitter releases the SDAn line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDAn line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse.
MC97F60128 ABOV Semiconductor Co., Ltd. Wait High Start High Counting Counting Fast Device SCLOUT High Counter Reset Slow Device SCLOUT SCLn Figure 11.76 Clock Synchronization during Arbitration Procedure (USIn, where n = 0 and 1) Arbitration Process Device 1 loses...
MC97F60128 ABOV Semiconductor Co., Ltd. 11.13.30 USI0/1 I2C Master Transmitter To operate I2C in master transmitter, follow the recommended steps below. Enable I2C by setting USInMS[1:0] bits in USInCR1 and USInEN bit in USInCR2. This provides main clock to the peripheral.
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MC97F60128 ABOV Semiconductor Co., Ltd. This is ACK signal processing stage for data packet transmitted by master. I2C holds the SCLn LOW. When I2C loses bus mastership while transmitting data arbitrating other masters, the MLOSTn bit in USInST2 is set.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.13.31 USI0/1 I2C Master Receiver To operate I2C in master receiver, follow the recommended steps below. Enable I2C by setting USInMS[1:0] bits in USInCR1 and USInEN bit in USInCR2. This provides main clock to the peripheral.
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MC97F60128 ABOV Semiconductor Co., Ltd. This is ACK signal processing stage for data packet transmitted by slave. I2C holds the SCLn LOW. When 1- Byte of data is received completely, I2C generates TENDn interrupt. I2C can choose one of the following cases according to the RXACKn flag in USInST2.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.13.32 USI0/1 I2C Slave Transmitter To operate I2C in slave transmitter, follow the recommended steps below. If the main operating clock (SCLK) of the system is slower than that of SCLn, load value 0x00 into USInSDHR to make SDAn change within one system clock period from the falling edge of SCLn.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.13.33 USI0/1 I2C Slave Receiver To operate I2C in slave receiver, follow the recommended steps below. If the main operating clock (SCLK) of the system is slower than that of SCLn, load value 0x00 into USInSDHR to make SDAn change within one system clock period from the falling edge of SCLn.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.13.35 Register Map Name Address Default Description USInCR1 4030H/4040H (XSFR) USIn Control Register 1 USInCR2 4031H/4041H (XSFR) USIn Control Register 2 USInCR3 4032H/4042H (XSFR) USIn Control Register 3 USInCR4 4033H/4043H (XSFR) USIn Control Register 4...
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MC97F60128 ABOV Semiconductor Co., Ltd. USInDR (USI0/1 Data Register: For UART, SPI and I2C mode) : 403CH/404CH (XSFR), n = 0 and 1 USInDR7 USInDR6 USInDR5 USInDR4 USInDR3 USInDR2 USInDR1 USInDR0 Initial value : 00H USInDR[7:0] The USIn transmit buffer and receive buffer share the same I/O address with this DATA register.
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MC97F60128 ABOV Semiconductor Co., Ltd. USInSCLR (USI0/1 SCL Low Period Register: For I2C mode) : 403DH/404DH (XSFR), n = 0 and 1 USInSCLR7 USInSCLR6 USInSCLR5 USInSCLR4 USInSCLR3 USInSCLR2 USInSCLR1 USInSCLR0 Initial value : 3FH USInSCLR[7:0] This register defines the high period of SCL when it operates in I2C master mode.
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MC97F60128 ABOV Semiconductor Co., Ltd. USInCR1 (USI0/1 Control Register 1: For UART, SPI and I2C mode) : 4030H/4040H (XSFR), n = 0 and 1 USInS1 USInS0 USInMS1 USInMS0 USInPM1 USInPM0 USInS2 CPOLn ORDn CPHAn Initial value : 00H USInMS[1:0] Selects operation mode of USIn...
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MC97F60128 ABOV Semiconductor Co., Ltd. USInCR2 (USI0/1 Control Register 2: For UART, SPI and I2C mode) : 4031H/4041H (XSFR), n = 0 and 1 DRIEn TXCIEn RXCIEn WAKEIEn TXEn RXEn USInEN DBLSn Initial value : 00H DRIEn Interrupt enable bit for data register empty (only UART and SPI mode).
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MC97F60128 ABOV Semiconductor Co., Ltd. USInCR3 (USI0/1 Control Register 3: For UART, SPI and I2C mode) : 4032H/4042H (XSFR), n = 0 and 1 MASTERn LOOPSn DISSCKn USInSSEN FXCHn USInSB USInTX8 USInRX8 Initial value : 00H MASTERn Selects master or slave in SPI and synchronous mode operation and controls the direction of SCKn pin Slave mode operation (External clock for SCK).
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MC97F60128 ABOV Semiconductor Co., Ltd. USInCR4 (USI0/1 Control Register 4: For I2C mode) : 4033H/4043H (XSFR), n = 0 and 1 – IICnIFR TXDLYENBn IICnIE ACKnEN IMASTERn STOPCn STARTCn – Initial value : 00H This is an interrupt flag bit for I2C mode. When an interrupt occurs, this bit becomes ‘1’.
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MC97F60128 ABOV Semiconductor Co., Ltd. USInST1 (USI0/1 Status Register 1: For UART and SPI mode) : 4038H/4048H (XSFR), n = 0 and 1 DREn TXCn RXCn WAKEn USInRST DORn Initial value : 80H DREn The DREn flag indicates if the transmit buffer (USInDR) is ready to receive new data. If DREn is ‘1’, the buffer is empty and ready to be written.
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MC97F60128 ABOV Semiconductor Co., Ltd. USInST2 (USI0/1 Status Register 2: For I2C mode) : 4039H/4049H (XSFR), n = 0 and 1 GCALLn TENDn STOPDn SSELn MLOSTn BUSYn TMODEn RXACKn Initial value : 00H (NOTE) GCALLn This bit has different meaning depending on whether I2C is master or slave. When I2C is a master, this bit represents whether it received AACK (address ACK) from slave.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.14 12-Bit A/D Converter 11.14.1 Overview The analog-to-digital converter (A/D) allows conversion of an analog input signal to corresponding 12-bit digital value. The A/D module has twelve analog inputs. The output of the multiplexer is the input into the converter which generates the result through successive approximation.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.14.3 Block Diagram TRIG[2:0] ADST T3 A match signal T4 A match signal T5 A match signal Start T8 overflow event signal T8 A match event signal CKSEL[1:0] T8 B match event signal T8 C match event signal...
MC97F60128 ABOV Semiconductor Co., Ltd. SET ADCCRH Select ADC Clock and Data Align Bit. SET ADCCRL ADC enable & Select AN Input Channel. Converting START Start ADC Conversion. If Conversion is completed, AFLAG is set “1” and ADC AFLAG = 1? interrupt is occurred.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.14.7 Register Description for ADC ADCDRH (A/D Converter Data High Register) : 4001H (XSFR) ADDM11 ADDM10 ADDM9 ADDM8 ADDM7 ADDM6 ADDM5 ADDM4 ADDL11 ADDL10 ADDL9 ADDL8 Initial value : xxH ADDM[11:4] MSB align, A/D Converter High Result (8-bit)
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MC97F60128 ABOV Semiconductor Co., Ltd. ADCCRH (A/D Converter High Register) : 4003H (XSFR) ADCIE ADCIFR TRIG2 TRIG1 TRIG0 ALIGN CKSEL1 CKSEL0 Initial value : 00H ADCIE Enable or Disable A/DC Interrupt Disable Enable When ADC interrupt occurs, this bit becomes ‘1’. For clearing bit, write ‘0’ to this bit or ADCIFR auto clear by INT_ACK signal.
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MC97F60128 ABOV Semiconductor Co., Ltd. ADCCRL (A/D Converter Counter Low Register) : 4002H (XSFR) STBY ADST AFLAG ADSEL3 ADSEL2 ADSEL1 ADSEL0 Initial value : 00H STBY Control Operation of A/D (The ADC module is automatically disabled at stop mode) ADC module disable...
MC97F60128 ABOV Semiconductor Co., Ltd. 11.15 12-Bit D/A Converter 11.15.1 Overview The digital-to-analog converter (D/A) uses successive approximation logic to convert 12-bit digital value to an analog output level. The D/A module has six registers which are the D/A converter control register (DACCR), D/A converter data high register (DACDRH), D/A converter data low register (DACDRL), D/A converter buffer high register (DACBRH), D/A converter buffer low register (DACBRL) and programmable gain selection register (PGSR).
MC97F60128 ABOV Semiconductor Co., Ltd. 11.15.4 Automatically D/AC Data Increment/Decrement The “automatically D/AC data increment/decrement” function is important to remove a pop noise when voice prompt play. If this function is not embedded, a programmer have to code to reduce a pop noise on speaker. The DACDR[15:4] value increases a curret D/AC data value to 800H with “automatically D/AC data increment”...
MC97F60128 ABOV Semiconductor Co., Ltd. 11.15.5 Programmable Gain Controller There are 11 selectable step in the programmable gain controller. The steps are -30dB, -24dB, -18dB, -12dB, -6dB, 0dB, +6dB, +12dB, +18dB, +24dB and +30dB. The gain is selected by the programmable gain register (PGSR).
MC97F60128 ABOV Semiconductor Co., Ltd. 11.15.10 Register Description for DAC DACDRH (D/A Converter Data High Register) : 40C3H (XSFR) DACDR15 DACDR14 DACDR13 DACDR12 DACDR11 DACDR10 DACDR9 DACDR8 Initial value : 00H DACDR[15:8] D/A Converter High Data (8-bit) DACDRL (D/A Converter Data Low Register) : 40C2H (XSFR)
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MC97F60128 ABOV Semiconductor Co., Ltd. DACCR (D/A Converter Control Register) : 40C0H (XSFR) DACIE DACIFR ADATID DACBC FADFEN DACRLDS1 DACRLDS0 DACEN Initial value : 00H DACIE Enable or Disable D/AC Interrupt Disable Enable When D/AC Interrupt occurs, this bit becomes ‘1’. The flag is cleared only by writing a DACIFR ‘0’...
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MC97F60128 ABOV Semiconductor Co., Ltd. DACIFCR (D/AC Interface Control Register) : 40C9H (XSFR) – DACIFEN LDACB3FS LDACB2FS CSB3FS CSB2FS SPISEL MDSEL – Initial value : 00H PGS[3:0] D/AC Interface Enable Bit Disable Enable LDACB3FS LDACB3 Function Selection Bit. This bit is effective only when the P3FSRH[6:5] bits are set to “00b”, the SPISEL bit is set to “1b”, the DACIFEN bit is set to “1b”...
MC97F60128 ABOV Semiconductor Co., Ltd. 11.16 LCD Driver 11.16.1 Overview The LCD driver is controlled by the LCD control register (LCDCRH/L) and LCD driver contrast control register (LCDCCR). The LCLK[1:0] determines the frequency of COM signal scanning of each segment output. A RESET clears the LCD control register LCDCRH, LCDCRL and LCDCCR values to logic ‘0’.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.16.2 LCD Display RAM Organization Display data are stored to the display data area in the external data memory. The display data which stored to the display external data area (address 0000H-003FH) are read automatically and sent to the LCD driver by the hardware.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.16.5 LCD AUTOMATIC BIAS CONTROL Bias Mode A Bias Mode B Bias Mode A Bias Mode B ● ● ● ● Figure 11.97 Bias Mode A and Bias Mode B...
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MC97F60128 ABOV Semiconductor Co., Ltd. LCDCCR (LCD Driver Contrast Control Register) : 4009H (XSFR) LCTEN LCDCC3 LCDCC2 LCDCC1 LCDCC0 Initial value : 00H LCTEN Control LCD Driver Contrast LCD driver contrast disable LCD driver contrast enable LCDCC[3:0] VLCD0 Voltage Control when the contrast is enabled.
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MC97F60128 ABOV Semiconductor Co., Ltd. LCDBCR (LCD Automatic Bias Control Register) : 400CH (XSFR) LCDABC BMSEL2 BMSEL1 BMSEL0 BMODEB1 BMODEB0 BMODEA1 BMODEA0 Initial value : 00H LCDABC LCD Automatic Bias Control LCD Automatic Bias is Off LCD Automatic Bias is On (LCD contrast control function is disable when LCDABC=1) Select Bias A/B Mode Time (Refer to the Figure “LCD bias automatic control”)
MC97F60128 ABOV Semiconductor Co., Ltd. 11.17 The Fine ADPCM Decoder 11.17.1 Overview The fine ADPCM decoder has the decoder block to play voice promt and the interface block to read data of a serial flash memory. The fine ADPCM has eighteen registers which are the decoder control register (DECCR), decoder FIFO...
MC97F60128 ABOV Semiconductor Co., Ltd. 11.17.3 The Decoder Result Output of the FADPCM The decoder result output data (DODRH/L) are a 16-bit binary format. The data will be output every decoder match signal and the first data is 8000H after clear of decoder block by DIVS bit set to ‘1’. The match signal is generated twice in the interval time which is set for a sampling frequency.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.17.4 Serial Flash Interface by SPI2 or SPI3 The interface block with a serial flash memory are to automatically read the table data of voice prompt and the encoding data of the FADPCM format. One of the SPI2 and SPI3 can be selected for a serial interface with flash memory by SPICSS bit.
MC97F60128 ABOV Semiconductor Co., Ltd. 11.17.5 Voice Prompt Play The FADPCM decoder decodes the encoding data of FADPCM format every sampling frequency. The encoding data can be read from a serial flash memory through auto-interface function up to 16M-bytes. The decoding data can be played by the D/A converter.
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MC97F60128 ABOV Semiconductor Co., Ltd. - Voice prompt data fetch for play: ATRIGS[1:0] = “11b”, DUMY[3:0] = “n”, RDNO[2:0] = “Don’t care” This bit is automatically cleared to ‘0’ after being exection SFRDST MOSI SFCMD VPADDR1 VPADDR2 VPADDR3 DUMY1 DUMY2...
MC97F60128 ABOV Semiconductor Co., Ltd. 11.17.9 Register Description for FADPCM DFIFOR (FADPCM Decoder FIFO Register) : 40B1H (XSFR) DFIFOR7 DFIFOR6 DFIFOR5 DFIFOR4 DFIFOR3 DFIFOR2 DFIFOR1 DFIFOR0 Initial value : 00H DFIFOR[7:0] Decoder FIFO Data. The data goes to the decoder FIFO (8-bytes length) if data are written in this register.
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MC97F60128 ABOV Semiconductor Co., Ltd. VPSIZE3 (Voice Prompt Size Register 3) : 40BDH (XSFR) VPSZ7 VPSZ6 VPSZ5 VPSZ4 VPSZ3 VPSZ2 VPSZ1 VPSZ0 Initial value : 00H VPSZ[7:0] Voice Prompt Size LSB-byte. The VPSIZE[23:0] is the size of a voice prompt to play continuously in a serial flash.
12.1 Overview The MC97F60128 has two power-down modes to minimize the power consumption of the device. In power down mode, power consumption is reduced considerably. The device provides three kinds of power saving functions, Main- IDLE, Sub-IDLE and STOP mode. In three modes, program is stopped.
MC97F60128 ABOV Semiconductor Co., Ltd. 12.3 IDLE Mode The power control register is set to ‘01h’ to enter the IDLE Mode. In this mode, the internal oscillation circuits remain active. Oscillation continues and peripherals are operated normally but CPU stop. It is released by reset or interrupt. To be released by interrupt, interrupt should be enabled before IDLE mode.
MC97F60128 ABOV Semiconductor Co., Ltd. 12.4 STOP Mode The power control register is set to ‘03H’ to enter the STOP Mode. In the stop mode, the selected oscillator, system clock and peripheral clock is stopped, but watch timer can be continued to operate with sub clock. With the clock frozen, all functions are stopped, but the on-chip RAM and control registers are held.
MC97F60128 ABOV Semiconductor Co., Ltd. 12.5 Release Operation of STOP Mode After STOP mode is released, the operation begins according to content of related interrupt register just before STOP mode start (Figure 12.3). If the global interrupt Enable Flag (IE.EA) is set to `1`, the STOP mode is released by the interrupt which each interrupt enable flag = `1` and the CPU jumps to the relevant interrupt service routine.
MC97F60128 ABOV Semiconductor Co., Ltd. 12.6 Register Map Name Address Default Description PCON Power Control Register Table 12-2 Power Down Operation Register Map 12.7 Power Down Operation Register Description The power down operation register consists of the power control register (PCON).
Control Register Refer to the Peripheral Registers Table 13-1 Reset State 13.2 Reset Source The MC97F60128 has five types of reset sources. The following is the reset sources. − External RESETB − Power ON RESET (POR) − WDT Overflow Reset (In the case of WDTEN = `1`) −...
MC97F60128 ABOV Semiconductor Co., Ltd. 13.4 RESET Noise Canceller The Figure 13.2 is the noise canceller diagram for noise cancellation of RESET. It has the noise cancellation value of about 2us (@V =5V) to the low input of system reset.
MC97F60128 ABOV Semiconductor Co., Ltd. 13.5 Power on RESET When rising device power, the POR (Power On Reset) has a function to reset the device. If POR is used, it executes the device RESET function instead of the RESET IC or the RESET circuits.
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MC97F60128 ABOV Semiconductor Co., Ltd. Counting for config read start after POR is released Internal nPOR PAD RESETB “H” LVR_RESETB .. 27 28 BIT (for Config) 00 01 02 03 BIT (for Reset) 1us X 256 X 28h = about 10ms...
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MC97F60128 ABOV Semiconductor Co., Ltd. :VDD Input :Internal OSC ⑥ ④ Reset Release Config Read ② ⑦ ⑤ ① ③ Figure 13.6 Boot Process WaveForm Process Description Remarks ① -No Operation ② -1st POR level Detection -about 1.4V -(INT-OSC 8MHz/8)x256x28h Delay section (=10ms) ③...
MC97F60128 ABOV Semiconductor Co., Ltd. 13.6 External RESETB Input The External RESETB is the input to a Schmitt trigger. If RESETB pin is held with low for at least 10us over within the operating voltage range and stable oscillation, it is applied and the internal state is initialized. After reset state becomes ‘1’, it needs the stabilization time with 16ms and after the stable state, the internal RESET becomes ‘1’.
Brown Out Detector Processor The MC97F60128 has an On-chip brown-out detection circuit (BOD) for monitoring the VDD level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by LVRVS[3:0] bit to be 1.60V, 2.00V, 2.10V, 2.20V,2.32V, 2.44V, 2.59V, 2.75V, 2.93V, 3.14V, 3.38V, 3.67V, 4.00V, 4.40V.
MC97F60128 ABOV Semiconductor Co., Ltd. “H” “H” Internal nPOR “H” PAD RESETB LVR_RESETB ..27 28 00 01 02 BIT (for Config) BIT (for Reset) 1us X 256 X 28h = about 10ms Config Read 1us X 4096 X 4h = about 16ms...
MC97F60128 ABOV Semiconductor Co., Ltd. 13.9 Register Map Name Address Default Description LVICR Low Voltage Indicator Control Register RSTFR Reset Flag Register LVRCR Low Voltage Reset Control Register Table 13-3 Reset Operation Register Map 13.10 Reset Operation Register Description The reset control register consists of the reset flag register (RSTFR), low voltage reset control register (LVRCR) and...
MC97F60128 ABOV Semiconductor Co., Ltd. 13.11 Register Description for Reset Operation RSTFR (Reset Flag Register) : E8H – – PORF EXTRF WDTRF OCDRF LVRF FPRIRF – – Initial value : 80H Power-On Reset flag bit. The bit is reset by writing ‘0’ to this bit.
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MC97F60128 ABOV Semiconductor Co., Ltd. LVRCR (Low Voltage Reset Control Register) : D8H – – LVRST LVRVS3 LVRVS2 LVRVS1 LVRVS0 LVREN – – Initial value : 00H LVRST LVR Enable when Stop Release Not effect at stop release LVR enable at stop release NOTE) When this bit is ‘1’, the LVREN bit is cleared to ‘0’...
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MC97F60128 ABOV Semiconductor Co., Ltd. LVICR (Low Voltage Indicator Control Register) : 86H – – LVIF LVIEN LVILS3 LVILS2 LVILS1 LVILS0 – – Initial value : 00H LVIF Low Voltage Indicator Flag Bit No detection Detection LVIEN LVI Enable/Disable Disable...
Overview 14.1.1 Description On-chip debug system (OCD2) of MC97F60128 can be used for programming the non-volatile memories and on-chip debugging. Detail descriptions for programming via the OCD2 interface can be found in the following chapter. Figure 14.1 shows a block diagram of the OCD2 interface and the On-chip Debug system.
MC97F60128 ABOV Semiconductor Co., Ltd. 14.1.2 Feature • Two-wire external interface: 1-wire serial clock input, 1-wire bi-directional serial data bus • Debugger Access to: − All Internal Peripheral Units − Internal data RAM − Program Counter − Flash and Data EEPROM Memories •...
MC97F60128 ABOV Semiconductor Co., Ltd. 14.2 Two-Pin External Interface 14.2.1 Basic Transmission Packet • 10-bit packet transmission using two-pin interface. • packet consists of 8-bit data, 1-bit parity and 1-bit acknowledge. • Parity is even of ‘1’ for 8-bit data in transmitter.
MC97F60128 ABOV Semiconductor Co., Ltd. 14.2.2 Packet Transmission Timing Data Transfer 14.2.2.1 DSDA acknowledgement acknowledgement signal from receiver signal from receiver DSCL START STOP Figure 14.3 Data Transfer on the Twin Bus Bit Transfer 14.2.2.2 DSDA DSCL data line change...
MC97F60128 ABOV Semiconductor Co., Ltd. Start and Stop Condition 14.2.2.3 DSDA DSDA DSCL DSCL START condition STOP condition Figure 14.5 Start and Stop Condition Acknowledge Bit 14.2.2.4 Data output By transmitter no acknowledge Data output By receiver acknowledge DSCL from...
15.1.1 Description MC97F60128 incorporates flash memory to which a program can be written, erased and overwritten while mounted on the board. The flash memory can be read by ‘MOVC’ instruction and it can be programmed in OCD, serial ISP mode or user program mode.
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MC97F60128 ABOV Semiconductor Co., Ltd. FMCR (Flash Mode Control Register): FEH – – – – FMBUSY FMCR2 FMCR1 FMCR0 – – – – Initial value: 00H FMBUSY Flash Mode Busy Bit. This bit will be used for only debugger. No effect when “1” is written...
15.1.7 Protection Area (User program mode) MC97F60128 can program its own flash memory (protection area). The protection area can not be erased or programmed. The protection areas are available only when the PAEN bit is cleared to ‘0’, that is, enable protection area at the configure option 2 if it is needed.
MC97F60128 ABOV Semiconductor Co., Ltd. 15.1.8 Erase Mode The sector erase program procedure in user program mode Page buffer clear (FMCR=0x01) Write ‘0’ to page buffer Set flash sector address register (FSADRH/FSADRM/FSADRL). Set flash identification register (FIDR). (Note) Check the UserID for to prevent the invalid work Set flash mode control register (FMCR).
MC97F60128 ABOV Semiconductor Co., Ltd. 15.1.9 Write Mode The sector Write program procedure in user program mode Page buffer clear (FMCR=0x01) Write data to page buffer Set flash sector address register (FSADRH/FSADRM/FSADRL). Set flash identification register (FIDR). (Note1) Check the UserID for to prevent the invalid work Set flash mode control register (FMCR).
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MC97F60128 ABOV Semiconductor Co., Ltd. The Byte Write program procedure in user program mode Page buffer clear (FMCR=0x01) Write data to page buffer Set flash sector address register (FSADRH/FSADRM/FSADRL). Set flash identification register (FIDR). (Note1) Check the UserID for to prevent the invalid work Set flash mode control register (FMCR).
MC97F60128 ABOV Semiconductor Co., Ltd. 15.1.10 Protection for Invalid Erase/Write It should be taken care to the flash erase/write programming in code. You must make preparations for invalid jump to the flash erase/write code by malfunction, noise and power off.
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MC97F60128 ABOV Semiconductor Co., Ltd. The flash sector address (FSADRH/FSADRM/FSADRL) should always keep the address of the flash which is used for data area. For example, The FSADRH/FSADRM is always 0x01/0xff” if 0x01ff00 to 0x01ffff is used for data. Overview of main...
MC97F60128 ABOV Semiconductor Co., Ltd. Flow of Protection for Invalid Erase/Write 15.1.10.1 Start Work1 Decide to write/erase Set Flags on flash Work2 Check the flag for Match Write UserID1/2/3 UserID Work3 Check the UserID for Match Write/Erase Flash write/erase flash...
MC97F60128 ABOV Semiconductor Co., Ltd. 15.1.11 Read Mode The Reading program procedure in user program mode Load receive data from flash memory on MOVC instruction by indirectly addressing mode. Program Tip – reading EO,#0xF8 ;Set DPTR0 MEX2,#0x90 ;If used BANK1, set MCM and MCB is ‘1’, MEX3,#0x7F ;If used BANK0, set MCM and MCB is ‘0’,...
MC97F60128 ABOV Semiconductor Co., Ltd. Configure Option 16.1 Configure Option Control The data for configure option should be written in the configure option area (003EH – 003FH) by programmer (Writer tools). CONFIGURE OPTION 1 : ROM Address 003FH – –...
MC97F60128 ABOV Semiconductor Co., Ltd. APPENDIX 17.1 Instruction Table Instructions are either1, 2 or 3bytes long as listed in the ‘Bytes’ column below. Each instruction takes either 1, 2 or 4 machine cycles to execute as listed in the following table. 1 machine cycle comprises 2 system clock cycles.
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MC97F60128 ABOV Semiconductor Co., Ltd. LOGICAL Mnemonic Description Bytes Cycles Hex code ANL A,Rn AND register to A 58-5F ANL A,dir AND direct byte to A ANL A,@Ri AND indirect memory to A 56-57 ANL A,#data AND immediate to A...
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MC97F60128 ABOV Semiconductor Co., Ltd. DATA TRANSFER Mnemonic Description Bytes Cycles Hex code MOV A,Rn Move register to A E8-EF MOV A,dir Move direct byte to A MOV A,@Ri Move indirect memory to A E6-E7 MOV A,#data Move immediate to A...
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MC97F60128 ABOV Semiconductor Co., Ltd. BRANCHING Mnemonic Description Bytes Cycles Hex code ACALL addr 11 Absolute jump to subroutine 11→F1 LCALL addr 16 Long jump to subroutine Return from subroutine RETI Return from interrupt AJMP addr 11 Absolute jump unconditional 01→E1...
MC97F60128 ABOV Semiconductor Co., Ltd. 17.2 Flash Protection for Invalid Erase/Write Overview This is example to prevent changing code or data in flash by abnormal operation(noise, unstable power, malfunction, etc…). How to protect the flash • Divide into decision and execution to Erase/Write in flash.
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MC97F60128 ABOV Semiconductor Co., Ltd. Flowchart Start Initial ① Set LVR/LVI more than 2.0V Start Main Loop Working ③ Write Flash? Set User_ID1 ② Working ③ Check User_ID1? Set User_ID2 Working Check User_ID2? Set User_ID3 ③ Working Write Flash Set FSADDRH/M/L ④...
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Initialize User_ID1/2/3 Set Flash Sector Address to Dummy Address • Sample Source Refer to the ABOV homepage. It is created based on the MC97F2664. Each product should be modified according to the Page Buffer Size and Flash Size Etc •...
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