Clock Generator; Oscillation Circuit - Abov MC80F0304 User Manual

MC80F0304/08/16

10. CLOCK GENERATOR

As shown in Figure 10-1 , the clock generator produces the basic through a divide-by-two flip-flop, but minimum and maximum
clock pulses which provide the system clock to be supplied to the high and low times specified on the data sheet must be observed.
CPU and the peripheral hardware. It contains main-frequency To the peripheral block, the clock among the not-divided original
tained by attaching a crystal or a ceramic resonator between the clock oscillator. The system clock operation can be easily ob- clock, clocks divided by 1, 2, 4,..., up to 4096 can be provided.
IN X and X OUT pin, respectively. The system clock can also be ob- peripheral clock is controlled by clock control register Peripheral clock is enabled or disabled by STOP instruction. The
tained from the external oscillator. In this case, it is necessary to (CKCTLR). See "11. BASIC INTERVAL TIMER" on page 53
input a external clock signal to the X pin. There are no requirements on the duty cycle of the external IN pin and open the X OUT for details.
clock signal, since the input to the internal clocking circuitry is
STOP
INOSC
INOSC SLEEP
Main OSC Stop
X IN OSC Circuit ONP Circuit XIN f Clock Pulse
OUT X EX f Generator ( 2) ÷ system clock Internal
MUX
Int OSC Circuit INCLK
INOSC
PRESCALER
IN4MCLKXO/IN2MCLKXO) INOSC (IN4MCLK/IN2MCLK/ PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12
7 ~ 3 2 ~ 0 1 ÷ ÷ 2 ÷ 4 8 ÷ ÷ 16 ÷ 32 ÷ 64 ÷ 128 256 ÷ 512 ÷ ÷ 1024 ÷ 2048 ÷ 4096
Configuration Option Register (20FF ) H Peripheral clock
f EX (Hz) PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12
Frequency 4M 2M 1M 500K 250K 125K 62.5K 31.25K 15.63K 7.183K 3.906K 1.953K 976
4M period 250n 500n 1u 2u 4u 8u 16u 32u 64u 128u 256u 512u 1.024m
Figure 10-1 Block Diagram of Clock Generator

10.1 Oscillation Circuit

IN amplifier which can be set for use as an on-chip oscillator, as X and X OUT are the input and output, respectively, a inverting
shown in Figure 10-2 . Note: When using a system clock oscillator, carry out wiring in
the broken line area in Figure 10-2 to prevent any effects from wir-
C1 Xout ing capacities. - Minimize the wiring length.
C2 - Do not allow wiring to intersect with other signal conductors.
Xin - Set the potential of the grounding position of the oscillator capac- - Do not allow wiring to come near changing high current.
Vss itor to that of V SS . Do not ground to any ground pattern where high
- Do not fetch signals from the oscillator. current is present.
Figure 10-2 Oscillator Connections
November 4, 2011 Ver 2.12 51