Basic Interval Timer - Abov MC80F0304 User Manual

MC80F0304/08/16

11. BASIC INTERVAL TIMER

The MC80F0304/0308/0316 has one 8-bit Basic Interval Timer If the STOP instruction executed after writing "1" to bit RCWDT
that is free-run and can not stop. Block diagram is shown in Fig- of CKCTLR, it goes into the internal RC oscillated watchdog tim-
ure 11-1 . In addition, the Basic Interval Timer generates the time er mode. In this mode, all of the block is halted except the internal
base for watchdog timer counting. It also provides a Basic inter- val timer interrupt (BITIF). RC oscillator, Basic Interval Timer and Watchdog Timer. More detail informations are explained in Power Saving Function. The
The 8-bit Basic interval timer register (BITR) is increased every bit WDTON decides Watchdog Timer or the normal 7-bit timer.
internal count pulse which is divided by prescaler. Since prescal- Source clock can be selected by lower 3 bits of CKCTLR.
er has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024 BITR and CKCTLR are located at same address, and address
00H, this overflow causes the interrupt to be generated. of the oscillator frequency. As the count overflow from FFH to 0F2 is read as a BITR, and written to CKCTLR. H
The Basic Interval Timer is controlled by the clock control regis- Note: All control bits of Basic interval timer are in CKCTLR reg-
ter (CKCTLR) shown in Figure 11-2. If the RCWDT bit is set to ister which is located at same address of BITR (address EC ). Ad- H
"1", the clock source of the BITR is changed to the internal RC CKCTLR can not be accessed by bit manipulation instruction. dress EC H is read as BITR, written to CKCTLR. Therefore, the
oscillation.
When write "1" to bit BTCL of CKCTLR, BITR register is cleared to "0" and restart to count-up. The bit BTCL becomes "0"
after one machine cycle by hardware.
Internal RC OSC
RCWDT
÷8 ÷16 1 source 8-bit up-counter Basic Interval
÷32 clock BITR overflow BITIF Timer Interrupt
X IN PIN ÷64 ÷128 MUX 0 [0F2 ]
÷512 ÷256 H clear To Watchdog timer (WDTCK)
÷1024
Select Input clock 3 BCK[2:0]
[0F2 H ] CKCTLR RCWDT BTCL
Basic Interval Timer Read
clock control register
Internal bus line
Figure 11-1 Block Diagram of Basic Interval Timer
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