Interrupts - Abov MC80F0304 User Manual

MC80F0304/08/16

18. INTERRUPTS

enable register (IENH, IENL), Interrupt request flags of IRQH, The MC80F0304/0308/0316 interrupt circuits consist of Interrupt T2IF and T3IF which is set by a match in their respective timer/ The Timer 0 ~ Timer 3 Interrupts are generated by T0IF, T1IF,
IRQL, Priority circuit, and Master enable flag ("I" flag of PSW). counter register.
Fifteen interrupt sources are provided. The configuration of inter- The Basic Interval Timer Interrupt is generated by BITIF which
shown in Table 18-1. rupt circuit is shown in Figure 18-1 and interrupt priority is is set by an overflow in the timer register.
The External Interrupts INT0 ~ INT3 each can be transition-acti- The AD converter Interrupt is generated by ADCIF which is set
vated (1-to-0 or 0-to-1 transition) by selection IEDS register. by finishing the analog to digital conversion.
The flags that actually generate these interrupts are bit INT0IF, The Watchdog timer is generated by WDTIF which is set by a
interrupt is generated, the generated flag is cleared by the hard- INT1IF, INT2IF and INT3IF in register IRQH. When an external match in Watchdog timer register.
ware when the service routine is vectored to only if the interrupt
was transition-activated.
Internal bus line
[0EA ]
H IENH Interrupt Enable "EI" instruction. When it goes interrupt service, I-flag is in PSW, it is cleared by "DI", set by
IRQH Register (Higher byte) I-flag is cleared by hardware, thus any other interrupt are inhibited. When interrupt service is
[0EC H ] "1" by hardware. completed by "RETI" instruction, I-flag is set to
INT0 INT0IF
INT1 INT1IF Release STOP/SLEEP
INT3 INT2 INT2IF INT3IF
UART Rx UARTRIF
UART Tx UARTTIF To CPU
Serial SIOIF
Communication Timer 0 T0IF Interrupt Master I-flag
[0ED IRQL ] Enable Flag
Timer 1 H T1IF Interrupt
Timer 2 T2IF Vector
Timer 3 T3IF Address Generator
A/D Converter ADCIF
Watchdog Timer WDTIF
BIT BITIF
[0EB ] H IENL Register (Lower byte) Interrupt Enable
Internal bus line
Figure 18-1 Block Diagram of Interrupt
The Basic Interval Timer Interrupt is generated by BITIF which is set by a overflow in the timer counter register.
94 November 4, 2011 Ver 2.12