Example Of A Misaligned Long-Word Transfer; Example Of Misaligned Word Transfer - Motorola M68060 User Manual

Bus Operation
Figure 7-9 illustrates the transfer of a long-word operand from an odd address requiring
more than one bus cycle. For the first transfer or bus cycle, the SIZx signals specify a byte
transfer, and the byte offset is $1. The slave device supplies the byte and acknowledges the
data transfer. When the processor starts the second cycle, the SIZx signals specify a word
transfer with a byte offset of $2. The next two bytes are transferred during this cycle. The
processor then initiates the third cycle, with the SIZx signals indicating a byte transfer. The
byte offset is now $0; the port supplies the final byte and the operation is complete. This
example is similar to the one illustrated in Figure 7-10 except that the operand is word sized
and the transfer requires only two bus cycles. Figure 7-11 illustrates a functional timing dia-
gram for a misaligned long-word read transfer.
31
OP0
31
X
X
OP3
31
XXX
OP3
Figure 7-9. Example of a Misaligned Long-Word Transfer
31
—
31
—
OP3
31
XXX
OP3
Figure 7-10. Example of Misaligned Word Transfer
7-10
MOVE.L D0,$XXXXXXX1
REGISTER
24 23 16 15
OP1
DATA BUS
24 23 16 15
OP0
X
X
MEMORY
24 23 16 15
OP0
XXX
MOVE.W D0,$XXXXXXX3
Register
24 23 16 15
—
DATA BUS
24 23 16 15
—
—
MEMORY
24 23 16 15
XXX
XXX
M68060 USER'S MANUAL
8 7
OP2 OP3
8 7
X X
OP1 OP2
X X
8 7
OP1 OP2
XXX XXX
8 7
OP2 OP3
8 7
— OP2
— —
8 7
XXX OP2
XXX XXX
0
0
TRANSFER 1
TRANSFER 2
TRANSFER 3
0
0
0
TRANSFER 1
TRANSFER 2
0
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