Instruction Cache Line State Diagram; Instruction Cache Line State Transitions - Motorola M68060 User Manual

Table 5-2. Instruction Cache Line State Transitions
Cache Operation
IPU Read Miss
IPU Read Hit
Cache Invalidate or Push
(CINV or CPUSH)
Alternate Master Snoop Hit
(Read or Write)
Alternate Master Snoop Miss I5 Not possible.
TCI Asserted on Read Miss
(during the First Access)
Figure 5-6. Instruction Cache Line State Diagram
5.12.2 Data Cache
The integer unit uses the data cache to store operand data as it requires or generates the
data. The data cache supports a line-based protocol allowing individual cache lines to be in
one of three states: invalid, valid, or dirty. To maintain coherency with memory, the data
cache supports both writethrough and copyback modes, specified by the CM field for the
page.
MOTOROLA
Invalid Cases
I1 Read line from memory; supply data to
IPU and update cache; go to valid state. V1
I2 Not Possible.
I3 No action; remain in current state.
I4 Not possible.
I6 Read line for memory; Supply data to
the IPU; remain in current state.
I3—CINV/CPUSH
I6—TCI ASSERTED
I1—IPU READ MISS
INVALID
V3—CINV/CPUSH
V4—SNOOP READ/WRITE HIT
M68060 USER'S MANUAL
Current State
Valid Cases
Read line from memory; supply data to
IPU and update cache (replacing old
line); remain in current state.
V2 Suppply data to IPU; remain in current
state.
V3 No action; go to invalid state.
V4 No action; go to invalid state.
V5 No action; remain in current state.
V6 Not Possible.
V1—IPU READ MISS
V2—IPU READ HIT
V5—SNOOP MISS
VALID
Caches
5-17