Byte, Word, And Long-Word Read Bus Cycle Timing - Motorola M68060 User Manual

Bus Operation
BCLK
ADDRESS AND
ATTRIBUTES
R/W
A1–A0
SIZ1–SIZ0
TS
TIP
TA
SAS
BS0
BS1
BS2
BS3
D31–D24
D23–D16
D15–D8
D7–D0
NOTE: It is assumed that the acknowledge termination ignore state capability is disabled.
Figure 7-13. Byte, Word, and Long-Word Read Bus Cycle Timing
The processor asserts transfer start (TS) during C1 to indicate the beginning of a bus cy-
cle. If not already asserted from a previous bus cycle, the transfer in progress (TIP) signal
is also asserted at this time to indicate that a bus cycle is active.
7-14
C1 C2 C1
1
BYTE
WORD READ
BYTE READ
WITH WAIT
M68060 USER'S MANUAL
CW C2 C1
2
WORD LONG
LONG-WORD
READ
C2
0
MOTOROLA