Motorola M68060 User Manual page 60

Signal Description
nal peripheral devices. Refer to Section 7 Bus Operation for bus information related to
interrupts and to Section 8 Exception Processing for interrupt information.
2.9.3 Autovector (AVEC)
This input signal is asserted with TA during an interrupt acknowledge bus cycle to request
internal generation of the vector number. Refer to Section 7 Bus Operation for more infor-
mation about automatic vectors.
2.10 STATUS AND CLOCK SIGNALS
The following paragraphs describe the signals that provide timing and the internal processor
status.
2.10.1 Processor Status (PST4–PST0)
These outputs indicate the internal execution unit status. The timing is synchronous with the
MC68060 processor clock (CLK), and the status may have nothing to do with the current
bus transfer. Table 2-7 lists the definition of the PSTx encodings.
The encodings $16, $17, and $1C indicate the present status and do not reflect a specific
stage of the pipe. These encodings persist as long as the processor stays in the indicated
state. The default encoding $00 is indicated if none of the above conditions apply. Most
other encodings indicate that the instruction is in its last instruction execution stage. These
encodings exist for only one CLK period per instruction and are mutually exclusive.
In general, the PSTx bits indicate the following information:
PST4 = Supervisor Mode
PST3 = Branch Instruction
PST2 = Taken Branch Instruction
PST1, PST0 = Number of Instructions Completed that Cycle
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