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Motorola M68MPB16Z1 User Manual

Mcu personality board
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M68MPB16Z1UM/D
REV 1
March 1998
M68MPB16Z1
MCU PERSONALITY BOARD
USER'S MANUAL
© MOTOROLA, INC., 1994, 1998; All Rights Reserved

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  • Page 1 M68MPB16Z1UM/D REV 1 March 1998 M68MPB16Z1 MCU PERSONALITY BOARD USER’S MANUAL © MOTOROLA, INC., 1994, 1998; All Rights Reserved...
  • Page 2 Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur.

  • Page 3: Table Of Contents

    CONTENTS CONTENTS CHAPTER 1 GENERAL INFORMATION INTRODUCTION......................1-1 SPECIFICATIONS ......................1-2 EQUIPMENT REQUIRED....................1-2 CUSTOMER SUPPORT ....................1-3 CHAPTER 2 HARDWARE PREPARATION AND INSTALLATION INTRODUCTION......................2-1 HARDWARE PREPARATION ..................2-1 2.2.1 Clock Select Header (W1) ..................2-4 2.2.2 VDDA Select Header (W2) ..................2-5 2.2.3 Voltage Reference High Select Header (W3)............
  • Page 4 CONTENTS CHAPTER 5 MAPI SUPPORT INFORMATION INTRODUCTION......................5-1 MAPI BUS CONNECTORS .................... 5-1 CHAPTER 6 SCHEMATIC DIAGRAMS INTRODUCTION......................6-1 FIGURE 2-1. MPB Parts Location Diagram (top view)................2-2 2-2. MPB – MPFB Interconnection (with SDI interface connector)........2-9 2-3. Active Probe Interconnection (with Active Probe Box) ..........2-11 5-1.

  • Page 5: Chapter 1 General Information

    GENERAL INFORMATION 1.1 INTRODUCTION This manual provides general information, hardware preparation, installation instructions, a quick start guide, and support information for the M68MPB16Z1 MCU Personality Board (MPB). The MPB is one component of Motorola’s modular approach to MC68HC16Z1 Microcontroller Unit-based product development.

  • Page 6: Specifications

    1.3 EQUIPMENT REQUIRED The external requirements for MPB operation are either an MEVB or MMDS system. For MMDS operation requirements, see the MMDS1632 Motorola Modular Development System User’s Manual, MMDS1632UM/D. For operation requirements for the MEVB, see this manual and the M68MPFB Modular Platform Board User’s Manual, M68MPFBUM/D.

  • Page 7: Customer Support

    GENERAL INFORMATION 1.4 CUSTOMER SUPPORT For information about a Motorola distributor or sales office near you call: AUSTRALIA, Melbourne – (61-3)887-0711 JAPAN, Fukuoka – 81-92-725-7583 Sydney – 61(2)906-3855 Gotanda – 81-3-5487-8311 Nagoya – 81-52-232-3500 BRAZIL, Sao Paulo – 55(11)815-4200 Osaka – 81-6-305-1802 Sendai –...
  • Page 8 GENERAL INFORMATION M68MPB16Z1UM/D...

  • Page 9: Chapter 2 Hardware Preparation And Installation

    HARDWARE PREPARATION AND INSTALLATION CHAPTER 2 HARDWARE PREPARATION AND INSTALLATION 2.1 INTRODUCTION This chapter provides unpacking instructions, hardware preparation information, and installation instructions for the MPB. When you unpack the MPB from its shipping carton, verify that all items are in good condition.
  • Page 10 HARDWARE PREPARATION AND INSTALLATION CAUTION Depending on your application, it may be necessary to cut the W2 wiring trace short (cut-trace short). Be careful not to cut adjacent PCB traces, nor cut too deep into the multi-layer circuit board. If the cut-trace short on a jumper header is already cut, you can return the MPB to its default setting by installing a user-supplied fabricated jumper.

  • Page 11: Jumper Header Types

    HARDWARE PREPARATION AND INSTALLATION Table 2-1. Jumper Header Types Jumper Header Type Symbol Description two-pin with cut-trace Two-pin jumper header with cut-trace short, designated WX, short where X = the jumper header number. If you cut the short, use a fabricated jumper to return the jumper header to its factory default state.

  • Page 12: Clock Select Header (W1)

    HARDWARE PREPARATION AND INSTALLATION 2.2.1 Clock Select Header (W1) Jumper header W1 connects the MCU external clock (EXTAL) pin to either an on-board or external (target-system) clock source. The drawing below shows the factory configuration: a fabricated jumper on pins 1 and 2. This configuration selects the MPB on-board clock source;...

  • Page 13: Vdda Select Header (W2)

    HARDWARE PREPARATION AND INSTALLATION 2.2.2 VDDA Select Header (W2) Jumper header W2 selects the MPB VDDA power source: either MPB power (VDDI) or an external source. The drawing below shows the factory configuration: a cut-trace short between pins 1 and 2. This configuration connects filtered VDDI to VDDA.

  • Page 14: Voltage Reference High Select Header (W3)

    HARDWARE PREPARATION AND INSTALLATION 2.2.3 Voltage Reference High Select Header (W3) Jumper header W3 selects the voltage reference high (VRH) source: either MPB power (VDDA) or an external VRH source. The drawing below shows the factory configuration: a fabricated jumper on pins 1 and 2. This configuration selects VDDA as the VRH source.

  • Page 15: Voltage Reference Low Select Header (W4)

    HARDWARE PREPARATION AND INSTALLATION 2.2.4 Voltage Reference Low Select Header (W4) Jumper header W4 selects the voltage reference low (VRL) source: either MPB power (VSSA) or an external VRL source. The drawing below shows the factory configuration: a fabricated jumper on pins 1 and 2. This configuration selects VSSA as the VRL source.

  • Page 16: Mevb Configuration

    HARDWARE PREPARATION AND INSTALLATION 2.3 MEVB CONFIGURATION The MEVB contains: • MPB – MCU-device-specific board that defines the MCU to be evaluated. • M68MPFB1632 Modular Platform Board (MPFB) – which provides the interface connections to the host computer, logic analyzer connections, and the platform for installing the MPB.
  • Page 17 HARDWARE PREPARATION AND INSTALLATION Figure 2-2. MPB – MPFB Interconnection (with SDI interface connector) After you have installed the MPB, install the plastic overlay on the MPFB: place the overlay over logic analyzer connectors J12 through J20 and press down. Holes in the overlay slide down over plastic clips on the MPFB.

  • Page 18: Active Probe Configuration

    HARDWARE PREPARATION AND INSTALLATION 2.4 ACTIVE PROBE CONFIGURATION The M68MMDS1632 Motorola Modular Development System (MMDS) consists of the station module and an active probe. The active probe consists of a three board set, two cables, and a box: • MPB – MCU-device-specific board that defines the MCU to be evaluated.
  • Page 19 HARDWARE PREPARATION AND INSTALLATION 4. Connect one end of the 01-RE90341W01 REV 0 active probe cable to connector P6 on the MMDS control board; connect the other end to connector J6 on the TCB. Connect one end of the 01-RE90340W01 REV 0 active probe cable to connector P5 on the MMDS control board;...
  • Page 20 HARDWARE PREPARATION AND INSTALLATION 2-12 M68MPB16Z1UM/D...

  • Page 21: Chapter 3 Mevb Quick Start Guide

    3.1 INTRODUCTION This quick start guide is intended for the user who may not be familiar with Motorola’s development tools. This chapter explains the MEVB hardware and software set-up for M68MEVB16Z1 operation. Hardware set-up consists of configuring the MPB and MPFB jumper headers; software set-up consists of installing and running the appropriate macro script file within the debugger.

  • Page 22: Mpfb Jumper Headers

    MEVB QUICK START GUIDE 3.2.2 MPFB Jumper Headers Configure your MPFB jumper headers per the instructions in Table 3-1. Table 3-1 contains information exclusively intended for quick start and ignores the other jumper headers. Table 3-1. MPFB Quick Start Jumper Header Configuration Jumper Header Type...

  • Page 23: Mevb Installation Instructions

    MEVB QUICK START GUIDE Table 3-1. MPFB Quick Start Jumper Header Configuration (continued) Jumper Header Type Description 1 2 3 Jumper header W14 selects the MCU signal for the memory devices in the fast RAM sockets (U9 & U10) and pseudo ROM sockets (U2 & U4). Pins 1 and 2 select the MCU chip select for the memory devices in the fast RAM sockets.

  • Page 24: Power Supply - Mpfb Connection

    MEVB QUICK START GUIDE 3.3.1 Power Supply – MPFB Connection Use MPFB connector J5 to connect a user-supplied power supply to the MEVB. Contact 1 is ground; black lever. Contact 2 is VDD (+5 volts); red lever. Use 20 or 22 AWG wire for power connections. For each wire, trim back the insulation 1/4 in.

  • Page 25: Personal Computer - Bdm Connection

    MEVB QUICK START GUIDE 3.3.2 Personal Computer – BDM Connection Personal computer communication with the MEVB requires background debug mode (BDM) hardware. Connect your BDM hardware between your computer’s I/O port and the BDM header on the MPFB (MPFB connector J6). The drawing below shows signal assignments for connector J6.
  • Page 26 RAMBAH FFB04 symbol RAMMCR FFB00 Set SRAM base address dmmw RAMBAH 0001 Turn on SRAM dmmb RAMMCR 00 Check SRAM: Write Motorola 68HC16 Advanced MCUs dmml 10000 4D6F746F dmml 10004 726F6C61 dmml 10008 20363848 dmml 1000C 43313620 dmml 10010 41647661...

  • Page 27: Chapter 4 Mevb Support Information

    4.2 LOGIC ANALYZER CONNECTOR SIGNALS The tables of this chapter describe MPFB logic analyzer connector signals if you install an M68MPB16Z1 on the MPFB. The signal descriptions on J12 – J20 are the logic analyzer pin-outs on the plastic overlay supplied with the MPB.

  • Page 28: Logic Analyzer Connector J7 Pin Assignments

    MEVB SUPPORT INFORMATION Table 4-1. Logic Analyzer Connector J7 Pin Assignments Mnemonic Signal 1, 2 SPARE No connection OE(ALL) I/O PRU OUTPUT ENABLE – Input, active high; when low disables all PRU outputs. 4 – 11 PEPAR7 – PEPAR OUTPUTS – Output signals that show the complement (negated contents) of the PEPAR register.

  • Page 29: Logic Analyzer Connector J9 Pin Assignments

    MEVB SUPPORT INFORMATION Table 4-3. Logic Analyzer Connector J9 Pin Assignments Mnemonic Signal 1, 2 SPARE No connection OE(H) I/O PRU OUTPUT ENABLE – Input, active high; when low disables the port H outputs. 4 – 11 PH7 – PH0 PORT H I/O SIGNALS –...

  • Page 30: Logic Analyzer Connector J11 Pin Assignments

    MEVB SUPPORT INFORMATION Table 4-5. Logic Analyzer Connector J11 Pin Assignments Mnemonic Signal +5 VDC POWER – Input voltage (+5Vdc @ 1.0 A) used by the MEVB logic circuits. (To make this pin a no connection, remove the jumper from the jumper header W9 on the MPFB.) SPARE No connection...
  • Page 31 MEVB SUPPORT INFORMATION Table 4-6. Logic Analyzer Connector J12 Pin Assignments (continued) Mnemonic Signal LAT-DSI LATCHED INSTRUCTION PIPE 1 – Latched output (Latched IPIPE1) signal of the first state of IPIPE1 for CPU16-based MCUs; indicates instruction pipeline activity. DSO / DEVELOPMENT SERIAL OUT –...

  • Page 32: Logic Analyzer Connector J13 Pin Assignments

    MEVB SUPPORT INFORMATION Table 4-6. Logic Analyzer Connector J12 Pin Assignments (continued) Mnemonic Signal SIZ0 TRANSFER SIZE – Output signal that indicate the number of bytes still to be transferred during this cycle. READ/WRITE – Output signal that indicates the direction of data transfer on the bus.
  • Page 33 MEVB SUPPORT INFORMATION Table 4-7. Logic Analyzer Connector J13 Pin Assignments (continued) Mnemonic Signal BR / BUS REQUEST – Active-low input signal that indicates an external device requires bus mastership. CHIP SELECT 0 – Output signal that selects peripheral or memory devices at programmed addresses. BG / BUS GRANT –...

  • Page 34: Logic Analyzer Connector J14 Pin Assignments

    MEVB SUPPORT INFORMATION Table 4-7. Logic Analyzer Connector J13 Pin Assignments (continued) Mnemonic Signal A19 / ADDRESS BUS BIT 19 – One bit of the 24-bit address bus. CHIP SELECT 6 – Output signal that selects peripheral or memory devices at programmed addresses. 17 –...

  • Page 35: Logic Analyzer Connector J15 Pin Assignments

    MEVB SUPPORT INFORMATION Table 4-9. Logic Analyzer Connector J15 Pin Assignments Mnemonic Signal 1 – 3 SPARE No connection 4 – 13 GROUND PCLK AUXILIARY TIMER CLOCK INPUT – External input clock source for the GPT. PWMB PULSE WIDTH MODULATION B – Repetitive output signals whose high time to low time ratio can be controlled by the CPU.

  • Page 36: Logic Analyzer Connector J17 Pin Assignments

    MEVB SUPPORT INFORMATION Table 4-10. Logic Analyzer Connector J16 Pin Assignments (continued) Mnemonic Signal OUTPUT COMPARE 2 – Output signal that is generated when the GPT timer counter (TCNT) and TOC2 comparator register contain the same value. OUTPUT COMPARE 3 – Output signal that is generated when the GPT timer counter (TCNT) and TOC3 comparator register contain the same value.

  • Page 37: Logic Analyzer Connector J18 Pin Assignments

    MEVB SUPPORT INFORMATION Table 4-11. Logic Analyzer Connector J17 Pin Assignments (continued) Mnemonic Signal GROUND SPI SERIAL CLOCK – In master mode, the clock signal from the SPI; in slave mode the clock signal to the SPI. MOSI MASTER-OUT, SLAVE-IN – Serial output from QSPI in master mode;...

  • Page 38: Logic Analyzer Connector J19 Pin Assignments

    MEVB SUPPORT INFORMATION Table 4-13. Logic Analyzer Connector J19 Pin Assignments Mnemonic Signal 1 – 4 SPARE No connection 5 – 10 GROUND 11, 12 IRQ7, IRQ6 TARGET INTERRUPT REQUEST 7 and 6 - Active-low input signals from the target that asynchronously provides an interrupt priority level to the CPU.

  • Page 39: Chapter 5 Mapi Support Information

    MAPI SUPPORT INFORMATION CHAPTER 5 MAPI SUPPORT INFORMATION 5.1 INTRODUCTION This chapter information pertains to installing the MPB on a target system. The figures in this chapter show the MAPI interface connector layout and pin assignments for MPB connectors P1, P2, P3, and P4 (Figures 5-1 through 5-5). 5.2 MAPI BUS CONNECTORS The connectors required to interface to the MAPI bus are: 2 –...

  • Page 40: Mapi Interface Connector P1 Pin Assignments

    MAPI SUPPORT INFORMATION PCS0 / SS MOSI MISO IC4 / OC5 PWMA PWMB PCLK A23 / CS10 / ECLK A22 / CS9 A21 / CS8 A20 / CS7 A19 / CS6 FC2 / CS5 FC1 / CS4 FC0 / CS3 BGACK / CS2 BG / CS1 BR / CS0...

  • Page 41: Mapi Interface Connector P2 Pin Assignments

    MAPI SUPPORT INFORMATION PCS0 / SS PCS1 PCS2 PCS3 No Connect No Connect VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA Figure 5-3. MAPI Interface Connector P2 Pin Assignments M68MPB16Z1UM/D...

  • Page 42: Mapi Interface Connector P3 Pin Assignments

    MAPI SUPPORT INFORMATION VSSA VSSA MAPI – VRH VSSA MAPI – VRL VSSA VSSA IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 VSTBY DSO / IPIPE0 DSI / IPIPE1 HALT RESET BERR BKPT / DSCLK TSTME / TSC FREEZE / QUOT MAPI –...

  • Page 43: Mapi Interface Connector P4 Pin Assignments

    MAPI SUPPORT INFORMATION DSACK0 DSACK1 AVEC PULL-UP (RMC) SIZ0 SIZ1 MODCLK No Connect Figure 5-5. MAPI Interface Connector P4 Pin Assignments M68MPB16Z1UM/D...
  • Page 44 MAPI SUPPORT INFORMATION M68MPB16Z1UM/D...

  • Page 45: Chapter 6 Schematic Diagrams

    SCHEMATIC DIAGRAMS CHAPTER 6 SCHEMATIC DIAGRAMS 6.1 INTRODUCTION This chapter contains the M68MPB16Z1 MCU Personality Board (MPB) schematic diagrams. These schematic diagrams are for reference only and may deviate slightly from the circuits on your MPB. M68MPB16Z1UM/D...
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  • Page 54 SCHEMATIC DIAGRAMS 6-10 M68MPB16Z1UM/D...

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