Programming Model - Motorola M68060 User Manual

Introduction
modifying the S-bit of the SR. After these instructions execute, the instruction pipeline is
flushed and is refilled from the appropriate address space.
The MC68060 integrates the functions of the integer unit, FPU, and MMU. The registers
depicted in the programming model (see Figure 1-2) provide operand storage and control
for these three units. The registers are partitioned into two levels of privilege modes: user
and supervisor. The user programming model is the same as the user programming model
of the MC68040, which consists of 16 general-purpose 32-bit registers, two control regis-
ters, eight 80-bit floating-point data registers, a floating-point control register, a floating-point
status register, and a floating-point instruction address register.
31
DATA
REGISTERS
ADDRESS
REGISTERS
31
Only system programmers can use the supervisor programming model to implement oper-
ating system functions, I/O control, and memory management subsystems. This supervisor/
1-12
0 79
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
FP INSTRUCTION ADDRESS REGISTER
A5
A6
A7/USP USER STACK POINTER
PC
PROGRAM COUNTER
CCR
CONDITION CODE REGISTER
USER PROGRAMMING MODEL
0
PCR
PROCESSOR CONFIGURATION REGISTER
A7/SSP SUPERVISOR STACK POINTER
(CCR) SR STATUS REGISTER (CCR IS ALSO SHOWN IN THE USER PROGRAMMING MODEL)
VBR VECTOR BASE REGISTER
SFC SOURCE FUNCTION CODE
DFC DESTINATION FUNCTION CODE
CACR CACHE CONTROL REGISTER
URP USER ROOT POINTER REGISTER
SRP SUPERVISOR ROOT POINTER REGISTER
TC TRANSLATION CONTROL REGISTER
DTT0 DATA TRANSPARENT TRANSLATION REGISTER 0
DTT1 DATA TRANSPARENT TRANSLATION REGISTER 1
ITT0 INSTRUCTION TRANSPARENT TRANSLATION REGISTER 0
ITT1 INSTRUCTION TRANSPARENT TRANSLATION REGISTER 1
BUSCR BUS CONTROL REGISTER
SUPERVISOR PROGRAMMING MODEL
Figure 1-2. Programming Model
M68060 USER'S MANUAL
FLOATING-POINT
DATA
REGISTERS
31
FP CONTROL REGISTER
FP STATUS REGISTER
0
FP0
FP1
FP2
FP3
FP4
FP5
FP6
FP7
0
15
FPCR
0
FPSR
FPIAR
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