Line Write Retry Bus Cycle Timing - Motorola M68060 User Manual

A31–A0
MISCELLANEOUS
ATTRIBUTES
SIZ1–SIZ0
D31–D0
MC68040
ACKNOWLEDGE
TERMINATION
MODE
NATIVE-MC68060
ACKNOWLEDGE
TERMINATION
MODE
7.9.3 Double Bus Fault
A double bus fault occurs when an access or address error occurs during the exception pro-
cessing sequence, e.g., the processor attempts to stack several words containing informa-
tion about the state of the machine while processing an access error exception. If a bus error
occurs during the stacking operation, the second error is considered a double bus fault and
the processor is halted.
The MC68060 indicates a double bus fault condition by continuously driving PSTx with an
encoded value of $1C until the processor is reset. Only an external reset operation can
restart a halted processor. The halted processor releases the external bus by negating BR
and forcing all outputs to a high-impedance state.
MOTOROLA
C1 C2
BCLK
LINE
R/W
TS
TIP
SAS
TRA
TA
TEA
TRA
TA
TEA
RETRY
SIGNALED
Figure 7-40. Line Write Retry Bus Cycle Timing
M68060 USER'S MANUAL
C1 C2 C3
RETRY CYCLE
Bus Operation
C4 C5
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