Agilent Technologies E4416A Service Manual page 105

4 Theory of Operation
The filter output is fed to a buffer amplifier which has a gain of 1.1. This
ensures that switching transients are not passed backwards into the filter and
provides a low impedance output for the HI_GAIN switch. The combined gain
of the buffer amplifier and filter is approximately unity. An attenuator and
switch circuit follows this. The attenuation can be set to 1 or 16. The
attenuation is controlled by the level of the signal prior to the filter, which is
sensed with a comparator and fed into a latch and the FPGA. Logic within the
FPGA controls the switches that select the applied attenuation and hence the
gain of the normal path. As the level sense occurs before the 100 ns delay of
the filter, the FPGA and attenuators have 100 ns to select the right gain for
presentation to the ADC. A differential amplifier with a gain of 3 follows the
attenuator.
The ADC has a bipolar range but the power signal is essentially unipolar.
To utilize the full ADC range an offset is summed in to the signal just prior to
the ADC in an offset summer circuit. The outputs of the summer are arranged
to give a full- scale negative input to the ADC, so it reads circa (but greater
than) - 2048 when zero volts is applied to the normal path input. (The ADC
range is - 2048 to 2047.) There is a further filter that removes high frequency
noise, originating in the amplifier chain, from the ADC input. It has a 20 MHz
theoretical cut- off (− 3 dB) frequency.
The ADC is a 12- bit converter running at 20 MHz. Samples from the ADC are
combined with the normal path gain setting and the sensor range to derive the
power measurement. The ADC output and the range control bits are fed to the
FPGA. The FPGA controls a triggered acquisition into SDRAM. The acquisition
parameters (such as pre- trigger, post trigger and trigger level) are controlled
by the main processor.
The DSP transfers the acquired samples into its local memory where it then
performs the required processing to enable the demanded measurements. This
includes range correction, digital filters, linearity correction, averaging
together with display trace processing. The DSP generates an interrupt to the
processor when results are ready.
The processor assembly communicates with the DSP through the FPGA. The
DSP is loaded with the appropriate program by the processor assembly
depending on sensor type and required measurement mode. The processor
assembly loads the FPGA using a serial configuration bus.
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E4416A/E4417A Power Meters Service Guide