Xilinx ZC702 User Manual page 3

Date Version
04/04/2013 1.2
ZC702 Board User Guide
UG850 (v1.2) April 4, 2013
Chapter 1, ZC702 Evaluation Board
Marvell 88E1116R throughout the document. The bullet just before
page 9 changed from PL JTAG header to PS JTAG header. In
callout 3, PC28F00AG18FE StrataFlash memory changed to 128 Mb,
N25Q128A11ESF40G. In callout 9, Marvell M88E1116R-BAB1C000 changed to
88E1116RA0-NNC1C000. Callout 30 for J59 and 31 for J60 were added. The
Zynq-7000 XC7Z020 AP SoC, page 12
added a link to Table 1-2. Table 1-2 was removed because it is a duplicate of
Table 1-10. Above Table 1-2, page
configuration option." In Table
default setting changed. Section
In I/O Voltage Rails, page
AP SoC" was changed to "There are four PL I/O banks available on the XC7Z020 AP
SoC." A note about DDR3 memory was added after
Flash Memory, page 19 and
changed to N25Q128A11ESF40G. In
configuration section of UG585..." was changed to add "The configuration and QSPI
section of UG585..." JTAG information in
In Figure 1-10 pin numbers 5 and 6 are swapped and in U76, IN2 and IN1 switched
places. In Table 1-10, SW10 became SW10[1:2] in the table column heading and the
default setting was added. In
jitter changed from 20 ppm to 50 ppm. In
changed to TI. Figure 1-15
Table 1-22, reference designator DS12 changed to DS14. U3 level shifter was
changed to TXS0104E in Figure 1-19
was updated. Figure 1-21
and PS_MIO8_LED0 and removed pin info. Section
added. The Figure 1-26 title changed. A paragraph about design criteria was added
to Power Management, page
graphical user interface precedes
description of U19 in Table
Appendix A, Default Switch and Jumper
changed from right to left.
Appendix C, Master UCF Listing: A reminder was added to use the latest UCF listing.
Minor changes were made to the list, and power and ground pin constraints were
removed.
Appendix D, Board Specifications: This appendix was added to the book.
Appendix F, Regulatory and Compliance
master answer record was added.
www.xilinx.com
Revision
Features: Marvell 88E1111 was changed to
description for callout 1 changed. Callout 29
15, "configuration option" was changed to "JTAG
1-2, the PLL Used mode row was removed and the
Encryption Key Backup Circuit, page 15
16, "There are four I/O banks available on the XC7Z020
Table 1-4, page
Figure 1-6, N25Q128A13ESF40F (Micron/Numonyx)
Quad-SPI Flash Memory, page
Figure 1-10
Processing System Clock Source, page
I2C Bus, page
is updated. R249 was added to
and Table 1-21. The
added two LEDs. Table 1-23
User PS Switches, page 46
55. A paragraph about the TI Fusion Digital Power
Table 1-30. Voltages were added to the
1-30. The TI link on page 58
Settings: In
Information: A link to the ZC702 board
Block Diagram,
Table 1-1, page 11,
was added.
17. In Quad-SPI
19, "The
and Table 1-10 was updated.
29, frequency
36, NXP semiconductor
Figure 1-17. In
User I/O, page 42 section
added Net Name PS_LED1
was
was updated.
Table A-1, SW16 position 4
3