Xilinx ZC702 User Manual page 26

X-Ref Target - Figure 1-10
14PIN_JTAG_TDI
To J2
14PIN_JTAG_TMS
Parallel Cable or
Platform Cable
(14 pins) 14PIN_JTAG_TCK
DIGILENT_TDI
To U23
DIGILENT_TMS
USB-to-JTAG
Digilent bridge
DIGILENT_TCK
20PIN_JTAG_TDI
To J58
20PIN_JTAG_TMS
Parallel Cable
(20 Pins)
20PIN_JTAG_TCK
Figure 1-10: PL JTAG Programming Source Analog Switch
DIP switch SW10[1:2] setting 01 selects the 14-pin header J2 for configuration using either
a Parallel Cable IV (PC4) or Platform Cable USB II. DIP switch SW10 setting 10 selects the
USB-to-JTAG Digilent bridge U23 for configuration over a Standard-A to Micro-B USB cable.
DIP switch SW10 setting 11 selects the JTAG 20-pin header at J58. The four JTAG signals TDI,
TDO, TCK, and TMS would be connected to J58 via flying leads from a JTAG cable. The 3-to-1
analog switch settings are shown in
ZC702 Board User Guide
UG850 (v1.2) April 4, 2013
U75
VCC3V3
TS5A3359
SP3T
ANALOG SWITCH
6
IN1
5
IN2
1
NO0
7
2
NO1 COM
3
NO2
4 8
GND V+
U76
TS5A3359
SP3T
ANALOG SWITCH
6
IN1
5
IN2
1
NO0
2 7
NO1
COM
3
NO2
4 8
GND V+
U77
TS5A3359
SP3T
ANALOG SWITCH
6
IN2
5
IN1
1 NO0
2 NO1 7
COM
3 NO2
4 8
GND V+
Table 1-10.
www.xilinx.com
Feature Descriptions
VCC3V3
4 3
SW10
SDA02H1SBD
1 2
JTAG_SEL_1
JTAG_SEL_2
R376
4.7kW
0.1 W
5%
R375
4.7kW
0.1 W
5%
GND
JTAG_TMS
JTAG_TCK
UG850_c1_10_030513
JTAG_TDI
26