Xilinx ZC702 User Manual page 70

#NET PHY_TX_CTRL
#NET PHY_RXD0
#NET PHY_RXD2
#NET PHY_RX_CTRL
#NET USB_DIR
#NET USB_NXT
#NET USB_DATA1
#NET USB_DATA3
#NET USB_DATA6
#NET SDIO_CLK_LS
#NET SDIO_DAT0_LS
#NET SDIO_DAT2_LS
#NET CAN_RXD_LS
#NET USB_UART_RX
#NET PS_SCL_MAIN
#NET PHY_MDC
#NET PS_SRST_B
#NET PS_DIP_SW0
#NET PHY_TX_CLK
#NET PHY_TXD1
#NET PHY_TXD3
#NET PHY_RX_CLK
#NET PHY_RXD1
#NET PHY_RXD3
#NET USB_DATA4
#NET USB_STP
#NET USB_DATA0
#NET USB_DATA2
#NET USB_CLKOUT
#NET USB_DATA5
#NET USB_DATA7
#NET SDIO_CMD_LS
#NET SDIO_DAT1_LS
#NET SDIO_CD_DAT3_LS
#NET CAN_TXD_LS
#NET USB_UART_TX
#NET PS_SDA_MAIN
#NET PHY_MDIO
#NET IIC_MUX_RESET_B_LS
#NET PS_DIP_SW1
#NET PHY_RESET_B_AND
#NET PS_LED1
#NET CAN_STB_B_LS
#NET PS_MIO8_LED0
#NET USB_RESET_B_AND
#NET QSPI_CLK
#NET QSPI_IO3
#NET QSPI_IO2
#NET QSPI_IO1
#NET QSPI_IO0
#NET QSPI_CS_B
#NET SDIO_SDDET
#NET PS_DDR3_RESET_B
#NET PS_DDR3_DQ3
#NET PS_DDR3_DQ1
#NET PS_DDR3_DQ6
#NET PS_DDR3_DQ7
#NET PS_DDR3_DM0
#NET PS_DDR3_DQS0_P
#NET PS_DDR3_DQS0_N
#NET PS_DDR3_DQ0
#NET PS_DDR3_DQ5
#NET PS_DDR3_DQ2
#NET PS_DDR3_DQ4
#NET PS_DDR3_DQ8
#NET PS_DDR3_DQ10
#NET PS_DDR3_DQ9
#NET PS_DDR3_DQ13
ZC702 Board User Guide
UG850 (v1.2) April 4, 2013
LOC = F11 ; # Bank 501 - PS_MIO21_501
LOC = E11 ; # Bank 501 - PS_MIO23_501
LOC = F12 ; # Bank 501 - PS_MIO25_501
LOC = D7 ; # Bank 501 - PS_MIO27_501
LOC = E8 ; # Bank 501 - PS_MIO29_501
LOC = F9 ; # Bank 501 - PS_MIO31_501
LOC = G13 ; # Bank 501 - PS_MIO33_501
LOC = F14 ; # Bank 501 - PS_MIO35_501
LOC = F13 ; # Bank 501 - PS_MIO38_501
LOC = E14 ; # Bank 501 - PS_MIO40_501
LOC = D8 ; # Bank 501 - PS_MIO42_501
LOC = E13 ; # Bank 501 - PS_MIO44_501
LOC = D12 ; # Bank 501 - PS_MIO46_501
LOC = D11 ; # Bank 501 - PS_MIO48_501
LOC = D13 ; # Bank 501 - PS_MIO50_501
LOC = D10 ; # Bank 501 - PS_MIO52_501
LOC = C9 ; # Bank 501 - PS_SRST_B_501
LOC = B6 ; # Bank 500 - PS_MIO14_500
LOC = D6 ; # Bank 501 - PS_MIO16_501
LOC = A7 ; # Bank 501 - PS_MIO18_501
LOC = A8 ; # Bank 501 - PS_MIO20_501
LOC = A14 ; # Bank 501 - PS_MIO22_501
LOC = B7 ; # Bank 501 - PS_MIO24_501
LOC = A13 ; # Bank 501 - PS_MIO26_501
LOC = A12 ; # Bank 501 - PS_MIO28_501
LOC = A11 ; # Bank 501 - PS_MIO30_501
LOC = C7 ; # Bank 501 - PS_MIO32_501
LOC = B12 ; # Bank 501 - PS_MIO34_501
LOC = A9 ; # Bank 501 - PS_MIO36_501
LOC = B14 ; # Bank 501 - PS_MIO37_501
LOC = C13 ; # Bank 501 - PS_MIO39_501
LOC = C8 ; # Bank 501 - PS_MIO41_501
LOC = B11 ; # Bank 501 - PS_MIO43_501
LOC = B9 ; # Bank 501 - PS_MIO45_501
LOC = B10 ; # Bank 501 - PS_MIO47_501
LOC = C14 ; # Bank 501 - PS_MIO49_501
LOC = C10 ; # Bank 501 - PS_MIO51_501
LOC = C12 ; # Bank 501 - PS_MIO53_501
LOC = A6 ; # Bank 500 - PS_MIO13_500
LOC = C5 ; # Bank 500 - PS_MIO12_500
LOC = B4 ; # Bank 500 - PS_MIO11_500
LOC = G7 ; # Bank 500 - PS_MIO10_500
LOC = C4 ; # Bank 500 - PS_MIO9_500
LOC = E5 ; # Bank 500 - PS_MIO8_500
LOC = D5 ; # Bank 500 - PS_MIO7_500
LOC = A4 ; # Bank 500 - PS_MIO6_500
LOC = A3 ; # Bank 500 - PS_MIO5_500
LOC = E4 ; # Bank 500 - PS_MIO4_500
LOC = F6 ; # Bank 500 - PS_MIO3_500
LOC = A2 ; # Bank 500 - PS_MIO2_500
LOC = A1 ; # Bank 500 - PS_MIO1_500
LOC = G6 ; # Bank 500 - PS_MIO0_500
LOC = F3 ; # Bank 502 - PS_DDR_DRST_B_502
LOC = D1 ; # Bank 502 - PS_DDR_DQ0_502
LOC = C3 ; # Bank 502 - PS_DDR_DQ1_502
LOC = B2 ; # Bank 502 - PS_DDR_DQ2_502
LOC = D3 ; # Bank 502 - PS_DDR_DQ3_502
LOC = B1 ; # Bank 502 - PS_DDR_DM0_502
LOC = C2 ; # Bank 502 - PS_DDR_DQS_P0_502
LOC = D2 ; # Bank 502 - PS_DDR_DQS_N0_502
LOC = E3 ; # Bank 502 - PS_DDR_DQ4_502
LOC = E1 ; # Bank 502 - PS_DDR_DQ5_502
LOC = F2 ; # Bank 502 - PS_DDR_DQ6_502
LOC = F1 ; # Bank 502 - PS_DDR_DQ7_502
LOC = G2 ; # Bank 502 - PS_DDR_DQ8_502
LOC = G1 ; # Bank 502 - PS_DDR_DQ9_502
LOC = L1 ; # Bank 502 - PS_DDR_DQ10_502
LOC = L2 ; # Bank 502 - PS_DDR_DQ11_502
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ZC702 Board UCF Listing
70