Xilinx ZC702 User Manual page 62

X-Ref Target - Figure 1-32
VADJ
Table 1-34 describes the XADC header J40 pin functions.
Table 1-34: XADC Header J40 Pinout
Net Name
VN, VP
XADC_VAUX0P, N
XADC_VAUX8N, P
DXP, DXN
XADC_AGND
XADC_VREF
XADC_VCC5V0
XADC_VCC_HEADER
VADJ
GND
XADC_GPIO_3, 2, 1, 0 19, 20, 17, 18
ZC702 Board User Guide
UG850 (v1.2) April 4, 2013
XADC_VN
XADC_VAUX0P
XADC_VCC5V0
XADC_VAUX8N
XADC_DXP
XADC_VREF
XADC_GPIO_1
XADC_GPIO_3
Figure 1-32: XADC Header (J40)
J19 Pin
Number
1, 2 Dedicated analog input channel for the XADC.
Auxiliary analog input channel 0. Also supports use as I/O inputs when
3, 6
anti alias capacitor is not present.
Auxiliary analog input channel 8. Also supports use as I/O inputs when
7, 8
anti alias capacitor is not present.
9, 12 Access to thermal diode.
4, 5, 10 Analog ground reference.
11 1.25V reference from the board.
13 Filtered 5V supply from board.
14 Analog 1.8V supply for XADC.
15 VCCO supply for bank which is the source of DIO pins.
16 Digital Ground (board) Reference
Digital I/O. These pins should come from the same bank. These IOs should
not be shared with other functions because they are required to support
three-state operation.
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J40
1 2
3 4
XADC_VAUX0N
5 6
7 8 XADC_VAUX8P
9 10
11 12
13 14 XADC_VCC_HEADER
15 16
17 18 XADC_GPIO_0
XADC_GPIO_2
19 20
GND
XADC_AGND XADC_AGND
UG850_c1_32_030513
Description
Feature Descriptions
XADC_VP
XADC_DXN
62