Xilinx ZC702 User Manual page 71

#NET PS_DDR3_DM1
#NET PS_DDR3_DQS1_P
#NET PS_DDR3_DQS1_N
#NET PS_DDR3_DQ12
#NET PS_DDR3_DQ11
#NET PS_DDR3_DQ14
#NET PS_DDR3_DQ15
#NET PS_DDR3_A14
#NET PS_DDR3_A13
#NET PS_DDR3_A12
#NET PS_DDR3_A11
#NET PS_DDR3_A10
#NET PS_DDR3_A9
#NET PS_DDR3_A8
#NET PS_DDR3_A7
#NET PS_DDR3_A6
#NET PS_DDR3_A5
#NET PS_DDR3_A4
#NET PS_DDR3_A3
#NET PS_VRN
#NET PS_VRP
#NET PS_DDR3_CLK_P
#NET PS_DDR3_CLK_N
#NET PS_DDR3_A2
#NET PS_DDR3_A1
#NET PS_DDR3_A0
#NET PS_DDR3_BA2
#NET PS_DDR3_BA1
#NET PS_DDR3_BA0
#NET PS_DDR3_ODT
#NET PS_DDR3_CS_B
#NET PS_DDR3_CKE
#NET PS_DDR3_WE_B
#NET PS_DDR3_CAS_B
#NET PS_DDR3_RAS_B
#NET PS_DDR3_DQ16
#NET PS_DDR3_DQ17
#NET PS_DDR3_DQ18
#NET PS_DDR3_DQ19
#NET PS_DDR3_DM2
#NET PS_DDR3_DQS2_P
#NET PS_DDR3_DQS2_N
#NET PS_DDR3_DQ20
#NET PS_DDR3_DQ21
#NET PS_DDR3_DQ22
#NET PS_DDR3_DQ23
#NET PS_DDR3_DQ27
#NET PS_DDR3_DQ24
#NET PS_DDR3_DQ25
#NET PS_DDR3_DQ26
#NET PS_DDR3_DM3
#NET PS_DDR3_DQS3_P
#NET PS_DDR3_DQS3_N
#NET PS_DDR3_DQ28
#NET PS_DDR3_DQ29
#NET PS_DDR3_DQ30
#NET PS_DDR3_DQ31
ZC702 Board User Guide
UG850 (v1.2) April 4, 2013
LOC = H3 ; # Bank 502 - PS_DDR_DM1_502
LOC = H2 ; # Bank 502 - PS_DDR_DQS_P1_502
LOC = J2 ; # Bank 502 - PS_DDR_DQS_N1_502
LOC = L3 ; # Bank 502 - PS_DDR_DQ12_502
LOC = K1 ; # Bank 502 - PS_DDR_DQ13_502
LOC = J1 ; # Bank 502 - PS_DDR_DQ14_502
LOC = K3 ; # Bank 502 - PS_DDR_DQ15_502
LOC = G4 ; # Bank 502 - PS_DDR_A14_502
LOC = F4 ; # Bank 502 - PS_DDR_A13_502
LOC = H4 ; # Bank 502 - PS_DDR_A12_502
LOC = G5 ; # Bank 502 - PS_DDR_A11_502
LOC = J3 ; # Bank 502 - PS_DDR_A10_502
LOC = H5 ; # Bank 502 - PS_DDR_A9_502
LOC = J5 ; # Bank 502 - PS_DDR_A8_502
LOC = J6 ; # Bank 502 - PS_DDR_A7_502
LOC = J7 ; # Bank 502 - PS_DDR_A6_502
LOC = K5 ; # Bank 502 - PS_DDR_A5_502
LOC = K6 ; # Bank 502 - PS_DDR_A4_502
LOC = L4 ; # Bank 502 - PS_DDR_A3_502
LOC = M7 ; # Bank 502 - PS_DDR_VRN_502
LOC = N7 ; # Bank 502 - PS_DDR_VRP_502
LOC = N4 ; # Bank 502 - PS_DDR_CKP_502
LOC = N5 ; # Bank 502 - PS_DDR_CKN_502
LOC = K4 ; # Bank 502 - PS_DDR_A2_502
LOC = M5 ; # Bank 502 - PS_DDR_A1_502
LOC = M4 ; # Bank 502 - PS_DDR_A0_502
LOC = M6 ; # Bank 502 - PS_DDR_BA2_502
LOC = L6 ; # Bank 502 - PS_DDR_BA1_502 = 1.5v
LOC = L7 ; # Bank 502 - PS_DDR_BA0_502
LOC = P5 ; # Bank 502 - PS_DDR_ODT_502
LOC = P6 ; # Bank 502 - PS_DDR_CS_B_502
LOC = V3 ; # Bank 502 - PS_DDR_CKE_502
LOC = R4 ; # Bank 502 - PS_DDR_WE_B_502
LOC = P3 ; # Bank 502 - PS_DDR_CAS_B_502
LOC = R5 ; # Bank 502 - PS_DDR_RAS_B_502
LOC = M1 ; # Bank 502 - PS_DDR_DQ16_502
LOC = T3 ; # Bank 502 - PS_DDR_DQ17_502
LOC = N3 ; # Bank 502 - PS_DDR_DQ18_502
LOC = T1 ; # Bank 502 - PS_DDR_DQ19_502
LOC = P1 ; # Bank 502 - PS_DDR_DM2_502
LOC = N2 ; # Bank 502 - PS_DDR_DQS_P2_502
LOC = P2 ; # Bank 502 - PS_DDR_DQS_N2_502
LOC = R3 ; # Bank 502 - PS_DDR_DQ20_502
LOC = T2 ; # Bank 502 - PS_DDR_DQ21_502
LOC = M2 ; # Bank 502 - PS_DDR_DQ22_502
LOC = R1 ; # Bank 502 - PS_DDR_DQ23_502
LOC = AA3 ; # Bank 502 - PS_DDR_DQ24_502
LOC = U1 ; # Bank 502 - PS_DDR_DQ25_502
LOC = AA1 ; # Bank 502 - PS_DDR_DQ26_502
LOC = U2 ; # Bank 502 - PS_DDR_DQ27_502
LOC = AA2 ; # Bank 502 - PS_DDR_DM3_502
LOC = V2 ; # Bank 502 - PS_DDR_DQS_P3_502
LOC = W2 ; # Bank 502 - PS_DDR_DQS_N3_502
LOC = W1 ; # Bank 502 - PS_DDR_DQ28_502
LOC = Y3 ; # Bank 502 - PS_DDR_DQ29_502
LOC = W3 ; # Bank 502 - PS_DDR_DQ30_502
LOC = Y1 ; # Bank 502 - PS_DDR_DQ31_502
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ZC702 Board UCF Listing
71