Device Configuration - Xilinx ZC702 User Manual

X-Ref Target - Figure 1-4
Zynq-7000 AP SoC
Processing System
I/O
Peripherals
Clock
Generation
USB
2x USB
USB
2x GigE
GigE
GigE 2x SD
SD
SDIO
IRQ
SD
SDIO
GPIO
UART
UART
CAN
CAN
I2C
I2C
SPI
SPI
Memory
Interfaces
SRAM/
NOR
ONFI 1.0
NAND
Q-SPI
CTRL
EMIO
XADC
12-Bit ADC
Notes:
1) Arrow direction shows control (master to slave)
2) Data flows in both directions:
For additional information on Zynq-7000 AP SoC devices, see DS190, Zynq-7000 All
Programmable SoC Overview, and UG585, Zynq-7000 All Programmable SoC Technical
Reference Manual for more information about Zynq-7000 AP SoC configuration options.

Device Configuration

Zynq-7000 XC7Z020 AP SoC uses a multi-stage boot process that supports both a
non-secure and a secure boot. The PS is the master of the boot and configuration process.
For a secure boot, the PL must be powered on to enable the use of the security block
located within the PL, which provides 256-bit AES and SHA decryption/authentication.
The ZC702 board supports these configuration options:
• PS Configuration: Quad SPI flash memory
• PS Configuration: Processor System Boot from SD Card (J64)
ZC702 Board User Guide
UG850 (v1.2) April 4, 2013
Reset
SWDT
TTC
System-
Level
Control
Regs
DMA 8
Channel
Central
Interconnect
General-Purpose DMA
Ports Sync
AXI 32-Bit/64-Bit, AXI 64-Bit, AXI 32-Bit,
Figure 1-4: Zynq-7000 AP SoC Block Diagram
www.xilinx.com
Application Processor Unit
FPU and NEON Engine
ARM Cortex-A9
MMU
CPU
32 KB 32 KB
I-Cache D-Cache
Snoop Controller, AWDT, Timer
GIC
512 KB L2 Cache and Controller
OCM 256K
Interconnect
SRAM
CoreSight
Components
DAP
Programmable Logic to
DevC
Memory Interconnect
Config
IRQ High-Performance Ports
AES/
Programmable Logic
SHA
AHB 32-Bit, APB 32-Bit, Custom
Feature Descriptions
FPU and NEON Engine
ARM Cortex-A9
MMU
CPU
32 KB 32 KB
I-Cache D-Cache
Memory
Interfaces
DDR2/3,
LPDDR2
Controller
ACP
SelectIO
Resources
UG850_c1_04_101712
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