Clock Distribution; Table 7-9 Pci Arbitration Assignments - SMART Embedded Computing MVME3100 Installation And Use Manual

The PCI6520 secondary PCI/X interface arbiters support external bus masters in addition
to the PCI6520. One secondary arbiter provides arbitration for the PMC sites on PCI bus
B, and the other provides arbitration for the PMCspan and USB host controller on PCI bus
C.
The arbitration assignments on the MVME3100 are shown in the follow table so that
software may set arbiter priority assignments if necessary.
Table 7-9
PCI Bus
A
A
A
A
B
B
B
B
C
C
7.13

Clock Distribution

The clock function generates and distributes all of the clocks required for system operation.
The clock tree is designed in such a manner as to maintain the strict edge-to-edge jitter and
low clock-to-clock skew required by the devices. Additional clocks required by individual
devices are generated near the devices using individual
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The clock tree A frequencies on bus A have a default configuration of 66MHz. The
33/66/100MHz clocks are dynamically configured at reset depending on the state of the
PCIXCAP and M66EN pins on bus B.
The PCI clock trees A, B, and C are not required to be synchronized with each other.
MVME3100 Single Board Computer Installation and Use (6806800M28H)
PCI Arbitration Assignments
Arbitration Assignment
MPC8540 PCI_REQ/GNT[0]
MPC8540 PCI_REQ/GNT[1]
MPC8540 PCI_REQ/GNT[2]
MPC8540 PCI_REQ/GNT[3]
PCI6520-1 S_REQ/GNT[0]
PCI6520-1 S_REQ/GNT[1]
PCI6520-1 S_REQ/GNT[2]
PCI6520-1 S_REQ/GNT[3]
PCI6520-2 S_REQ/GNT[0]
PCI6520-2 S_REQ/GNT[1]
lists the clocks required on the MVME3100 along with their frequency and source.
PCI Master(s)
SATA Controller
TSI148 VME Controller
PCI6520 (Bus A to Bus B bridge)
PCI6520 (Bus A to Bus C bridge)
PMC site 1 primary master
PMC site 1 secondary master
PMC site 2 primary master
PMC site 2 secondary master
USB Controller
PMCspan
oscillatorsClock Assignments on
Clock Distribution
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