6.2.16.3 Compare Registers - SMART Embedded Computing MVME3100 Installation And Use Manual

Memory Maps
External Timer Registers
COC
Clear counter on compare. When this bit is high, the counter is reset to 0 when it compares
with the compare register. When this bit is low, the counter is not reset.
COVF
Clear overflow bits. The overflow counter is cleared when a 1 is written to this bit.
OVF
Overflow bits. These bits are the output of the overflow counter. The overflow counter is
incremented each time the tick timer sends an interrupt to the local bus interrupter. The
overflow counter can be cleared by writing a 1 to the COVF bit.
ENINT
Enable interrupt. When this bit is high, the interrupt is enabled. When this bit is low, the
interrupt is not enabled.
CINT
Clear interrupt.
INTS
Interrupt status.
RSVD
Reserved for future implementation.

6.2.16.3 Compare Registers

The tick timer counter is compared to the Compare register. When they are equal, the tick
timer interrupt is asserted and the overflow counter is incremented. If the clear-on-compare
mode is enabled, the counter is also cleared. For periodic interrupts, this equation should
be used to calculate the compare register value for a specific period (T):
Compare register value = T (us)
118 MVME3100 Single Board Computer Installation and Use (6806800M28H)