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SMART Embedded Computing MVME7100ET Programmer's Reference Manual

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MVME7100ET Single Board Computer
Programmer's Reference
P/N: 6806800K88C
October 2019

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  • Page 1 MVME7100ET Single Board Computer Programmer’s Reference P/N: 6806800K88C October 2019...
  • Page 2 Computing” and the SMART Embedded Computing logo are trademarks of SMART Modular Technologies, Inc. All other names and logos referred to are trade names, trademarks, or registered trademarks of their respective owners. These materials are provided by SMART Embedded Computing as a service to its customers and may be used for informational purposes only. Disclaimer* SMART Embedded Computing (SMART EC) assumes no responsibility for errors or omissions in these materials.

  • Page 3: Table Of Contents

    3.1.16 Watch Dog Timer Load Register ........41 MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 4 A.1 Overview ............. . . 63 MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 5 Related Documentation ............83 B.1 SMART Embedded Computing Documentation ....... . . 83 B.2 Manufacturers’...
  • Page 6 Table of Contents MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 7 Boot Flash Bank ..........33 MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 8 Table of Contents MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 9 PHY Types and MII Management Bus Addresses ......57 MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 10 Related Specifications ..........85 MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)

  • Page 11: About This Manual

    This manual is divided into the following chapters and appendices: Chapter 1, Introduction on page 15, provides a brief product description and a block diagram showing the architecture of the MVME7100ET Single Board Computer. Chapter 2, Memory Maps on page 21, provides information on the memory maps of the board.
  • Page 12 Ranges, for example: 0..4 means one of the integers 0,1,2,3, and 4 (used in registers) Logical OR Indicates a hazardous situation which, if not avoided, could result in death or serious injury MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 13 This manual has been revised and replaces all prior editions. Part Number Publication Date Description 6806800K88C October 2019 Rebrand to SMART Embedded Computing template 6806800K88B June 2014 Re-branded to Artesyn template. 6806800K88A September 2010 First Release MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 14 About this Manual About this Manual MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)

  • Page 15: Introduction

    For technical assistance, documentation, or to report product damage or shortages, contact your local SMART EC sales representative or visit our web site at https://www.smartembedded.com/ec/support/. NOTE: The IPMC712 and IPMC761 I/O modules are not supported on the MVME7100ET SBC. MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)

  • Page 16: Features

    128 MB soldered flash with two alternate 1 MB boot sectors selectable via hardware switch H/W switch or S/W bit write protection for entire logical bank NAND Flash Up to two devices available: 4 GB - 1 device 8 GB - 2 device MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 17 VME64 Extensions (ANSI/VITA 1.1-1997) compliant (5 row backplane 160-pin VME connector) 2eSST (ANSI/VITA 1.5-2003) compliant Two five-row P1 and P2 backplane connectors One Tsi148 VMEbus controller Form Factor Standard 6U VME, one slot MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 18 Board fail User S/W controlled LED Planar status indicators One standard 16-pin JTAG/COP header Boundary scan support Switches for VME geographical addressing in a three-row backplane Software Support VxWorks OS support Linux OS support MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)

  • Page 19: Block Diagram

    Introduction Block Diagram The following figure is a block diagram of the MVME7100ET architecture. Figure 1-1 Block Diagram MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)

  • Page 20: Functional Description

    SDRAM, quad 10/100/1000 Ethernet, and five serial ports. The MVME7100ET supports front and rear I/O with access to the rear I/O via the MVME7100ET transition module. The MVME7100ET provides front panel access to one serial port with a mini DB-9 connector and two 10/100/1000 Ethernet ports with two RJ-45 connectors.

  • Page 21: Memory Maps

    Chapter 2 Memory Maps Overview The following sections describe the memory maps for the MVME7100ET. Refer to the MC864xD Reference Manual for additional details and/or programming information. 2.1.1 Default Processor Memory Map The following table describes a default memory map from the point of view of the processor after a processor reset.

  • Page 22: Pci Memory Map

    Table 2-3 PCI Memory Map PCI Address Size Definition Notes Start System Memory 0x00000000 top_dram - 1 dram_size (on-board DRAM) 0x80000000 0xCFFFFFFF 0x50000000 PCI 0 Memory Space MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)

  • Page 23: Vme Memory Map

    PCI 1 I/O Space 1. CHRP-based addressing 2.1.4 VME Memory Map The MVME7100ET is fully capable of supporting both the PReP and the CHRP VME Memory Map examples with RAM size limited to 2GB. MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 24 Memory Maps Memory Maps MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)

  • Page 25: Register Descriptions

    System resources including system control and status registers, external timers, and the QUART are mapped into a 16 MB address range accessible from the MVME7100ET local bus via the MC864xD LBC. The memory map is defined in the following table including the LBC bank chip select used to decode the register.

  • Page 26: Table 3-23 Test Register 1

    COM 2 (QUART channel 1) F201 1FFF F201 2000 - COM 3 (QUART channel 2) F201 2FFF F201 3000 - COM 4 (QUART channel 3) F201 3FFF F201 4000 - COM 5 (QUART channel 4) F201 4FFF MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 27 External PLD Tick Timer 4 Counter Register F202 004C - Reserved F2FF FFFF F203 0000 NAND Chip 1 Data Register F203 0001 - Reserved F203 0FFF F203 1000 NAND Chip 2 Data Register F203 1001 - Reserved F203 FFFF MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)

  • Page 28: System Status Register

    2. 32-bit write only. 3. Byte read/write capable. 3.1.1 System Status Register The MVME7100ET has a System Status Register that is a read only register used to provide general board status information. Table 3-2 System Status Register System Status Register - 0xF200 0000...
  • Page 29 SW8. This bit reflects the current state of SW8. A cleared condition indicates the switch is off. A set condition indicates the switch is on. MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)

  • Page 30: System Control Register

    Register Descriptions Register Descriptions 3.1.2 System Control Register The MVME7100ET has a System Control Register that provides general board control bits. Table 3-3 System Control Register System Control Register - 0xF200 0001 EEPROM_ Field BRD_RST RSVD RSVD RSVD RSVD OPER...

  • Page 31: Status Indicator Register

    3.1.3 Status Indicator Register The MVME7100ET provides a Status Indicator Register that may be read by the system software to determine the state of the on-board status indicator LEDs or written to by system software to illuminate the corresponding on-board LEDs.

  • Page 32: Nor Flash Control/Status Register

    MAP_SEL Memory Map Select. When this bit is cleared, the flash memory map is controlled by the Flash Boot Block Select switch (see the MVME7100ET Installation and Use manual for switch settings). When the Map Select bit is set, boot block A is selected and mapped to the highest address (see Figure 3-1).

  • Page 33: Interrupt Register 1

    Figure 3-1 Boot Flash Bank 3.1.5 Interrupt Register 1 The MVME7100ET provides an Interrupt Register that may be read by the system software to determine which of the Ethernet PHYs originated their combined (OR'd) interrupt. Table 3-6 Interrupt Register 1...

  • Page 34: Interrupt Register 2

    3.1.6 Interrupt Register 2 The RTC, TEMP sensor and Abort switch interrupts are OR'd together. The MVME7100ET provides an Interrupt Register that may be read by the system software to determine which device originated the interrupt. This register also includes bits that allow the interrupt sources to be masked.

  • Page 35: Presence Detect Register

    Register Descriptions 3.1.7 Presence Detect Register The MVME7100ET provides a Presence Detect Register that may be read by the system software to determine the presence of optional devices. Table 3-8 Presence Detect Register Presence Detect Register - 0xF200 0006 Field...

  • Page 36: Nand Flash Chip 1 Control Register

    Register Descriptions Register Descriptions 3.1.8 NAND Flash Chip 1 Control Register The MVME7100ET provides a Control Register for the NAND Flash device. Table 3-9 NAND Flash Chip 1 Control Register NAND Flash Chip 1 Control Register - 0xF200 0010 Field...

  • Page 37: Nand Flash Chip 1 Presence Register

    RSVD Reserved for future implementation. 3.1.10 NAND Flash Chip 1 Presence Register The MVME7100ET provides a Presence Register for the NAND Flash device. Table 3-11 NAND Flash Chip 1 Presence Register NAND Flash Chip 1 Presence Register - 0xF200 0014...

  • Page 38: Nand Flash Chip 1 Status Register

    Register Descriptions Register Descriptions 3.1.11 NAND Flash Chip 1 Status Register The MVME7100ET provides a Status Register for the NAND Flash device. Table 3-12 NAND Flash Chip 1 Status Register NAND Flash Chip 1 Presence Register - 0xF200 00145 Field...

  • Page 39: Nand Flash Chip 2 Select Register

    RSVD Reserved for future implementation. 3.1.13 NAND Flash Chip 2 Select Register The MVME7100ET provides a Select Register for the NAND Flash device. Table 3-14 NAND Flash Chip 2 Select Register NAND Flash Chip 2 Select Register - 0xF200 0019...

  • Page 40: Nand Flash Chip 2 Presence Register

    Register Descriptions Register Descriptions 3.1.14 NAND Flash Chip 2 Presence Register The MVME7100ET provides a Presence Register for the NAND Flash device. Table 3-15 NAND Flash Chip 2 Presence Register NAND Flash Chip 2 Presence Register - 0xF200 001C Field...

  • Page 41: 3.1.16 Watch Dog Timer Load Register

    System Reset. If cleared a board-level reset is generated when a time- out occurs. If set, a VMEbus SYSRST is generated when a time-out occurs. If MVME7100ET is SYSCON, then a local reset will also result in a VMEbus SYSRST.

  • Page 42: 3.1.18 Watch Dog Timer Resolution Register

    Register Descriptions Register Descriptions 3.1.18 Watch Dog Timer Resolution Register The MVME7100ET provides a watch dog timer resolution register. Table 3-19 Watch Dog Timer count Register Watch Dog Timer Resolution Register - 0xF200 0025 Field RSVD RSVD RSVD RSVD OPER RESET Resolution.

  • Page 43: 3.1.19 Watch Dog Timer Count Register

    If the counter reaches zero a system or board- level reset will be generated. 3.1.20 PLD Revision Register The MVME7100ET provides a PLD revision register that can be read by the system software to determine the current revision of the timers/registers PLD. Table 3-21 PLD Revision Register...

  • Page 44: Pld Date Code Register

    Register Descriptions Register Descriptions 3.1.21 PLD Date Code Register The MVME7100ET PLD provides a 32-bit register which contains the build date code of the inters/registers PLD. Table 3-22 PLD Date Code Register Test Register 1 - 0xF200 0034 31:24 23:16...

  • Page 45: Test Register 2

    3.1.24 External Timer Registers The MVME7100ET provides a set of tick timer registers for access to the four external timers implemented in the timers/registers PLD. Note that these registers are 32-bit registers and are not byte writable. The following sections describe the external timer prescaler and control registers.

  • Page 46: 3.1.24.2 Control Registers

    ENINT Enable Interrupt. When the bit is set the interrupt is enabled. When the bit is cleared the interrupt is not enabled. CINT Clear Interrupt. INTS Interrupt Status. RSVD Reserved for future implementation. MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)

  • Page 47: 3.1.24.3 Compare Register

    Tick Timer 2 Counter Register - 0xF202 0028 (32 bits) Tick Timer 3 Counter Register - 0xF202 0038 (32 bits) Tick Timer 4 Counter Register - 0xF202 0048 (32 bits) … Field Tick Timer Counter Value OPER RESET MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)

  • Page 48: Geographical Address Register

    MVME7100ET. This register reflects the inverted states of the geographical address pins at the 5-row, 160-pin P1 connector. Applications not using the 5-row backplane can use the planar switch described in the MVME7100ET Installation and Use manual to assign a geographical address.

  • Page 49: Programming Details

    This chapter includes additional programming information for the MVME7100ET. MC864xD Reset Configuration The MVME7100ET supports the power-on reset (POR) pin sampling method for processor reset configuration. The states of the various configuration pins on the processor are sampled when reset is deasserted to determine the desired operating modes.
  • Page 50 Local Bus GPCM - 16 Local Bus GPCM -32 -bit 1111 PCI-E 1 outbound ATMU 1 (no option Alternate Boot window 1 is enabled pulldown) TSEC1_TXD[0] Resistor Vector Location Boot vector fetched from default boot ROM location MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 51 SerDes2: x4 Serial RapidIO SerDes1: disabled 1011 SerDes2: x4 Serial RapidIO SerDes1: disabled 1110 SerDes2: x1/x2/x4/x8 PCIE SerDes1: x1/x2/x4/x8 PCI- E, 100 MHz ref clk 1111 SerDes2: x1/x2/x4/x8 PCI- E, 100 MHz ref clk MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 52 TSEC2_TXD[4] DDR SDRAM No Connects Type TSEC2_TX_ER (default) DDR2 Ethernet interface operates in reduced mode, RTBI or RGMII. eTSEC Width TSECn_TXD5 Resistors Configuration (pulldowns) Ethernet interface operates in standard TBI or GMII modes. MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 53 DDR debug information is driven on the ECC pins instead of the normal ECC DDR Debug D1_MSRCID[1] No Connect (processor I/O. Configuration default) DDR debug information is not driven on the ECC pins. MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)

  • Page 54: Mc864Xd Interrupt Controller

    Programming Details Programming Details MC864xD Interrupt Controller The MVME7100ET uses the MC864xD integrated programmable interrupt controller (PIC) to manage locally generated interrupts. Currently defined external interrupting devices and interrupt assignments, along with corresponding edge/levels and polarities, are shown in the following table.

  • Page 55: Local Bus Controller Chip Select Assignments

    C controller is used by the system software to read the contents of the various I C devices located on the MVME7100ET. The following table contains the I C devices used for the MVME7100ET and their assigned device addresses. Table 4-4 I2C Bus Device Addressing Device Address...

  • Page 56: User Configuration Eeprom

    Documentation, for additional details. VPD EEPRO The MVME7100ET board provides an 8KB dual address serial EEPROM containing Vital Product Data (VPD) configuration information specific to the MVME7100ET. Typical information that may be present in the EEPROM may include: manufacturer, board revision, build version, date of assembly, memory present, options present, L2 cache information, and so on.

  • Page 57: Rtm Vpd Eeprom

    Programming Details RTM VPD EEPROM The MVME7100ET RTM provides an 8 KB dual address serial EEPROM containing VPD configuration information specific to the MVME7100ET RTM. Typical information that may be present in the EEPROM may include: manufacturer, board revision, build version, date of assembly, options present, and so on.

  • Page 58: Pci/Pci-X Configuration

    Programming Details Programming Details A hardware Flash Bank write-protect switch is provided on the MVME7100ET to enable write protection of the NOR flash. Regardless of the state of the software flash write-protect bit in the NOR Flash Control/Status register, write protection is enabled when this switch is ON.

  • Page 59: Pci Arbitration Assignments

    0x10B5 0x8112 PCI-E-to-PCI-X Bridge PEX8114 0x10B5 0x8114 VME Controller TSi148 0x10E3 0x0148 4.11.2 PCI Arbitration Assignments The integrated PCI/X arbiters internal to the PEX8112 and the PEX8114 provide PCI arbitration for the MVME7100ET. MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)

  • Page 60: Other Software Considerations

    Programming Details Programming Details The arbitration assignments on the MVME7100ET are shown in the table below so that software may set arbiter priority assignments if necessary. Table 4-10 PCI Arbitration Assignments PCI Bus Arbitration Assignment PCI Master(s) PEX8114 REQ/GNT[0] PMC site 1 primary master...

  • Page 61: Clock Distribution

    X bus clocks are generated by the bridge chips from the PCI-E clock. Additional clocks required by individual devices are generated near the devices using individual oscillators. The following table lists the clocks required on the MVME7100ET along with their frequency and source.

  • Page 62: System Clock

    This provides a fixed clock reference for the MC864xD PIC timers, which software can use as a known timing reference. 4.13.3 Local Bus Controller Clock Divisor The Local Bus Controller (LBC) clock output is connected to the PLD but is not used by the internal logic. MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)

  • Page 63: Programmable Configuration Data

    Programmable Configuration Data Overview This appendix provides data and specifications pertaining to programmable parts used on the MVME7100ET. The board is shipped after the programmable parts have been programmed through ATE or boundary scan according to the In-Circuit Test specifications. Table A-1...

  • Page 64: Vital Product Data (Vpd) Introduction

    The firmware ignores the VPD contents and attempts to acquire information from other sources.  Some device drivers will not work.  Some diagnostic tests will fail.  The board will run much slower than usual. MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)

  • Page 65: How To Fix Corrupted Vpd Information

    If you suspect that your board has problems, as a result of wrong VPD information, select SAFE mode by setting S1:1 ON and reboot the MVME7100ET. At this point, the firmware will ignore all EEPROM contents. Use the vpdEdit command to change the VPD to the correct parameters.
  • Page 66 = (crcValue >> 31) & 1; crcValue <<= 1; if (msbDataBitValue ^ (dataByte & 1)) crcValue ^= 0x04c11db6; crcValue |= 1; dataByte >>= 1; crcValueFlipped = 0; for (index = 0; index < 32; index++) MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)

  • Page 67: Serial Presence Detect Checksum Calculation

    1111 1110 > + 254 02 (0x02) 0000 0000 > 03 (0x03) 0000 0000 > > > 60 (0x3C) 0000 0000 > 61 (0x3D) 0000 0000 > 62 (0x3E) 0000 0000 > Decimal Total MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)

  • Page 68: A.10 Vpd Contents For Mvme7100Et Boards

    Size of VPD area in bytes. The size is viewed as BINARY logical; it is not the size of the EEPROM. 512 bytes in this VPD architecture BINARY VPD Revision Packet BINARY # of Bytes BINARY Board Type: Processor Board BINARY Architecture Revision MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 69 Data (HEX) Description (HEX) Type BINARY Board Build Revision BINARY Revision Reason Flags Product Identifier Packet. BINARY Refer to Notes 1 and 2. BINARY # of bytes Product Identifier. ASCII Table A-5 Refer to MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 70 Factory Assembly Number. ASCII Table A-5 Table A-6 Refer to **Serial number to be filled in. BINARY Refer to Notes BINARY # of bytes Most significant serial number character ASCII Least significant serial number character MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 71 BINARY Six bytes containing the lowest Ethernet address. BINARY Ethernet Controller 0 BINARY Ethernet MAC Address Packet BINARY # of bytes BINARY Six bytes containing the next Ethernet address. BINARY Ethernet Controller 1 MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 72 Ethernet MAC Address Packet BINARY # of bytes BINARY Six bytes containing the highest Ethernet address. BINARY Ethernet Controller 3 BINARY Processor Identifier Packet BINARY # of bytes Processor type ASCII Table A-5 Refer to MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 73 Minimum write/erase data width in bits BINARY Flash bank number BINARY Flash access speed in nanoseconds: 0x6E = 110 ns BINARY Total bank size [(1<<n)*256K bytes]: 0x09 = 128 MB BINARY Bank 2 Flash Memory Configuration Packet MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 74 2. The method used to program the Product Identifier, Factory Assembly Number, and Serial Number packets requires that these packets be located in absolute fixed locations. For this reason, these packets shall have fixed sizes and shall immediately follow the header. MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 75 Table A-5 at address 0x32 represents the assembly revision letter (A=41, B=42, and so on). Table A-5 Variable VPD Contents Offset MVME7100ET- MVME7100ET- MVME7100ET- MVME7100ET- (Hex) 0106839D11* 0106839D12* 0106839D13* 0106839D14* Product Identifier (ASCII) MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 76 Programmable Configuration Data Programmable Configuration Data Table A-5 Variable VPD Contents (continued) Offset MVME7100ET- MVME7100ET- MVME7100ET- MVME7100ET- (Hex) 0106839D11* 0106839D12* 0106839D13* 0106839D14* Factory Assembly Number (ASCII) Processor Type NAND Flash Size MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)

  • Page 77: A.11 Spd Contents For Mvme7100Et Boards

    Primary SDRAM Width: 0x08 = 8 bits 14 (0x0E) Error Checking SDRAM Width: 0x08 = 8 bits 15 (0x0F) Reserved SDRAM Device Attributes - Burst Lengths Supported: 0x0C = 4, and 8 16 (0x10) burst lengths MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 78 Address and Command Setup Time Before Clock (t lS): 0x20 = 0.20ns. 32 (0x20) Refer to Note Address and Command Hold Time After Clock (t lH): 0x28 = 0.28ns. 33 (0x21) Refer to Note MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 79 0x03 = Double refresh mode bit and High temperature self-refresh 50 (0x32) Not Used 51 (0x33) Not Used 52 (0x34) Not Used 53 (0x35) Not Used 54 (0x36) Not Used 55 (0x37) Not Used 56 (0x38) Not Used 57 (0x39) Not Used MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 80 69 (0x45) 70 (0x46) 71 (0x47) Module Manufacturing location. 72 (0x48) Refer to Note Module Part Number. 73 (0x49) Refer to Note 74 (0x4A) 75 (0x4B) 76 (0x4C) 77 (0x4D) 78 (0x4E) 79 (0x4F) MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 81 Module Manufacturing Date. 93 (0x5D) Refer to Note 94 (0x5E) Module Serial Number. 95 (0x5F) Refer to Note 96 (0x60) 97 (0x61) 98 (0x62) Manufacturer's Specific Data. 99 (0x63) Refer to Note 127 (0x7F) MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 82 1. This will typically be programmed as 128 bytes. 2. This will typically be programmed as 256 bytes. 3. From datasheet. 4. High order bit is self refresh “flag”. If set to “1”, the assembly supports self refresh. 5. Reserved. MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)

  • Page 83: Related Documentation

    SMART EC Documentation Document Title Publication Number MVME7100 Data Sheet MVME7100-DS MVME7100ET Single Board Computer Installation and Use 6806800K87 MOTLoad Firmware Package User’s Manual 6806800C24 Manufacturers’ Documents For additional information, refer to the following table for manufacturers’ data sheets or user’s manuals.
  • Page 84 MAX811/MAX812 19-0411 4-Pin µP Voltage Monitors Rev 3 3/99 With Manual Reset Input On Semi device ADT7461 ADT7461/D, Rev 4, January 2009 FN 80A3020_ Tsi148-133ILY PCI/X-to-VME Bus Bridge User Manual MA001_13 Broadcom Corporation MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)

  • Page 85: Related Specifications

    2eSST Source Synchronous ANSI/VITA 1.5-2003 Transfer Processor PMC ANSI/VITA32-2003 PCI-X for PMC and Processor PMC ANSI/VITA39-2003 VITA 36 PMC I/O Module (PIM) Draft Draft Rev 0.1 Standard July 19, 1999 Connector Current Capacity ANSI/VITA 1.7-2003 MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 86 Institute for Electrical and Electronics Engineers, Inc. Draft Standard for a Common P1386 - 2001 Mezzanine Card Family: CMC Draft Standard Physical and Environmental Layer for PCI P1386 - 2001 Mezzanine Cards: PMC MVME7100ET Single Board Computer Programmer’s Reference (6806800K88C)
  • Page 88 © 2019 SMART Embedded Computing™, Inc. All Rights Reserved. The stylized “S” and “SMART” is a registered trademark of SMART Modular Technologies, Inc. and “SMART Embedded Computing” and the SMART Embedded Computing logo are trademarks of SMART Modular Technologies, Inc. All other names and logos...

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