Memory Maps; Introduction; Default Processor Memory Map; Table 6-1 Default Processor Address Map - SMART Embedded Computing MVME3100 Installation And Use Manual

Memory Maps

6.1

Introduction

This chapter provides information on memory maps and system and configuration registers
6.2 Memory Maps
Memory Maps is explained in two different types:
The mapping of all resources as viewed by local bus masters (local bus memory

map)
The mapping of on-board resources as viewed by VMEbus Masters (VMEbus

memory map)
6.2.1

Default Processor Memory Map

The MPC8540 presents a default processor memory map following RESET negation. The
following table shows the default memory map from the point of view of the processor. The
e500 core only provides one default TLB entry to access boot code and it allows for
accesses within the highest 4KB of memory. To access the full 8MB of default boot space
(and the 1MB of CCSR space), additional TLB entries must be set up within the e500 core
for mapping these regions. Refer to the MPC8540 Reference Manual listed in
Related Documentation
This is the default location for the CCSRs, but it is not mapped after reset.
Table 6-1
Processor Address
Start
0000 0000
FF70 0000
FF80 0000
Only FFFF F000 to FFFF FFFF is mapped after reset. The e500 core fetches the first
instruction from FFFF FFFC following a reset.
MVME3100 Single Board Computer Installation and Use (6806800M28H)
for details.
Default Processor Address Map
End
FF6F FFFF
FF7F FFFF
FFFF FFFF
Size Definition
4087M Not mapped
1M MPC8540 CCS Registers
8M Flash
Chapter 6
Appendix B,
Notes
1
2
101