System I/O Memory Map; Table 6-3 System I/O Memory Map - SMART Embedded Computing MVME3100 Installation And Use Manual

6.2.4

System I/O Memory Map

System resources including System Control and Status registers, external timers, and the
QUART are mapped into a 16MB address range from the MVME3100 via the MPC8540
local bus controller (LBC). The memory map is defined in the following table, including the
LBC bank chip select used to decode the register:
Table 6-3
Address
E200 0000
E200 0001
E200 0002
E200 0003
E200 0004
E200 0005
E200 0006
E200 0007
E200 0008
E200 0009
E200 000C
E200 0010
E200 0014
E200 0018 -
E200 0FFF
E201 1000 -
E201 1FFF
E201 2000 -
E201 2FFF
E201 3000 -
E201 3FFF
MVME3100 Single Board Computer Installation and Use (6806800M28H)
System I/O Memory Map
Definition
System Status Register
System Control Register
Status Indicator Register
Flash Control/Status Register
PCI Bus A Status Register
PCI Bus B Status Register
PCI Bus C Status Register
Interrupt Detect Register
Presence Detect Register
PLD Revision
PLD Date Code (32 bits)
Test Register 1 (32 bits)
Test Register 2 (32 bits)
Reserved
COM 2 (QUART channel 1)
COM 3 (QUART channel 2)
COM 4 (QUART channel 3)
System I/O Memory Map
LBC Bank /
Chip Select
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
Notes
3
3
3
3
3
3
3
3
3
3
3
3
1
3
1
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