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Table 7-1
MPC8540
Signal
MSRCID0
MSRCID1
NOTES:
1. The selected configuration settings are indicated by dark cell outlines.
2.
External arbitration is required.
3.
e500 core does not boot until configured by an external master.
4.
Dependent on PCI/PCI-X mode configuration.
5.
Required to meet 2 ns hold time requirement.
6.
Meets 0.7 ns hold time requirement.
7.
Local bus LAD[0:31] is sampled during POR, but only LAD[28:31] are configurable by resistor
option. Software can use this value to inform the firmware or operating system about initial board
configuration.
8.
ECC signals from memory devices must be disconnected.
MVME3100 Single Board Computer Installation and Use (6806800M28H)
MPC8540 Power-on Reset Configuration Settings (continued)
Select
Default
Option
Setting
Resistor
1
Resistor
1
MPC8540 Reset Configuration
Description
State of Bit vs Function
0
Memory Debug
Configuration
1
0
DDR Debug
Configuration
1
1
Debug info from the
LBC is driven on
MSRCID & MDVAL
pins
Debug info from the
DDR SDRAM
controller is driven on
MSRCID & MDVAL
pins
Debug info on ECC
pins instead of normal
8
ECC
ECC pins function in
normal mode
127
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