Interrupt Detect Register; Table 6-11 Interrupt Detect Register - SMART Embedded Computing MVME3100 Installation And Use Manual

Interrupt Detect Register

6.2.10 Interrupt Detect Register
The MVME3100 provides an Interrupt Detect register that may be read by the system
software to determine which of the Ethernet PHYs originated their combined (OR'd)
interrupt.
Table 6-11
REG
BIT
FIELD
OPER
RESET
TSEC1_PHY
TSEC1 PHY interrupt. If cleared, the TSEC1 interrupt is not asserted. If set, the TSEC1
interrupt is asserted.
TSEC2_PHY
TSEC2 PHY interrupt. If cleared, the TSEC2 interrupt is not asserted. If set, the TSEC2
interrupt is asserted.
FEC_PHY
FEC PHY interrupt. If cleared, the FEC interrupt is not asserted. If set, the FEC interrupt is
asserted.
RSVD
Reserved for future implementation.
112
Interrupt Detect Register
Interrupt Detect Register - 0xE2000007
7 6 5
R R R
1 1 1
MVME3100 Single Board Computer Installation and Use (6806800M28H)
4 3 2
R R R
0 0 0
Memory Maps
1 0
R R
0 0