Table of Contents
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Register Descriptions
3.1
Overview
System resources including system control and status registers, external timers, and the
QUART are mapped into a 16 MB address range accessible from the MVME7100ET local
bus via the MC864xD LBC. The memory map is defined in the following table including the
LBC bank chip select used to decode the register.
Table 3-1
Address
F200 0000
F200 0001
F200 0002
F200 0003
F200 0004
F200 0005
F200 0006
F200 0010
F200 0011
F200 0012
F200 0013
F200 0014
F200 0015
F200 0016
F200 0017
F200 0018
F200 0019
F200 001A
F200 001B
F200 001C
MVME7100ET Single Board Computer Programmer's Reference (6806800K88C)
System I/O Memory Map
Definition
System Status Register
System Control Register
Status Indicator Register
NOR Flash Control/Status Register
Interrupt Register 1
Interrupt Register 2
Presence Detect Register
NAND Flash Chip 1 Control Register
NAND Flash Chip 1 Select Register
Reserved
Reserved
NAND Flash Chip 1 Presence Register
NAND Flash Chip 1 Status Register
Reserved
Reserved
NAND Flash Chip 2 Control Register
NAND Flash Chip 2 Select Register
Reserved
Reserved
NAND Flash Chip 2 Presence Register
Chapter 3
LBC Bank/Chip
Notes
Select
4
3
4
3
4
3
4
3
4
3
4
3
4
3
4
3
4
3
4
1
4
1
4
3
4
3
4
1
4
1
4
3
4
3
4
1
4
1
4
3
25
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