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Register and Bit #Defines File
#define SCON_RDIS_P 2 // Reset Disable
#define SCON_RST_P 0 // Soft Chip Reset
// Bit Masks
#define SCON_PCIRST
#define SCON_VAUX
#define SCON_PCI_5V
#define SCON_BUS1
#define SCON_BUS0
#define SCON_CRST1
#define SCON_CRST0
#define SCON_REGD
// Control Disable
#define SCON_VXPD MK_BMSK_(SCON_VXPD_P) // Vaux Policy for AC'97
// Pad Drivers
#define SCON_VXPW
// Pad Well Bias
#define SCON_ACVX
// Vaux Powered
#define SCON_XON
#define SCON_RDIS
#define SCON_RST
//**************************************************
//
PWRPx register
//**************************************************
// Bit Positions
#define PWRP_AINT_P 13
#define PWRP_PMINT_P 12 // Power Management Interrupt Pending
#define PWRP_GIEN_P 10
#define PWRP_GWE_P 6 // DSP Wake up on GPIO Input Enable
#define PWRP_PMWE_P 4
#define PWRP_RSTD_P 2 // DSP Soft Reset
#define PWRP_PU_P 1 // DSP Power Up
#define PWRP_PD_P 0 // DSP Power Down
// Bit Masks
#define PWRP_AINT
// from AC'97 Input
#define PWRP_PMINT
// Interrupt Pending
#define PWRP_GIEN
// for GPIO Input
B-98
ADSP-219x/2192 DSP Hardware Reference
MK_BMSK_(SCON_PCIRST_P) // PCI Reset
MK_BMSK_(SCON_VAUX_P ) // Vaux Present
MK_BMSK_(SCON_PCI_5V_P) // PCI 5V level
MK_BMSK_(SCON_BUS1_P ) // Bus Mode
MK_BMSK_(SCON_BUS0_P ) // Bus Mode
MK_BMSK_(SCON_CRST1_P ) // Chip Reset Source
MK_BMSK_(SCON_CRST0_P ) // Chip Reset Source
MK_BMSK_(SCON_REGD_P ) // 2.5V Regulator
MK_BMSK_(SCON_VXPW_P) // Vaux Policy for AC'97
MK_BMSK_(SCON_ACVX_P) // AC'97 External Devices
MK_BMSK_(SCON_XON_P) // XTAL Force On
MK_BMSK_(SCON_RDIS_P) // Reset Disable
MK_BMSK_(SCON_RST_P) // Soft Chip Reset
// DSP Interrupt Pending from AC'97 Input
// DSP Interrupt Enable for GPIO Input
// Power Management Wake up Enable
MK_BMSK_(PWRP_AINT_P)
MK_BMSK_(PWRP_PMINT_P)
MK_BMSK_(PWRP_GIEN_P)
// DSP Interrupt Pending
// Power Management
// DSP Interrupt Enable
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