Analog Devices ADSP-219 Series Hardware Reference Manual page 54

ADSP-2192 Peripheral Device Control Registers
Table B-24. PCI_CFGCTL Register Bit Descriptions (Continued)
Bit Bit name
position
9 Reserved
10 Reserved
11 GPIO IEN
12 AC'97 IEN
13 MAbort IEN
14 TAbort IEN
15 Reserved
PCI Configuration Register Space
The ADSP-2192 PCI Interface requires separate configuration space for
each function due to operating system requirements. This section
describes the registers in each function, their reset conditions, and interac-
tion between the functions to access and control the ADSP-2192
hardware.
Commonalities Between the Three Functions
Each function contains a complete set of registers in the predefined header
region, as defined in PCI Local Bus Specification, Revision 2.2. In addi-
tion, each function contains optional registers to support PCI Bus Power
Management. Registers that are unimplemented or read-only in one func-
tion are similarly defined in the other functions.
B-54 ADSP-219x/2192 DSP Hardware Reference
Description
Reserved
General Purpose I/O Pin Initiated Interrupt Enabled.
AC'97 Interface Initiated Interrupt Enabled.
PCI Interface Master Abort Detect Interrupt Enabled.
PCI Interface Target Abort Detect Interrupt Enabled.