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ADSP-2192 Peripheral Device Control Registers
Table B-4. SYSCON Register Bit Descriptions (Continued)
Bit Position
Bit Name
4
ACVX
5
Reserved
6
Reserved
7
REGD
9:8
CRST<1:0>
B-16
ADSP-219x/2192 DSP Hardware Reference
Description
AC'97 External Devices Vaux Powered.
Controls the AC'97 interface during D3cold (RST asserted).
0 = Disable the interface (drive 0, disable all inputs). This is
used if external AC'97 devices are NOT powered
during d3cold, and protects the ADSP-2192 from
floating inputs and from outputs driving input clamps
on an external device. (default)
1 = Interface enabled during RST.
Note: This bit resets to zero.
Reserved
Reserved
2.5V Regulator Control Disable.
Disables the on-chip 2.5V Regulator controller when the
2.5V (IVDD) supply is derived from an external regulator (e.g.
in USB and Mini-PCI applications).
0 = On-Chip 2.5V Regulator Control Enabled. (default)
1 = On-Chip 2.5V Regulator Control Disabled.
Note: This bit resets to zero.
Chip Reset Source.
Indicates the source of the last reset to the chip (Read-Only)
00 = Power-On Reset
01 = Reserved.
10 = PCI/ISA/CBUS/USB bus interface hard reset
11 = Soft Reset from the CMSR:RST bit
Note: the fifth possible reset source, DIP Soft Reset, is
indicated by DIP1/2:RD = 1. Each DSP must check its
DIP<n>:RD bit and clear it to zero upon reset.
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