Advertisement
Register and Bit #Defines File
// Bit Masks
#define PWRC_SPME MK_BMSK_(PWRC_SPME_P) // DSP PLL N Divisor Selects
#define PWRC_GPME MK_BMSK_(PWRC_GPME_P) // DSP PLL N Divisor Selects
#define PWRC_PWRST1 MK_BMSK_(PWRC_PWRST1_P) // DSP PLL K Divisor Selects
#define PWRC_PWRST0 MK_BMSK_(PWRC_PWRST0_P) // DSP PLL K Divisor Selects
//----------------------------------------------------------------------
//
//----------------------------------------------------------------------
#define DMAPAGE
#define STCTL0
#define SRCTL0
#define TX0
#define RX0
#define STCTL1
#define SRCTL1
#define TX1
#define RX1
#define TPERIOD
#define TCOUNT
#define TSCALE
#define TSCALECNT
#define FLAGS
#define MASTADDR
#define MASTNXTADDR 0x45
#define MASTCNT
#define MASTCURCNT
#define TX0ADDR
#define TX0NXTADDR
#define TX0CNT
#define TX0CURCNT
#define RX0ADDR
#define RX0NXTADDR
#define RX0CNT
#define RX0CURCNT
B-100
ADSP-219x/2192 DSP Hardware Reference
System Register address definitions
0x0C
// DMA Page Register
0x10
// FIFO0 Transmit Control Register
0x11
// FIFO0 Receive Control Register
0x12
// FIFO0 Transmit Data (TX) register
0x13
// FIFO0 Receive Data (RX) register
0x20
// FIFO1 Transmit Control Register
0x21
// FIFO1 Receive Control Register
0x22
// FIFO1 Transmit Data (TX) register
0x23
// FIFO1 Receive Data (RX) register
0x30
// Timer Period Register
0x31
// Timer Counter Register
0x32
// Timer Scaling Register
0x33
// Timer Scale Count Register
0x34
// Flags Register
0x44
// DMA Address,
// DMA Next Address,
0x46
// DMA Count,
0x47
// DMA Current Count, DSP Master DMA
0x48
// DMA Address,
0x49
// DMA Next Address,
0x4A
// DMA Count,
0x4B
// DMA Current Count, Fifo0 Transmit
0x4C
// DMA Address,
0x4D
// DMA Next Address,
0x4E
// DMA Count,
0x4F
// DMA Current Count, Fifo0 Receive
DSP Master DMA
DSP Master DMA
DSP Master DMA
Fifo0 Transmit
Fifo0 Transmit
Fifo0 Transmit
Fifo0 Receive
Fifo0 Receive
Fifo0 Receive
Advertisement
