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ADSP-2192 Peripheral Device Control Registers
Table B-2. Register Group Descriptions (Continued)
Page
Addresses
0x05
0x00-0x7E
0x06
0x00-0x7E
0x07
Reserved
0x08
0x00-0x7F
0x80-0x87
0x88-0x8A
0x09
0x00-0xFF
0x0A
0x00-0xFF
0x0B
0x00-0xFF
0x0C
0x00-0x4F
0x0D-0xFF
Reserved
1 PCI configuration spaces should be accessed only by the DSP, and only during the boot process.
After the PCI interface has been configured, bit 2 (ConfRdy) of the PCI_CFGCTL register
should be set by the DSP. This allows the PCI interface access to these registers while at the same
time denying the DSP access.
B-12
ADSP-219x/2192 DSP Hardware Reference
Descriptions
AC'97 Codec Register
Space,
Secondary Codec 1
AC'97 Codec Register
Space,
Secondary Codec 2
DMA Address, Count
Registers
DMA Control Registers
PCI Interrupt, Control
Registers
PCI Configuration
Register Space, Function 0
PCI Configuration
Register Space, Function 1
PCI Configuration
Register Space, Function 2
USB DSP Registers
Access
Refer to
permitted by
DSP / PCI / USB
page B-45
DSP / PCI / USB
page B-46
DSP / PCI
page B-46
DSP / PCI
page B-46
DSP / PCI
page B-47
1
page B-56
DSP
/ PCI
1
page B-58
DSP
/ PCI
1
page B-59
DSP
/ PCI
DSP / USB
page B-71
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