Analog Devices ADSP-219 Series Hardware Reference Manual page 72

ADSP-2192 Peripheral Device Control Registers
DSP Register Definitions
For each endpoint, four registers are defined in order to provide a memory
buffer in the DSP. These registers are defined for each endpoint shared by
all interfaces that are defined for a total of 4x8 = 32 registers. These regis-
ters are read/write by the DSP only.
Table B-33. USB DSP Register Definitions
Page
0x0C
0x0C
0x0C
0x0C
0x0C
0x0C
0x0C
0x0C
0x0C
0x0C
0x0C
0x0C
0x0C
0x0C
0x0C
0x0C
0x0C
B-72 ADSP-219x/2192 DSP Hardware Reference
Address Name
0x00-0x03 DSP Memory Buffer Base Addr EP4
0x04-0x05 DSP Memory Buffer Size EP4
0x06-0x07 DSP Memory Buffer RD Offset EP4
0x08-0x09 DSP Memory Buffer WR Offset EP4
0x10-0x13 DSP Memory Buffer Base Addr EP5
0x14-0x15 DSP Memory Buffer Size EP5
0x16-0x17 DSP Memory Buffer RD Offset EP5
0x18-0x19 DSP Memory Buffer WR Offset EP5
0x20-0x23 DSP Memory Buffer Base Addr EP6
0x24-0x25 DSP Memory Buffer Size EP6
0x26-0x27 DSP Memory Buffer RD Offset EP6
0x28-0x29 DSP Memory Buffer WR Offset EP6
0x30-0x33 DSP Memory Buffer Base Addr EP7
0x34-0x35 DSP Memory Buffer Size EP7
0x36-0x37 DSP Memory Buffer RD Offset EP7
0x38-0x39 DSP Memory Buffer WR Offset EP7
0x40-0x43 DSP Memory Buffer Base Addr EP8