Analog Devices ADSP-219 Series Hardware Reference Manual page 97

#define SCTL_SSEL2 MK_BMSK_(SCTL_SSEL2_P) // AC'97 Slot Select
#define SCTL_SSEL1 MK_BMSK_(SCTL_SSEL1_P) // AC'97 Slot Select
#define SCTL_SSEL0 MK_BMSK_(SCTL_SSEL0_P) // AC'97 Slot Select
#define SCTL_FIP2 MK_BMSK_(SCTL_FIP2_P ) // AC'97 FIFO Interrupt Position
#define SCTL_FIP1 MK_BMSK_(SCTL_FIP1_P ) // AC'97 FIFO Interrupt Position
#define SCTL_FIP0 MK_BMSK_(SCTL_FIP0_P ) // AC'97 FIFO Interrupt Position
#define SCTL_SDEN MK_BMSK_(SCTL_SDEN_P )
#define SCTL_FULL MK_BMSK_(SCTL_FULL_P )
#define SCTL_EMPTY MK_BMSK_(SCTL_EMPTY_P)
#define SCTL_FLOW MK_BMSK_(SCTL_FLOW_P )
// write-one-clear
//----------------------------------------------------------------------
//
//----------------------------------------------------------------------
// Chip Control Registers (DSP IOPAGE=0x00)
#define SYSCON
#define PWRCFG0
#define PWRCFG1
#define PWRCFG2
#define PWRP0
#define PWRP1
#define PLLCTL
#define REVID
//**************************************************
// SYSCON register
//**************************************************
// Bit Positions
#define SCON_PCIRST_P 15 // PCI Reset
#define SCON_VAUX_P 14 // Vaux Present
#define SCON_PCI_5V_P 13 // PCI 5V level
#define SCON_BUS1_P 11 // Bus Mode
#define SCON_BUS0_P 10 // Bus Mode
#define SCON_CRST1_P 9 // Chip Reset Source
#define SCON_CRST0_P 8 // Chip Reset Source
#define SCON_REGD_P
#define SCON_VXPD_P 6
#define SCON_VXPW_P 5
#define SCON_ACVX_P 4 // AC'97 External Devices Vaux Powered
#define SCON_XON_P 3 // XTAL Force On
ADSP-219x/2192 DSP Hardware Reference
ADSP-2192 DSP Peripheral Registers
I/O Processor Register Map
0x00 // Chip Mode/Status Register
0x02 // Function 0 Power Management
0x04 // Function 1 Power Management
0x06 // Function 2 Power Management
0x08 // DSP 0 Interrupt/Power down
0x0A // DSP 1 Interrupt/Power down
0x0C // DSP PLL Control
0x0E // ADSP-2192 Revision ID (read only)
7 // 2.5V Regulator Control Disable
// Vaux Policy for AC'97 Pad Drivers
// Vaux Policy for AC'97 Pad Well Bias
// AC'97 Port DMA Enable
// FIFO Full, read-only
// FIFO Empty, read-only
// FIFO Over/Underflow, sticky,
B-97