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DSP Peripherals Architecture
Figure B-1
shows the DSP's on-chip peripherals, which include the Host
port (PCI or USB), AC'97 port, JTAG test and emulation port, flags, and
interrupt controller.
,17(5 5837 &21752//(5
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;
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3;
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, 1387
5(*, 67(56
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5(*, 67(56
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!# $$ # !
Figure B-1. ADSP-2192 Dual-Core DSP Block Diagram
The ADSP-2192 can respond to up to fourteen interrupts at any given
time. A list of these interrupts can be found in the table
for an ADSP-2192 DSP Core" on page
The AC'97 codec port on the ADSP-2192 provides a complete synchro-
nous, full-duplex serial interface. This interface completely supports the
AC'97 standard.
The ADSP-2192 provides up to eight general-purpose I/O pins, which are
programmable as either inputs or outputs. These pins are dedicated gen-
eral-purpose programmable flag pins.
ADSP-2192 DSP Peripheral Registers
3
6+$5('
0(025<
0(025<
. 30
. '0
. '0
%227 520
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&25(
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3 '0$
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6+$5(' '63
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), )26
5(*, 67(56
*3 ,2 3,16
6(5,$/ 3257
237,21$/
$&
6(5,$/
&203/,$17
((3520
ADSP-219x/2192 DSP Hardware Reference
3
0(025<
. 30
. '0
%227 520
'$7$
$''5
'$7$
'$7$
$''5 '$7$
3 '0$
&21752//(5
),)26
+267 3257
-7$*
3&,
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25
3257
86%
6-14.
!# $$ # !
"Interrupt Vectors
B-3
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