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ADSP-2192 Peripheral Device Control Registers
Within the Power Management section of the configuration blocks, there
are a few interactions. The part will stay in the highest power state
between the three functions. Thus if a modem is requested to be powered
down to state
D2,
will remain in state
power state, they can only respond to configuration accesses, regardless of
the power state of the other functions. Similarly, when a function transi-
D3hot
tions from
re-initialized. Each function has a separate PME enable and PME status
bit. Whenever possible, the hardware will identify Function 0 wakeup
from wakeup and set the appropriate PME status. When no determination
is possible, both PME status bits will be set.
PCI Configuration Register Space, Function 0
PCI Configuration Spaces should only be accessed by the DSP, and only
during the boot process. After the PCI interface has been configured, bit 2
PCI_CFGCTL
of the
the PCI interface access to these registers while at the same time denying
the DSP access.
Access to these registers is controlled by the PCI RDY bit in the
Chip Mode/Status Register (Page 0x00, Address 0x00).
Table B-25. Function 0 Registers
Register Name
PCI_CFG0_VID
PCI_CFG0_DID
B-56
ADSP-219x/2192 DSP Hardware Reference
but Function 0 is set for power state
D0
. When one or the other of the functions is in a low
D0
to
, that function's configuration space will be
ConfRdy
register (
) should be set by the DSP. This allows
Description
PCI
Address
Config0 Vendor
0x01-0x00
ID
Config0 Device
0x03-0x02
ID
D0
, the overall chip
USB
DSP
Address
I/O
Page
n/a
0x09
n/a
0x09
DSP
I/O
Address
0x00
0x02
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