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Peripheral Device Register Groups
Peripheral Device Register Groups
The registers that control FIFO DMA transfers are accessible only from
within the DSP. They are defined as part of the Core Register Space.
Summary
Each of the DSPs integrated within the ADSP-2192 and the interfaces
(PCI, USB Sub-ISA, Cardbus) needs to be capable of controlling and
monitoring a variety of registers external to the DSP core. This section
describes how the DSPs access these Peripheral Device Control (PDC)
registers. The operation of the Peripheral Device Control (PDC) Bus that
connects the DSPs and Interfaces to the PDC Registers is also described in
this section.
Writes to AC'97 codec registers are posted, but only one may complete
per AC'97 frame. Up to two writes may be pending at any one time. The
first write completes with zero PDC wait states. A second write launched
immediately after the first incurs PDC wait states equivalent to a few
BITCLK
AC'97
s. A third write in a row blocks for an entire AC'97 frame.
Use the Frame interrupt to time AC'97 codec writes out to one per frame,
assuring that they will all complete with zero wait states.
Reads from AC'97 codec registers must always wait for the data to be
returned. A read must also wait for any pending AC'97 codec register
writes to complete before it can begin. In the best case, a read takes one
full AC'97 frame plus another three AC'97 slots (25.39 µs, or approxi-
mately 3,744 DSP cycles). This is also the typical case when the AC'97
Frame Interrupt is used to time the Read.
The worst case AC'97 read time is four frames plus three slots (87.89 µs,
or approximately 12,960 DSP cycles). This occurs only when there are
already two AC'97 codec register writes pending just after the start of a
frame.
B-4
ADSP-219x/2192 DSP Hardware Reference
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