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USB Endpoint Stall Policy Register
Figure B-8. USB Endpoint Stall Policy Register
15
14
13
12
NK
NK
NK
NK
Contains the base
4-11. The
STALL
as well. This register is read/write by the MCU only.
Table B-41. USB Endpoint Stall Policy Register
ST[3:1]
A value of 1 means the Endpoint is stalled. ST[1] maps to Endpoint 1, ST[2] maps
to Endpoint 2, etc.
TB[3:1]
Toggle bit for Endpoint. Reflects the current state of the DATA toggle bit. ST[1]
maps to Endpoint 1, ST[2] maps to Endpoint 2, etc.
NK[3:0]
Base NAK counter. Determines how many sequential NAKs are issued before send-
ing zero length packet, or a packet less than the maximum packet size, on any given
Endpoint.
FE
FIFO error policy. A value of 1 means: Endpoint FIFO is overrun/underrun, STALL
Endpoint
ADSP-2192 DSP Peripheral Registers
11
10
9
8
7
X
X
X
X
NAK
count and FIFO error policy bits for Endpoints
status and Data toggle bits for Endpoints 1-3 are included
ADSP-219x/2192 DSP Hardware Reference
6
5
4
X
TB3
TB2
TB1
3
2
1
ST3
ST2
ST1
B-81
0
FE
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