Analog Devices ADSP-219 Series Hardware Reference Manual page 59

Table B-26. Function 1 Registers (Continued)
Register Name
PCI_CFG1_PWRMT
PCI Configuration Register Space, Function 2
PCI Configuration Spaces should be accessed only by the DSP, and only
during the boot process. After the PCI interface has been configured, bit 2
PCI_CFGCTL
of the
the PCI interface access to these registers while at the same time denying
the DSP access.
Access to these registers is controlled by the PCI RDY bit in the PCI
Interrupt Control Register (Page 0x08, Address 0xA2). See
"General Purpose I/O (GPIO) Control Registers" on page
Table B-27. Function 2 Registers
Register Name
PCI_CFG2_VID
PCI_CFG2_DID
PCI_CFG2_CCODEL
ADSP-2192 DSP Peripheral Registers
Description PCI
Address
Config1 Power 0x45-0x44
Mgt Capabilities
Bit 15 set, if
Vaux is sensed
valid.
ConfRdy
register ( ) should be set by the DSP. This allows
Description PCI
Address
Config2 Vendor 0x01-0x00
ID
Config2 Device 0x03-0x02
ID
Config2 Class 0x08
Code[7:0],Rev
ID
ADSP-219x/2192 DSP Hardware Reference
USB DSP
Address I/O
Page
n/a 0x0A
USB DSP
Address I/O
Page
n/a 0x0B
n/a 0x0B
n/a 0x0B
DSP
I/O
Address
0x44
B-24.
DSP I/O
Address
0x00
0x02
0x08
B-59