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PCI Control (PCI_CFGCTL) Register
All bits in this register reset to 0.
15
14
13
12
Table B-24. PCI_CFGCTL Register Bit Descriptions
Bit
Bit name
position
1-0
PCIF[1:0]
2
Conf Rdy
4:3
Reserved
5
P2DM0 IEN
6
P2DM1 IEN
7
D2PM0 IEN
8
D2PM1 IEN
ADSP-2192 DSP Peripheral Registers
11
10
9
8
Description
PCI Functions Configured.
00 = One PCI Function enabled
01= Two functions
10= Three functions
Configuration Ready.
When 0, disables PCI accesses to the ADSP-2192 (terminated
with Retry). Must be set to 1 by DSP ROM code after initializing
configuration space.
Once 1, cannot be written to 0.
PCI to DSP Mailbox 0 Transfer Interrupt Enabled.
PCI to DSP Mailbox 1 Transfer Interrupt Enabled.
DSP to PCI Mailbox 0 Transfer Interrupt Enabled.
DSP to PCI Mailbox 1 Transfer Interrupt Enabled.
ADSP-219x/2192 DSP Hardware Reference
7
6
5
4
3
2
1
0
B-53
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